board/amcc/bamboo/bamboo.c

   1 /*
   2  * (C) Copyright 2005-2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <asm/gpio.h>
  27 #include <spd_sdram.h>
  28 #include <ppc440.h>
  29 #include "bamboo.h"
  30
  31 void ext_bus_cntlr_init(void);
  32 void configure_ppc440ep_pins(void);
  33 int is_nand_selected(void);
  34
  35 unsigned char cfg_simulate_spd_eeprom[128];
  36
  37 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX];
  38 #if 0
  39 {          /* GPIO   Alternate1       Alternate2        Alternate3 */
  40     {
  41         /* GPIO Core 0 */
  42         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_0  -> EBC_ADDR(7)      DMA_REQ(2) */
  43         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_1  -> EBC_ADDR(6)      DMA_ACK(2) */
  44         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_2  -> EBC_ADDR(5)      DMA_EOT/TC(2) */
  45         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_3  -> EBC_ADDR(4)      DMA_REQ(3) */
  46         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_4  -> EBC_ADDR(3)      DMA_ACK(3) */
  47         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_5 ................. */
  48         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_6  -> EBC_CS_N(1) */
  49         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_7  -> EBC_CS_N(2) */
  50         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_8  -> EBC_CS_N(3) */
  51         { GPIO0_BASE, GPIO_DIS, GPIO_ALT1 }, /* GPIO0_9  -> EBC_CS_N(4) */
  52         { GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO0_10 -> EBC_CS_N(5) */
  53         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_11 -> EBC_BUS_ERR */
  54         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_12 -> ZII_p0Rxd(0) */
  55         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_13 -> ZII_p0Rxd(1) */
  56         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_14 -> ZII_p0Rxd(2) */
  57         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_15 -> ZII_p0Rxd(3) */
  58         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_16 -> ZII_p0Txd(0) */
  59         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_17 -> ZII_p0Txd(1) */
  60         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_18 -> ZII_p0Txd(2) */
  61         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_19 -> ZII_p0Txd(3) */
  62         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_20 -> ZII_p0Rx_er */
  63         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_21 -> ZII_p0Rx_dv */
  64         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_22 -> ZII_p0RxCrs */
  65         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_23 -> ZII_p0Tx_er */
  66         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_24 -> ZII_p0Tx_en */
  67         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_25 -> ZII_p0Col */
  68         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_26 ->                  USB2D_RXVALID */
  69         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_27 -> EXT_EBC_REQ      USB2D_RXERROR */
  70         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_28 ->                  USB2D_TXVALID */
  71         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_29 -> EBC_EXT_HDLA     USB2D_PAD_SUSPNDM */
  72         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_30 -> EBC_EXT_ACK      USB2D_XCVRSELECT */
  73         { GPIO0_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO0_31 -> EBC_EXR_BUSREQ   USB2D_TERMSELECT */
  74     },
  75     {
  76         /* GPIO Core 1 */
  77         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_0  -> USB2D_OPMODE0 */
  78         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_1  -> USB2D_OPMODE1 */
  79         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_2  -> UART0_DCD_N      UART1_DSR_CTS_N   UART2_SOUT */
  80         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_3  -> UART0_8PIN_DSR_N UART1_RTS_DTR_N   UART2_SIN */
  81         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_4  -> UART0_8PIN_CTS_N                   UART3_SIN */
  82         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_5  -> UART0_RTS_N */
  83         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_6  -> UART0_DTR_N      UART1_SOUT */
  84         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_7  -> UART0_RI_N       UART1_SIN */
  85         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_8  -> UIC_IRQ(0) */
  86         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_9  -> UIC_IRQ(1) */
  87         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_10 -> UIC_IRQ(2) */
  88         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_11 -> UIC_IRQ(3) */
  89         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_12 -> UIC_IRQ(4)       DMA_ACK(1) */
  90         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_13 -> UIC_IRQ(6)       DMA_EOT/TC(1) */
  91         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_14 -> UIC_IRQ(7)       DMA_REQ(0) */
  92         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_15 -> UIC_IRQ(8)       DMA_ACK(0) */
  93         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_16 -> UIC_IRQ(9)       DMA_EOT/TC(0) */
  94         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_17 -> - */
  95         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_18 ->  | */
  96         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_19 ->  | */
  97         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_20 ->  | */
  98         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_21 ->  | */
  99         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_22 ->  | */
 100         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_23 ->   \     Can be unselected thru TraceSelect Bit */
 101         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_24 ->   /        in PowerPC440EP Chip */
 102         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_25 ->  | */
 103         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_26 ->  | */
 104         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_27 ->  | */
 105         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_28 ->  | */
 106         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_29 ->  | */
 107         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_30 ->  | */
 108         { GPIO1_BASE, GPIO_DIS, GPIO_SEL }, /* GPIO1_31 -> - */
 109     }
 110 };
 111 #endif
 112
 113 /*----------------------------------------------------------------------------+
 114   | EBC Devices Characteristics
 115   |   Peripheral Bank Access Parameters       -   EBC0_BnAP
 116   |   Peripheral Bank Configuration Register  -   EBC0_BnCR
 117   +----------------------------------------------------------------------------*/
 118 /* Small Flash */
 119 #define EBC0_BNAP_SMALL_FLASH                           \
 120         EBC0_BNAP_BME_DISABLED                  |       \
 121         EBC0_BNAP_TWT_ENCODE(6)                 |       \
 122         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 123         EBC0_BNAP_OEN_ENCODE(1)                 |       \
 124         EBC0_BNAP_WBN_ENCODE(1)                 |       \
 125         EBC0_BNAP_WBF_ENCODE(3)                 |       \
 126         EBC0_BNAP_TH_ENCODE(1)                  |       \
 127         EBC0_BNAP_RE_ENABLED                    |       \
 128         EBC0_BNAP_SOR_DELAYED                   |       \
 129         EBC0_BNAP_BEM_WRITEONLY                 |       \
 130         EBC0_BNAP_PEN_DISABLED
 131
 132 #define EBC0_BNCR_SMALL_FLASH_CS0                       \
 133         EBC0_BNCR_BAS_ENCODE(0xFFF00000)        |       \
 134         EBC0_BNCR_BS_1MB                        |       \
 135         EBC0_BNCR_BU_RW                         |       \
 136         EBC0_BNCR_BW_8BIT
 137
 138 #define EBC0_BNCR_SMALL_FLASH_CS4                       \
 139         EBC0_BNCR_BAS_ENCODE(0x87F00000)        |       \
 140         EBC0_BNCR_BS_1MB                        |       \
 141         EBC0_BNCR_BU_RW                         |       \
 142         EBC0_BNCR_BW_8BIT
 143
 144 /* Large Flash or SRAM */
 145 #define EBC0_BNAP_LARGE_FLASH_OR_SRAM                   \
 146         EBC0_BNAP_BME_DISABLED                  |       \
 147         EBC0_BNAP_TWT_ENCODE(8)                 |       \
 148         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 149         EBC0_BNAP_OEN_ENCODE(1)                 |       \
 150         EBC0_BNAP_WBN_ENCODE(1)                 |       \
 151         EBC0_BNAP_WBF_ENCODE(1)                 |       \
 152         EBC0_BNAP_TH_ENCODE(2)                  |       \
 153         EBC0_BNAP_SOR_DELAYED                   |       \
 154         EBC0_BNAP_BEM_RW                        |       \
 155         EBC0_BNAP_PEN_DISABLED
 156
 157 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0               \
 158         EBC0_BNCR_BAS_ENCODE(0xFF800000)        |       \
 159         EBC0_BNCR_BS_8MB                        |       \
 160         EBC0_BNCR_BU_RW                         |       \
 161         EBC0_BNCR_BW_16BIT
 162
 163
 164 #define EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4               \
 165         EBC0_BNCR_BAS_ENCODE(0x87800000)        |       \
 166         EBC0_BNCR_BS_8MB                        |       \
 167         EBC0_BNCR_BU_RW                         |       \
 168         EBC0_BNCR_BW_16BIT
 169
 170 /* NVRAM - FPGA */
 171 #define EBC0_BNAP_NVRAM_FPGA                            \
 172         EBC0_BNAP_BME_DISABLED                  |       \
 173         EBC0_BNAP_TWT_ENCODE(9)                 |       \
 174         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 175         EBC0_BNAP_OEN_ENCODE(1)                 |       \
 176         EBC0_BNAP_WBN_ENCODE(1)                 |       \
 177         EBC0_BNAP_WBF_ENCODE(0)                 |       \
 178         EBC0_BNAP_TH_ENCODE(2)                  |       \
 179         EBC0_BNAP_RE_ENABLED                    |       \
 180         EBC0_BNAP_SOR_DELAYED                   |       \
 181         EBC0_BNAP_BEM_WRITEONLY                 |       \
 182         EBC0_BNAP_PEN_DISABLED
 183
 184 #define EBC0_BNCR_NVRAM_FPGA_CS5                        \
 185         EBC0_BNCR_BAS_ENCODE(0x80000000)        |       \
 186         EBC0_BNCR_BS_1MB                        |       \
 187         EBC0_BNCR_BU_RW                         |       \
 188         EBC0_BNCR_BW_8BIT
 189
 190 /* Nand Flash */
 191 #define EBC0_BNAP_NAND_FLASH                            \
 192         EBC0_BNAP_BME_DISABLED                  |       \
 193         EBC0_BNAP_TWT_ENCODE(3)                 |       \
 194         EBC0_BNAP_CSN_ENCODE(0)                 |       \
 195         EBC0_BNAP_OEN_ENCODE(0)                 |       \
 196         EBC0_BNAP_WBN_ENCODE(0)                 |       \
 197         EBC0_BNAP_WBF_ENCODE(0)                 |       \
 198         EBC0_BNAP_TH_ENCODE(1)                  |       \
 199         EBC0_BNAP_RE_ENABLED                    |       \
 200         EBC0_BNAP_SOR_NOT_DELAYED               |       \
 201         EBC0_BNAP_BEM_RW                        |       \
 202         EBC0_BNAP_PEN_DISABLED
 203
 204
 205 #define EBC0_BNCR_NAND_FLASH_CS0        0xB8400000
 206
 207 /* NAND0 */
 208 #define EBC0_BNCR_NAND_FLASH_CS1                        \
 209         EBC0_BNCR_BAS_ENCODE(0x90000000)        |       \
 210         EBC0_BNCR_BS_1MB                        |       \
 211         EBC0_BNCR_BU_RW                         |       \
 212         EBC0_BNCR_BW_32BIT
 213 /* NAND1 - Bank2 */
 214 #define EBC0_BNCR_NAND_FLASH_CS2                        \
 215         EBC0_BNCR_BAS_ENCODE(0x94000000)        |       \
 216         EBC0_BNCR_BS_1MB                        |       \
 217         EBC0_BNCR_BU_RW                         |       \
 218         EBC0_BNCR_BW_32BIT
 219
 220 /* NAND1 - Bank3 */
 221 #define EBC0_BNCR_NAND_FLASH_CS3                        \
 222         EBC0_BNCR_BAS_ENCODE(0x94000000)        |       \
 223         EBC0_BNCR_BS_1MB                        |       \
 224         EBC0_BNCR_BU_RW                         |       \
 225         EBC0_BNCR_BW_32BIT
 226
 227 int board_early_init_f(void)
 228 {
 229         ext_bus_cntlr_init();
 230
 231         /*--------------------------------------------------------------------
 232          * Setup the interrupt controller polarities, triggers, etc.
 233          *-------------------------------------------------------------------*/
 234         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 235         mtdcr(uic0er, 0x00000000);      /* disable all */
 236         mtdcr(uic0cr, 0x00000009);      /* ATI & UIC1 crit are critical */
 237         mtdcr(uic0pr, 0xfffffe13);      /* per ref-board manual */
 238         mtdcr(uic0tr, 0x01c00008);      /* per ref-board manual */
 239         mtdcr(uic0vr, 0x00000001);      /* int31 highest, base=0x000 */
 240         mtdcr(uic0sr, 0xffffffff);      /* clear all */
 241
 242         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 243         mtdcr(uic1er, 0x00000000);      /* disable all */
 244         mtdcr(uic1cr, 0x00000000);      /* all non-critical */
 245         mtdcr(uic1pr, 0xffffe0ff);      /* per ref-board manual */
 246         mtdcr(uic1tr, 0x00ffc000);      /* per ref-board manual */
 247         mtdcr(uic1vr, 0x00000001);      /* int31 highest, base=0x000 */
 248         mtdcr(uic1sr, 0xffffffff);      /* clear all */
 249
 250         /*--------------------------------------------------------------------
 251          * Setup the GPIO pins
 252          *-------------------------------------------------------------------*/
 253         out32(GPIO0_OSRL,  0x00000400);
 254         out32(GPIO0_OSRH,  0x00000000);
 255         out32(GPIO0_TSRL,  0x00000400);
 256         out32(GPIO0_TSRH,  0x00000000);
 257         out32(GPIO0_ISR1L, 0x00000000);
 258         out32(GPIO0_ISR1H, 0x00000000);
 259         out32(GPIO0_ISR2L, 0x00000000);
 260         out32(GPIO0_ISR2H, 0x00000000);
 261         out32(GPIO0_ISR3L, 0x00000000);
 262         out32(GPIO0_ISR3H, 0x00000000);
 263
 264         out32(GPIO1_OSRL,  0x0C380000);
 265         out32(GPIO1_OSRH,  0x00000000);
 266         out32(GPIO1_TSRL,  0x0C380000);
 267         out32(GPIO1_TSRH,  0x00000000);
 268         out32(GPIO1_ISR1L, 0x0FC30000);
 269         out32(GPIO1_ISR1H, 0x00000000);
 270         out32(GPIO1_ISR2L, 0x0C010000);
 271         out32(GPIO1_ISR2H, 0x00000000);
 272         out32(GPIO1_ISR3L, 0x01400000);
 273         out32(GPIO1_ISR3H, 0x00000000);
 274
 275         configure_ppc440ep_pins();
 276
 277         return 0;
 278 }
 279
 280 int checkboard(void)
 281 {
 282         char *s = getenv("serial#");
 283
 284         printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
 285         if (s != NULL) {
 286                 puts(", serial# ");
 287                 puts(s);
 288         }
 289         putc('\n');
 290
 291         return (0);
 292 }
 293
 294 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
 295 /*************************************************************************
 296  *
 297  * init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
 298  *
 299  * Fixed memory is composed of :
 300  *      MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266,
 301  *      13 row add bits, 10 column add bits (but 12 row used only).
 302  *      ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266,
 303  *      12 row add bits, 10 column add bits.
 304  *      Prepare a subset (only the used ones) of SPD data
 305  *
 306  *      Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of
 307  *      the corresponding bank is divided by 2 due to number of Row addresses
 308  *      12 in the ECC module
 309  *
 310  *  Assumes:    64 MB, ECC, non-registered
 311  *              PLB @ 133 MHz
 312  *
 313  ************************************************************************/
 314 static void init_spd_array(void)
 315 {
 316         cfg_simulate_spd_eeprom[8]     = 0x04;    /* 2.5 Volt */
 317         cfg_simulate_spd_eeprom[2]     = 0x07;    /* DDR ram */
 318
 319 #ifdef CONFIG_DDR_ECC
 320         cfg_simulate_spd_eeprom[11]    = 0x02;    /* ECC ON : 02 OFF : 00 */
 321         cfg_simulate_spd_eeprom[31]    = 0x08;    /* bankSizeID: 32MB */
 322         cfg_simulate_spd_eeprom[3]     = 0x0C;    /* num Row Addr: 12 */
 323 #else
 324         cfg_simulate_spd_eeprom[11]    = 0x00;    /* ECC ON : 02 OFF : 00 */
 325         cfg_simulate_spd_eeprom[31]    = 0x10;    /* bankSizeID: 64MB */
 326         cfg_simulate_spd_eeprom[3]     = 0x0D;    /* num Row Addr: 13 */
 327 #endif
 328
 329         cfg_simulate_spd_eeprom[4]     = 0x09;    /* numColAddr: 9  */
 330         cfg_simulate_spd_eeprom[5]     = 0x01;    /* numBanks: 1 */
 331         cfg_simulate_spd_eeprom[0]     = 0x80;    /* number of SPD bytes used: 128 */
 332         cfg_simulate_spd_eeprom[1]     = 0x08;    /*  total number bytes in SPD device = 256 */
 333         cfg_simulate_spd_eeprom[21]    = 0x00;    /* not registered: 0  registered : 0x02*/
 334         cfg_simulate_spd_eeprom[6]     = 0x20;    /* Module data width: 32 bits */
 335         cfg_simulate_spd_eeprom[7]     = 0x00;    /* Module data width continued: +0 */
 336         cfg_simulate_spd_eeprom[15]    = 0x01;    /* wcsbc = 1 */
 337         cfg_simulate_spd_eeprom[27]    = 0x50;    /* tRpNs = 20 ns  */
 338         cfg_simulate_spd_eeprom[29]    = 0x50;    /* tRcdNs = 20 ns */
 339
 340         cfg_simulate_spd_eeprom[30]    = 45;      /* tRasNs */
 341
 342         cfg_simulate_spd_eeprom[18]    = 0x0C;    /* casBit (2,2.5) */
 343
 344         cfg_simulate_spd_eeprom[9]     = 0x75;    /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */
 345         cfg_simulate_spd_eeprom[23]    = 0xA0;    /* SDRAM Cycle Time (cas latency 2) = 10 ns */
 346         cfg_simulate_spd_eeprom[25]    = 0x00;    /* SDRAM Cycle Time (cas latency 1.5) = N.A */
 347         cfg_simulate_spd_eeprom[12]    = 0x82;    /* refresh Rate Type: Normal (15.625us) + Self refresh */
 348 }
 349 #endif
 350
 351 long int initdram (int board_type)
 352 {
 353 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
 354         long dram_size;
 355
 356         /*
 357          * First write simulated values in eeprom array for onboard bank 0
 358          */
 359         init_spd_array();
 360
 361         dram_size = spd_sdram();
 362
 363         return dram_size;
 364 #else
 365         return CFG_MBYTES_SDRAM << 20;
 366 #endif
 367 }
 368
 369 #if defined(CFG_DRAM_TEST)
 370 int testdram(void)
 371 {
 372         unsigned long *mem = (unsigned long *)0;
 373         const unsigned long kend = (1024 / sizeof(unsigned long));
 374         unsigned long k, n;
 375
 376         mtmsr(0);
 377
 378         for (k = 0; k < CFG_KBYTES_SDRAM;
 379              ++k, mem += (1024 / sizeof(unsigned long))) {
 380                 if ((k & 1023) == 0) {
 381                         printf("%3d MB\r", k / 1024);
 382                 }
 383
 384                 memset(mem, 0xaaaaaaaa, 1024);
 385                 for (n = 0; n < kend; ++n) {
 386                         if (mem[n] != 0xaaaaaaaa) {
 387                                 printf("SDRAM test fails at: %08x\n",
 388                                        (uint) & mem[n]);
 389                                 return 1;
 390                         }
 391                 }
 392
 393                 memset(mem, 0x55555555, 1024);
 394                 for (n = 0; n < kend; ++n) {
 395                         if (mem[n] != 0x55555555) {
 396                                 printf("SDRAM test fails at: %08x\n",
 397                                        (uint) & mem[n]);
 398                                 return 1;
 399                         }
 400                 }
 401         }
 402         printf("SDRAM test passes\n");
 403         return 0;
 404 }
 405 #endif
 406
 407 /*************************************************************************
 408  *  pci_pre_init
 409  *
 410  *  This routine is called just prior to registering the hose and gives
 411  *  the board the opportunity to check things. Returning a value of zero
 412  *  indicates that things are bad & PCI initialization should be aborted.
 413  *
 414  *      Different boards may wish to customize the pci controller structure
 415  *      (add regions, override default access routines, etc) or perform
 416  *      certain pre-initialization actions.
 417  *
 418  ************************************************************************/
 419 #if defined(CONFIG_PCI)
 420 int pci_pre_init(struct pci_controller *hose)
 421 {
 422         unsigned long addr;
 423
 424         /*-------------------------------------------------------------------------+
 425           | Set priority for all PLB3 devices to 0.
 426           | Set PLB3 arbiter to fair mode.
 427           +-------------------------------------------------------------------------*/
 428         mfsdr(sdr_amp1, addr);
 429         mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
 430         addr = mfdcr(plb3_acr);
 431         mtdcr(plb3_acr, addr | 0x80000000);
 432
 433         /*-------------------------------------------------------------------------+
 434           | Set priority for all PLB4 devices to 0.
 435           +-------------------------------------------------------------------------*/
 436         mfsdr(sdr_amp0, addr);
 437         mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
 438         addr = mfdcr(plb4_acr) | 0xa0000000;    /* Was 0x8---- */
 439         mtdcr(plb4_acr, addr);
 440
 441         /*-------------------------------------------------------------------------+
 442           | Set Nebula PLB4 arbiter to fair mode.
 443           +-------------------------------------------------------------------------*/
 444         /* Segment0 */
 445         addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
 446         addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
 447         addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
 448         addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
 449         mtdcr(plb0_acr, addr);
 450
 451         /* Segment1 */
 452         addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
 453         addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
 454         addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
 455         addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
 456         mtdcr(plb1_acr, addr);
 457
 458         return 1;
 459 }
 460 #endif /* defined(CONFIG_PCI) */
 461
 462 /*************************************************************************
 463  *  pci_target_init
 464  *
 465  *      The bootstrap configuration provides default settings for the pci
 466  *      inbound map (PIM). But the bootstrap config choices are limited and
 467  *      may not be sufficient for a given board.
 468  *
 469  ************************************************************************/
 470 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 471 void pci_target_init(struct pci_controller *hose)
 472 {
 473         /*--------------------------------------------------------------------------+
 474          * Set up Direct MMIO registers
 475          *--------------------------------------------------------------------------*/
 476         /*--------------------------------------------------------------------------+
 477           | PowerPC440 EP PCI Master configuration.
 478           | Map one 1Gig range of PLB/processor addresses to PCI memory space.
 479           |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
 480           |   Use byte reversed out routines to handle endianess.
 481           | Make this region non-prefetchable.
 482           +--------------------------------------------------------------------------*/
 483         out32r(PCIX0_PMM0MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 484         out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);  /* PMM0 Local Address */
 485         out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);       /* PMM0 PCI Low Address */
 486         out32r(PCIX0_PMM0PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 487         out32r(PCIX0_PMM0MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 488
 489         out32r(PCIX0_PMM1MA, 0x00000000);       /* PMM0 Mask/Attribute - disabled b4 setting */
 490         out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
 491         out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);      /* PMM0 PCI Low Address */
 492         out32r(PCIX0_PMM1PCIHA, 0x00000000);    /* PMM0 PCI High Address */
 493         out32r(PCIX0_PMM1MA, 0xE0000001);       /* 512M + No prefetching, and enable region */
 494
 495         out32r(PCIX0_PTM1MS, 0x00000001);       /* Memory Size/Attribute */
 496         out32r(PCIX0_PTM1LA, 0);        /* Local Addr. Reg */
 497         out32r(PCIX0_PTM2MS, 0);        /* Memory Size/Attribute */
 498         out32r(PCIX0_PTM2LA, 0);        /* Local Addr. Reg */
 499
 500         /*--------------------------------------------------------------------------+
 501          * Set up Configuration registers
 502          *--------------------------------------------------------------------------*/
 503
 504         /* Program the board's subsystem id/vendor id */
 505         pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
 506                               CFG_PCI_SUBSYS_VENDORID);
 507         pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
 508
 509         /* Configure command register as bus master */
 510         pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
 511
 512         /* 240nS PCI clock */
 513         pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
 514
 515         /* No error reporting */
 516         pci_write_config_word(0, PCI_ERREN, 0);
 517
 518         pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 519
 520 }
 521 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 522
 523 /*************************************************************************
 524  *  pci_master_init
 525  *
 526  ************************************************************************/
 527 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 528 void pci_master_init(struct pci_controller *hose)
 529 {
 530         unsigned short temp_short;
 531
 532         /*--------------------------------------------------------------------------+
 533           | Write the PowerPC440 EP PCI Configuration regs.
 534           |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).
 535           |   Enable PowerPC440 EP to act as a PCI memory target (PTM).
 536           +--------------------------------------------------------------------------*/
 537         pci_read_config_word(0, PCI_COMMAND, &temp_short);
 538         pci_write_config_word(0, PCI_COMMAND,
 539                               temp_short | PCI_COMMAND_MASTER |
 540                               PCI_COMMAND_MEMORY);
 541 }
 542 #endif                          /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 543
 544 /*************************************************************************
 545  *  is_pci_host
 546  *
 547  *      This routine is called to determine if a pci scan should be
 548  *      performed. With various hardware environments (especially cPCI and
 549  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 550  *      bit in the strap register, or generic host/adapter assumptions.
 551  *
 552  *      Rather than hard-code a bad assumption in the general 440 code, the
 553  *      440 pci code requires the board to decide at runtime.
 554  *
 555  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 556  *
 557  *
 558  ************************************************************************/
 559 #if defined(CONFIG_PCI)
 560 int is_pci_host(struct pci_controller *hose)
 561 {
 562         /* Bamboo is always configured as host. */
 563         return (1);
 564 }
 565 #endif                          /* defined(CONFIG_PCI) */
 566
 567 /*----------------------------------------------------------------------------+
 568   | is_powerpc440ep_pass1.
 569   +----------------------------------------------------------------------------*/
 570 int is_powerpc440ep_pass1(void)
 571 {
 572         unsigned long pvr;
 573
 574         pvr = get_pvr();
 575
 576         if (pvr == PVR_POWERPC_440EP_PASS1)
 577                 return TRUE;
 578         else if (pvr == PVR_POWERPC_440EP_PASS2)
 579                 return FALSE;
 580         else {
 581                 printf("brdutil error 3\n");
 582                 for (;;)
 583                         ;
 584         }
 585
 586         return(FALSE);
 587 }
 588
 589 /*----------------------------------------------------------------------------+
 590   | is_nand_selected.
 591   +----------------------------------------------------------------------------*/
 592 int is_nand_selected(void)
 593 {
 594 #ifdef CONFIG_BAMBOO_NAND
 595         return TRUE;
 596 #else
 597         return FALSE;
 598 #endif
 599 }
 600
 601 /*----------------------------------------------------------------------------+
 602   | config_on_ebc_cs4_is_small_flash => from EPLD
 603   +----------------------------------------------------------------------------*/
 604 unsigned char config_on_ebc_cs4_is_small_flash(void)
 605 {
 606         /* Not implemented yet => returns constant value */
 607         return TRUE;
 608 }
 609
 610 /*----------------------------------------------------------------------------+
 611   | Ext_bus_cntlr_init.
 612   | Initialize the external bus controller
 613   +----------------------------------------------------------------------------*/
 614 void ext_bus_cntlr_init(void)
 615 {
 616         unsigned long sdr0_pstrp0, sdr0_sdstp1;
 617         unsigned long bootstrap_settings, boot_selection, ebc_boot_size;
 618         int           computed_boot_device = BOOT_DEVICE_UNKNOWN;
 619         unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;
 620         unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;
 621         unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;
 622         unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;
 623         unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;
 624
 625
 626         /*-------------------------------------------------------------------------+
 627           |
 628           |  PART 1 : Initialize EBC Bank 5
 629           |  ==============================
 630           | Bank5 is always associated to the NVRAM/EPLD.
 631           | It has to be initialized prior to other banks settings computation since
 632           | some board registers values may be needed
 633           |
 634           +-------------------------------------------------------------------------*/
 635         /* NVRAM - FPGA */
 636         mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);
 637         mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);
 638
 639         /*-------------------------------------------------------------------------+
 640           |
 641           |  PART 2 : Determine which boot device was selected
 642           |  =========================================
 643           |
 644           |  Read Pin Strap Register in PPC440EP
 645           |  In case of boot from IIC, read Serial Device Strap Register1
 646           |
 647           |  Result can either be :
 648           |   - Boot from EBC 8bits    => SMALL FLASH
 649           |   - Boot from EBC 16bits   => Large Flash or SRAM
 650           |   - Boot from NAND Flash
 651           |   - Boot from PCI
 652           |
 653           +-------------------------------------------------------------------------*/
 654         /* Read Pin Strap Register in PPC440EP */
 655         mfsdr(sdr_pstrp0, sdr0_pstrp0);
 656         bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;
 657
 658         /*-------------------------------------------------------------------------+
 659           |  PPC440EP Pass1
 660           +-------------------------------------------------------------------------*/
 661         if (is_powerpc440ep_pass1() == TRUE) {
 662                 switch(bootstrap_settings) {
 663                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
 664                         /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
 665                         /* Boot from Small Flash */
 666                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 667                         break;
 668                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
 669                         /* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */
 670                         /* Boot from PCI */
 671                         computed_boot_device = BOOT_FROM_PCI;
 672                         break;
 673
 674                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
 675                         /* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */
 676                         /* Boot from Nand Flash */
 677                         computed_boot_device = BOOT_FROM_NAND_FLASH0;
 678                         break;
 679
 680                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
 681                         /* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */
 682                         /* Boot from Small Flash */
 683                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 684                         break;
 685
 686                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
 687                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
 688                         /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
 689                         /* Read Serial Device Strap Register1 in PPC440EP */
 690                         mfsdr(sdr_sdstp1, sdr0_sdstp1);
 691                         boot_selection  = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
 692                         ebc_boot_size   = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
 693
 694                         switch(boot_selection) {
 695                         case SDR0_SDSTP1_BOOT_SEL_EBC:
 696                                 switch(ebc_boot_size) {
 697                                 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
 698                                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 699                                         break;
 700                                 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
 701                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 702                                         break;
 703                                 }
 704                                 break;
 705
 706                         case SDR0_SDSTP1_BOOT_SEL_PCI:
 707                                 computed_boot_device = BOOT_FROM_PCI;
 708                                 break;
 709
 710                         case SDR0_SDSTP1_BOOT_SEL_NDFC:
 711                                 computed_boot_device = BOOT_FROM_NAND_FLASH0;
 712                                 break;
 713                         }
 714                         break;
 715                 }
 716         }
 717
 718         /*-------------------------------------------------------------------------+
 719           |  PPC440EP Pass2
 720           +-------------------------------------------------------------------------*/
 721         else {
 722                 switch(bootstrap_settings) {
 723                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
 724                         /* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */
 725                         /* Boot from Small Flash */
 726                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 727                         break;
 728                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
 729                         /* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */
 730                         /* Boot from PCI */
 731                         computed_boot_device = BOOT_FROM_PCI;
 732                         break;
 733
 734                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
 735                         /* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */
 736                         /* Boot from Nand Flash */
 737                         computed_boot_device = BOOT_FROM_NAND_FLASH0;
 738                         break;
 739
 740                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:
 741                         /* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */
 742                         /* Boot from Large Flash or SRAM */
 743                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 744                         break;
 745
 746                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
 747                         /* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */
 748                         /* Boot from Large Flash or SRAM */
 749                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 750                         break;
 751
 752                 case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:
 753                         /* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */
 754                         /* Boot from PCI */
 755                         computed_boot_device = BOOT_FROM_PCI;
 756                         break;
 757
 758                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:
 759                 case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:
 760                         /* Default Strap Settings 5-7 */
 761                         /* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */
 762                         /* Read Serial Device Strap Register1 in PPC440EP */
 763                         mfsdr(sdr_sdstp1, sdr0_sdstp1);
 764                         boot_selection  = sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;
 765                         ebc_boot_size   = sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;
 766
 767                         switch(boot_selection) {
 768                         case SDR0_SDSTP1_BOOT_SEL_EBC:
 769                                 switch(ebc_boot_size) {
 770                                 case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
 771                                         computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;
 772                                         break;
 773                                 case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
 774                                         computed_boot_device = BOOT_FROM_SMALL_FLASH;
 775                                         break;
 776                                 }
 777                                 break;
 778
 779                         case SDR0_SDSTP1_BOOT_SEL_PCI:
 780                                 computed_boot_device = BOOT_FROM_PCI;
 781                                 break;
 782
 783                         case SDR0_SDSTP1_BOOT_SEL_NDFC:
 784                                 computed_boot_device = BOOT_FROM_NAND_FLASH0;
 785                                 break;
 786                         }
 787                         break;
 788                 }
 789         }
 790
 791         /*-------------------------------------------------------------------------+
 792           |
 793           |  PART 3 : Compute EBC settings depending on selected boot device
 794           |  ======   ======================================================
 795           |
 796           | Resulting EBC init will be among following configurations :
 797           |
 798           |  - Boot from EBC 8bits => boot from SMALL FLASH selected
 799           |            EBC-CS0     = Small Flash
 800           |            EBC-CS1,2,3 = NAND Flash or
 801           |                         Exp.Slot depending on Soft Config
 802           |            EBC-CS4     = SRAM/Large Flash or
 803           |                         Large Flash/SRAM depending on jumpers
 804           |            EBC-CS5     = NVRAM / EPLD
 805           |
 806           |  - Boot from EBC 16bits => boot from Large Flash or SRAM selected
 807           |            EBC-CS0     = SRAM/Large Flash or
 808           |                          Large Flash/SRAM depending on jumpers
 809           |            EBC-CS1,2,3 = NAND Flash or
 810           |                          Exp.Slot depending on Software Configuration
 811           |            EBC-CS4     = Small Flash
 812           |            EBC-CS5     = NVRAM / EPLD
 813           |
 814           |  - Boot from NAND Flash
 815           |            EBC-CS0     = NAND Flash0
 816           |            EBC-CS1,2,3 = NAND Flash1
 817           |            EBC-CS4     = SRAM/Large Flash or
 818           |                          Large Flash/SRAM depending on jumpers
 819           |            EBC-CS5     = NVRAM / EPLD
 820           |
 821           |    - Boot from PCI
 822           |            EBC-CS0     = ...
 823           |            EBC-CS1,2,3 = NAND Flash or
 824           |                          Exp.Slot depending on Software Configuration
 825           |            EBC-CS4     = SRAM/Large Flash or
 826           |                          Large Flash/SRAM or
 827           |                          Small Flash depending on jumpers
 828           |            EBC-CS5     = NVRAM / EPLD
 829           |
 830           +-------------------------------------------------------------------------*/
 831
 832         switch(computed_boot_device) {
 833                 /*------------------------------------------------------------------------- */
 834         case BOOT_FROM_SMALL_FLASH:
 835                 /*------------------------------------------------------------------------- */
 836                 ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;
 837                 ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;
 838                 if ((is_nand_selected()) == TRUE) {
 839                         /* NAND Flash */
 840                         ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 841                         ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 842                         ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;
 843                         ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;
 844                         ebc0_cs3_bnap_value = 0;
 845                         ebc0_cs3_bncr_value = 0;
 846                 } else {
 847                         /* Expansion Slot */
 848                         ebc0_cs1_bnap_value = 0;
 849                         ebc0_cs1_bncr_value = 0;
 850                         ebc0_cs2_bnap_value = 0;
 851                         ebc0_cs2_bncr_value = 0;
 852                         ebc0_cs3_bnap_value = 0;
 853                         ebc0_cs3_bncr_value = 0;
 854                 }
 855                 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 856                 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
 857
 858                 break;
 859
 860                 /*------------------------------------------------------------------------- */
 861         case BOOT_FROM_LARGE_FLASH_OR_SRAM:
 862                 /*------------------------------------------------------------------------- */
 863                 ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 864                 ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;
 865                 if ((is_nand_selected()) == TRUE) {
 866                         /* NAND Flash */
 867                         ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 868                         ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 869                         ebc0_cs2_bnap_value = 0;
 870                         ebc0_cs2_bncr_value = 0;
 871                         ebc0_cs3_bnap_value = 0;
 872                         ebc0_cs3_bncr_value = 0;
 873                 } else {
 874                         /* Expansion Slot */
 875                         ebc0_cs1_bnap_value = 0;
 876                         ebc0_cs1_bncr_value = 0;
 877                         ebc0_cs2_bnap_value = 0;
 878                         ebc0_cs2_bncr_value = 0;
 879                         ebc0_cs3_bnap_value = 0;
 880                         ebc0_cs3_bncr_value = 0;
 881                 }
 882                 ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
 883                 ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
 884
 885                 break;
 886
 887                 /*------------------------------------------------------------------------- */
 888         case BOOT_FROM_NAND_FLASH0:
 889                 /*------------------------------------------------------------------------- */
 890                 ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
 891                 ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 892
 893                 ebc0_cs1_bnap_value = 0;
 894                 ebc0_cs1_bncr_value = 0;
 895                 ebc0_cs2_bnap_value = 0;
 896                 ebc0_cs2_bncr_value = 0;
 897                 ebc0_cs3_bnap_value = 0;
 898                 ebc0_cs3_bncr_value = 0;
 899
 900                 /* Large Flash or SRAM */
 901                 ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 902                 ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
 903
 904                 break;
 905
 906                 /*------------------------------------------------------------------------- */
 907         case BOOT_FROM_PCI:
 908                 /*------------------------------------------------------------------------- */
 909                 ebc0_cs0_bnap_value = 0;
 910                 ebc0_cs0_bncr_value = 0;
 911
 912                 if ((is_nand_selected()) == TRUE) {
 913                         /* NAND Flash */
 914                         ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
 915                         ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
 916                         ebc0_cs2_bnap_value = 0;
 917                         ebc0_cs2_bncr_value = 0;
 918                         ebc0_cs3_bnap_value = 0;
 919                         ebc0_cs3_bncr_value = 0;
 920                 } else {
 921                         /* Expansion Slot */
 922                         ebc0_cs1_bnap_value = 0;
 923                         ebc0_cs1_bncr_value = 0;
 924                         ebc0_cs2_bnap_value = 0;
 925                         ebc0_cs2_bncr_value = 0;
 926                         ebc0_cs3_bnap_value = 0;
 927                         ebc0_cs3_bncr_value = 0;
 928                 }
 929
 930                 if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {
 931                         /* Small Flash */
 932                         ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;
 933                         ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;
 934                 } else {
 935                         /* Large Flash or SRAM */
 936                         ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;
 937                         ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;
 938                 }
 939
 940                 break;
 941
 942                 /*------------------------------------------------------------------------- */
 943         case BOOT_DEVICE_UNKNOWN:
 944                 /*------------------------------------------------------------------------- */
 945                 /* Error */
 946                 break;
 947
 948         }
 949
 950
 951         /*-------------------------------------------------------------------------+
 952           | Initialize EBC CONFIG
 953           +-------------------------------------------------------------------------*/
 954         mtdcr(ebccfga, xbcfg);
 955         mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN        |
 956               EBC0_CFG_PTD_ENABLED        |
 957               EBC0_CFG_RTC_2048PERCLK     |
 958               EBC0_CFG_EMPL_LOW           |
 959               EBC0_CFG_EMPH_LOW           |
 960               EBC0_CFG_CSTC_DRIVEN        |
 961               EBC0_CFG_BPF_ONEDW          |
 962               EBC0_CFG_EMS_8BIT           |
 963               EBC0_CFG_PME_DISABLED       |
 964               EBC0_CFG_PMT_ENCODE(0)      );
 965
 966         /*-------------------------------------------------------------------------+
 967           | Initialize EBC Bank 0-4
 968           +-------------------------------------------------------------------------*/
 969         /* EBC Bank0 */
 970         mtebc(pb0ap, ebc0_cs0_bnap_value);
 971         mtebc(pb0cr, ebc0_cs0_bncr_value);
 972         /* EBC Bank1 */
 973         mtebc(pb1ap, ebc0_cs1_bnap_value);
 974         mtebc(pb1cr, ebc0_cs1_bncr_value);
 975         /* EBC Bank2 */
 976         mtebc(pb2ap, ebc0_cs2_bnap_value);
 977         mtebc(pb2cr, ebc0_cs2_bncr_value);
 978         /* EBC Bank3 */
 979         mtebc(pb3ap, ebc0_cs3_bnap_value);
 980         mtebc(pb3cr, ebc0_cs3_bncr_value);
 981         /* EBC Bank4 */
 982         mtebc(pb4ap, ebc0_cs4_bnap_value);
 983         mtebc(pb4cr, ebc0_cs4_bncr_value);
 984
 985         return;
 986 }
 987
 988
 989 /*----------------------------------------------------------------------------+
 990   | get_uart_configuration.
 991   +----------------------------------------------------------------------------*/
 992 uart_config_nb_t get_uart_configuration(void)
 993 {
 994         return (L4);
 995 }
 996
 997 /*----------------------------------------------------------------------------+
 998   | set_phy_configuration_through_fpga => to EPLD
 999   +----------------------------------------------------------------------------*/
1000 void set_phy_configuration_through_fpga(zmii_config_t config)
1001 {
1002
1003         unsigned long fpga_selection_reg;
1004
1005         fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;
1006
1007         switch(config)
1008         {
1009         case ZMII_CONFIGURATION_IS_MII:
1010                 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;
1011                 break;
1012         case ZMII_CONFIGURATION_IS_RMII:
1013                 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;
1014                 break;
1015         case ZMII_CONFIGURATION_IS_SMII:
1016                 fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;
1017                 break;
1018         case ZMII_CONFIGURATION_UNKNOWN:
1019         default:
1020                 break;
1021         }
1022         out8(FPGA_SELECTION_1_REG,fpga_selection_reg);
1023
1024 }
1025
1026 /*----------------------------------------------------------------------------+
1027   | scp_selection_in_fpga.
1028   +----------------------------------------------------------------------------*/
1029 void scp_selection_in_fpga(void)
1030 {
1031         unsigned long fpga_selection_2_reg;
1032
1033         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1034         fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;
1035         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1036 }
1037
1038 /*----------------------------------------------------------------------------+
1039   | iic1_selection_in_fpga.
1040   +----------------------------------------------------------------------------*/
1041 void iic1_selection_in_fpga(void)
1042 {
1043         unsigned long fpga_selection_2_reg;
1044
1045         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;
1046         fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;
1047         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1048 }
1049
1050 /*----------------------------------------------------------------------------+
1051   | dma_a_b_selection_in_fpga.
1052   +----------------------------------------------------------------------------*/
1053 void dma_a_b_selection_in_fpga(void)
1054 {
1055         unsigned long fpga_selection_2_reg;
1056
1057         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;
1058         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1059 }
1060
1061 /*----------------------------------------------------------------------------+
1062   | dma_a_b_unselect_in_fpga.
1063   +----------------------------------------------------------------------------*/
1064 void dma_a_b_unselect_in_fpga(void)
1065 {
1066         unsigned long fpga_selection_2_reg;
1067
1068         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;
1069         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1070 }
1071
1072 /*----------------------------------------------------------------------------+
1073   | dma_c_d_selection_in_fpga.
1074   +----------------------------------------------------------------------------*/
1075 void dma_c_d_selection_in_fpga(void)
1076 {
1077         unsigned long fpga_selection_2_reg;
1078
1079         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;
1080         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1081 }
1082
1083 /*----------------------------------------------------------------------------+
1084   | dma_c_d_unselect_in_fpga.
1085   +----------------------------------------------------------------------------*/
1086 void dma_c_d_unselect_in_fpga(void)
1087 {
1088         unsigned long fpga_selection_2_reg;
1089
1090         fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;
1091         out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);
1092 }
1093
1094 /*----------------------------------------------------------------------------+
1095   | usb2_device_selection_in_fpga.
1096   +----------------------------------------------------------------------------*/
1097 void usb2_device_selection_in_fpga(void)
1098 {
1099         unsigned long fpga_selection_1_reg;
1100
1101         fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;
1102         out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1103 }
1104
1105 /*----------------------------------------------------------------------------+
1106   | usb2_device_reset_through_fpga.
1107   +----------------------------------------------------------------------------*/
1108 void usb2_device_reset_through_fpga(void)
1109 {
1110         /* Perform soft Reset pulse */
1111         unsigned long fpga_reset_reg;
1112         int i;
1113
1114         fpga_reset_reg = in8(FPGA_RESET_REG);
1115         out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);
1116         for (i=0; i<500; i++)
1117                 udelay(1000);
1118         out8(FPGA_RESET_REG,fpga_reset_reg);
1119 }
1120
1121 /*----------------------------------------------------------------------------+
1122   | usb2_host_selection_in_fpga.
1123   +----------------------------------------------------------------------------*/
1124 void usb2_host_selection_in_fpga(void)
1125 {
1126         unsigned long fpga_selection_1_reg;
1127
1128         fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;
1129         out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1130 }
1131
1132 /*----------------------------------------------------------------------------+
1133   | ndfc_selection_in_fpga.
1134   +----------------------------------------------------------------------------*/
1135 void ndfc_selection_in_fpga(void)
1136 {
1137         unsigned long fpga_selection_1_reg;
1138
1139         fpga_selection_1_reg  = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;
1140         fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;
1141         fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;
1142         out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);
1143 }
1144
1145 /*----------------------------------------------------------------------------+
1146   | uart_selection_in_fpga.
1147   +----------------------------------------------------------------------------*/
1148 void uart_selection_in_fpga(uart_config_nb_t uart_config)
1149 {
1150         /* FPGA register */
1151         unsigned char   fpga_selection_3_reg;
1152
1153         /* Read FPGA Reagister */
1154         fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);
1155
1156         switch (uart_config)
1157         {
1158         case L1:
1159                 /* ----------------------------------------------------------------------- */
1160                 /* L1 configuration:    UART0 = 8 pins */
1161                 /* ----------------------------------------------------------------------- */
1162                 /* Configure FPGA */
1163                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1164                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;
1165                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1166
1167                 break;
1168
1169         case L2:
1170                 /* ----------------------------------------------------------------------- */
1171                 /* L2 configuration:    UART0 = 4 pins */
1172                 /*                      UART1 = 4 pins */
1173                 /* ----------------------------------------------------------------------- */
1174                 /* Configure FPGA */
1175                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1176                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;
1177                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1178
1179                 break;
1180
1181         case L3:
1182                 /* ----------------------------------------------------------------------- */
1183                 /* L3 configuration:    UART0 = 4 pins */
1184                 /*                      UART1 = 2 pins */
1185                 /*                      UART2 = 2 pins */
1186                 /* ----------------------------------------------------------------------- */
1187                 /* Configure FPGA */
1188                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1189                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;
1190                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1191                 break;
1192
1193         case L4:
1194                 /* Configure FPGA */
1195                 fpga_selection_3_reg    = fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;
1196                 fpga_selection_3_reg    = fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;
1197                 out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);
1198
1199                 break;
1200
1201         default:
1202                 /* Unsupported UART configuration number */
1203                 for (;;)
1204                         ;
1205                 break;
1206
1207         }
1208 }
1209
1210
1211 /*----------------------------------------------------------------------------+
1212   | init_default_gpio
1213   +----------------------------------------------------------------------------*/
1214 void init_default_gpio(void)
1215 {
1216         int i;
1217
1218         /* Init GPIO0 */
1219         for(i=0; i<GPIO_MAX; i++)
1220         {
1221                 gpio_tab[GPIO0][i].add    = GPIO0_BASE;
1222                 gpio_tab[GPIO0][i].in_out = GPIO_DIS;
1223                 gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;
1224         }
1225
1226         /* Init GPIO1 */
1227         for(i=0; i<GPIO_MAX; i++)
1228         {
1229                 gpio_tab[GPIO1][i].add    = GPIO1_BASE;
1230                 gpio_tab[GPIO1][i].in_out = GPIO_DIS;
1231                 gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;
1232         }
1233
1234         /* EBC_CS_N(5) - GPIO0_10 */
1235         gpio_tab[GPIO0][10].in_out    = GPIO_OUT;
1236         gpio_tab[GPIO0][10].alt_nb    = GPIO_ALT1;
1237
1238         /* EBC_CS_N(4) - GPIO0_9 */
1239         gpio_tab[GPIO0][9].in_out    = GPIO_OUT;
1240         gpio_tab[GPIO0][9].alt_nb    = GPIO_ALT1;
1241 }
1242
1243 /*----------------------------------------------------------------------------+
1244   | update_uart_ios
1245   +------------------------------------------------------------------------------
1246   |
1247   | Set UART Configuration in PowerPC440EP
1248   |
1249   | +---------------------------------------------------------------------+
1250   | | Configuartion   |   Connector   | Nb of pins | Pins   | Associated  |
1251   | |    Number       |   Port Name   |  available | naming |   CORE      |
1252   | +-----------------+---------------+------------+--------+-------------+
1253   | |     L1          |   Port_A      |     8      | UART   | UART core 0 |
1254   | +-----------------+---------------+------------+--------+-------------+
1255   | |     L2          |   Port_A      |     4      | UART1  | UART core 0 |
1256   | |    (L2D)        |   Port_B      |     4      | UART2  | UART core 1 |
1257   | +-----------------+---------------+------------+--------+-------------+
1258   | |     L3          |   Port_A      |     4      | UART1  | UART core 0 |
1259   | |    (L3D)        |   Port_B      |     2      | UART2  | UART core 1 |
1260   | |                 |   Port_C      |     2      | UART3  | UART core 2 |
1261   | +-----------------+---------------+------------+--------+-------------+
1262   | |                 |   Port_A      |     2      | UART1  | UART core 0 |
1263   | |     L4          |   Port_B      |     2      | UART2  | UART core 1 |
1264   | |    (L4D)        |   Port_C      |     2      | UART3  | UART core 2 |
1265   | |                 |   Port_D      |     2      | UART4  | UART core 3 |
1266   | +-----------------+---------------+------------+--------+-------------+
1267   |
1268   |  Involved GPIOs
1269   |
1270   | +------------------------------------------------------------------------------+
1271   | |  GPIO   |   Aternate 1     | I/O |  Alternate 2    | I/O | Alternate 3 | I/O |
1272   | +---------+------------------+-----+-----------------+-----+-------------+-----+
1273   | | GPIO1_2 | UART0_DCD_N      |  I  | UART1_DSR_CTS_N |  I  | UART2_SOUT  |  O  |
1274   | | GPIO1_3 | UART0_8PIN_DSR_N |  I  | UART1_RTS_DTR_N |  O  | UART2_SIN   |  I  |
1275   | | GPIO1_4 | UART0_8PIN_CTS_N |  I  | NA              |  NA | UART3_SIN   |  I  |
1276   | | GPIO1_5 | UART0_RTS_N      |  O  | NA              |  NA | UART3_SOUT  |  O  |
1277   | | GPIO1_6 | UART0_DTR_N      |  O  | UART1_SOUT      |  O  | NA          |  NA |
1278   | | GPIO1_7 | UART0_RI_N       |  I  | UART1_SIN       |  I  | NA          |  NA |
1279   | +------------------------------------------------------------------------------+
1280   |
1281   |
1282   +----------------------------------------------------------------------------*/
1283
1284 void update_uart_ios(uart_config_nb_t uart_config)
1285 {
1286         switch (uart_config)
1287         {
1288         case L1:
1289                 /* ----------------------------------------------------------------------- */
1290                 /* L1 configuration:    UART0 = 8 pins */
1291                 /* ----------------------------------------------------------------------- */
1292                 /* Update GPIO Configuration Table */
1293                 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1294                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;
1295
1296                 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1297                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;
1298
1299                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1300                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1301
1302                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1303                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1304
1305                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1306                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;
1307
1308                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1309                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;
1310
1311                 break;
1312
1313         case L2:
1314                 /* ----------------------------------------------------------------------- */
1315                 /* L2 configuration:    UART0 = 4 pins */
1316                 /*                      UART1 = 4 pins */
1317                 /* ----------------------------------------------------------------------- */
1318                 /* Update GPIO Configuration Table */
1319                 gpio_tab[GPIO1][2].in_out = GPIO_IN;
1320                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;
1321
1322                 gpio_tab[GPIO1][3].in_out = GPIO_OUT;
1323                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;
1324
1325                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1326                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1327
1328                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1329                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1330
1331                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1332                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1333
1334                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1335                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1336
1337                 break;
1338
1339         case L3:
1340                 /* ----------------------------------------------------------------------- */
1341                 /* L3 configuration:    UART0 = 4 pins */
1342                 /*                      UART1 = 2 pins */
1343                 /*                      UART2 = 2 pins */
1344                 /* ----------------------------------------------------------------------- */
1345                 /* Update GPIO Configuration Table */
1346                 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1347                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1348
1349                 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1350                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1351
1352                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1353                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;
1354
1355                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1356                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;
1357
1358                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1359                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1360
1361                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1362                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1363
1364                 break;
1365
1366         case L4:
1367                 /* ----------------------------------------------------------------------- */
1368                 /* L4 configuration:    UART0 = 2 pins */
1369                 /*                      UART1 = 2 pins */
1370                 /*                      UART2 = 2 pins */
1371                 /*                      UART3 = 2 pins */
1372                 /* ----------------------------------------------------------------------- */
1373                 /* Update GPIO Configuration Table */
1374                 gpio_tab[GPIO1][2].in_out = GPIO_OUT;
1375                 gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;
1376
1377                 gpio_tab[GPIO1][3].in_out = GPIO_IN;
1378                 gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;
1379
1380                 gpio_tab[GPIO1][4].in_out = GPIO_IN;
1381                 gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;
1382
1383                 gpio_tab[GPIO1][5].in_out = GPIO_OUT;
1384                 gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;
1385
1386                 gpio_tab[GPIO1][6].in_out = GPIO_OUT;
1387                 gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;
1388
1389                 gpio_tab[GPIO1][7].in_out = GPIO_IN;
1390                 gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;
1391
1392                 break;
1393
1394         default:
1395                 /* Unsupported UART configuration number */
1396                 printf("ERROR - Unsupported UART configuration number.\n\n");
1397                 for (;;)
1398                         ;
1399                 break;
1400
1401         }
1402
1403         /* Set input Selection Register on Alt_Receive for UART Input Core */
1404         out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));
1405         out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));
1406         out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));
1407 }
1408
1409 /*----------------------------------------------------------------------------+
1410   | update_ndfc_ios(void).
1411   +----------------------------------------------------------------------------*/
1412 void update_ndfc_ios(void)
1413 {
1414         /* Update GPIO Configuration Table */
1415         gpio_tab[GPIO0][6].in_out = GPIO_OUT;       /* EBC_CS_N(1) */
1416         gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
1417
1418         gpio_tab[GPIO0][7].in_out = GPIO_OUT;       /* EBC_CS_N(2) */
1419         gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1420
1421 #if 0
1422         gpio_tab[GPIO0][7].in_out = GPIO_OUT;       /* EBC_CS_N(3) */
1423         gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
1424 #endif
1425 }
1426
1427 /*----------------------------------------------------------------------------+
1428   | update_zii_ios(void).
1429   +----------------------------------------------------------------------------*/
1430 void update_zii_ios(void)
1431 {
1432         /* Update GPIO Configuration Table */
1433         gpio_tab[GPIO0][12].in_out = GPIO_IN;       /* ZII_p0Rxd(0) */
1434         gpio_tab[GPIO0][12].alt_nb = GPIO_ALT1;
1435
1436         gpio_tab[GPIO0][13].in_out = GPIO_IN;       /* ZII_p0Rxd(1) */
1437         gpio_tab[GPIO0][13].alt_nb = GPIO_ALT1;
1438
1439         gpio_tab[GPIO0][14].in_out = GPIO_IN;       /* ZII_p0Rxd(2) */
1440         gpio_tab[GPIO0][14].alt_nb = GPIO_ALT1;
1441
1442         gpio_tab[GPIO0][15].in_out = GPIO_IN;       /* ZII_p0Rxd(3) */
1443         gpio_tab[GPIO0][15].alt_nb = GPIO_ALT1;
1444
1445         gpio_tab[GPIO0][16].in_out = GPIO_OUT;      /* ZII_p0Txd(0) */
1446         gpio_tab[GPIO0][16].alt_nb = GPIO_ALT1;
1447
1448         gpio_tab[GPIO0][17].in_out = GPIO_OUT;      /* ZII_p0Txd(1) */
1449         gpio_tab[GPIO0][17].alt_nb = GPIO_ALT1;
1450
1451         gpio_tab[GPIO0][18].in_out = GPIO_OUT;      /* ZII_p0Txd(2) */
1452         gpio_tab[GPIO0][18].alt_nb = GPIO_ALT1;
1453
1454         gpio_tab[GPIO0][19].in_out = GPIO_OUT;      /* ZII_p0Txd(3) */
1455         gpio_tab[GPIO0][19].alt_nb = GPIO_ALT1;
1456
1457         gpio_tab[GPIO0][20].in_out = GPIO_IN;       /* ZII_p0Rx_er */
1458         gpio_tab[GPIO0][20].alt_nb = GPIO_ALT1;
1459
1460         gpio_tab[GPIO0][21].in_out = GPIO_IN;       /* ZII_p0Rx_dv */
1461         gpio_tab[GPIO0][21].alt_nb = GPIO_ALT1;
1462
1463         gpio_tab[GPIO0][22].in_out = GPIO_IN;       /* ZII_p0Crs */
1464         gpio_tab[GPIO0][22].alt_nb = GPIO_ALT1;
1465
1466         gpio_tab[GPIO0][23].in_out = GPIO_OUT;      /* ZII_p0Tx_er */
1467         gpio_tab[GPIO0][23].alt_nb = GPIO_ALT1;
1468
1469         gpio_tab[GPIO0][24].in_out = GPIO_OUT;      /* ZII_p0Tx_en */
1470         gpio_tab[GPIO0][24].alt_nb = GPIO_ALT1;
1471
1472         gpio_tab[GPIO0][25].in_out = GPIO_IN;       /* ZII_p0Col */
1473         gpio_tab[GPIO0][25].alt_nb = GPIO_ALT1;
1474
1475 }
1476
1477 /*----------------------------------------------------------------------------+
1478   | update_uic_0_3_irq_ios().
1479   +----------------------------------------------------------------------------*/
1480 void update_uic_0_3_irq_ios(void)
1481 {
1482         gpio_tab[GPIO1][8].in_out = GPIO_IN;        /* UIC_IRQ(0) */
1483         gpio_tab[GPIO1][8].alt_nb = GPIO_ALT1;
1484
1485         gpio_tab[GPIO1][9].in_out = GPIO_IN;        /* UIC_IRQ(1) */
1486         gpio_tab[GPIO1][9].alt_nb = GPIO_ALT1;
1487
1488         gpio_tab[GPIO1][10].in_out = GPIO_IN;       /* UIC_IRQ(2) */
1489         gpio_tab[GPIO1][10].alt_nb = GPIO_ALT1;
1490
1491         gpio_tab[GPIO1][11].in_out = GPIO_IN;       /* UIC_IRQ(3) */
1492         gpio_tab[GPIO1][11].alt_nb = GPIO_ALT1;
1493 }
1494
1495 /*----------------------------------------------------------------------------+
1496   | update_uic_4_9_irq_ios().
1497   +----------------------------------------------------------------------------*/
1498 void update_uic_4_9_irq_ios(void)
1499 {
1500         gpio_tab[GPIO1][12].in_out = GPIO_IN;       /* UIC_IRQ(4) */
1501         gpio_tab[GPIO1][12].alt_nb = GPIO_ALT1;
1502
1503         gpio_tab[GPIO1][13].in_out = GPIO_IN;       /* UIC_IRQ(6) */
1504         gpio_tab[GPIO1][13].alt_nb = GPIO_ALT1;
1505
1506         gpio_tab[GPIO1][14].in_out = GPIO_IN;       /* UIC_IRQ(7) */
1507         gpio_tab[GPIO1][14].alt_nb = GPIO_ALT1;
1508
1509         gpio_tab[GPIO1][15].in_out = GPIO_IN;       /* UIC_IRQ(8) */
1510         gpio_tab[GPIO1][15].alt_nb = GPIO_ALT1;
1511
1512         gpio_tab[GPIO1][16].in_out = GPIO_IN;       /* UIC_IRQ(9) */
1513         gpio_tab[GPIO1][16].alt_nb = GPIO_ALT1;
1514 }
1515
1516 /*----------------------------------------------------------------------------+
1517   | update_dma_a_b_ios().
1518   +----------------------------------------------------------------------------*/
1519 void update_dma_a_b_ios(void)
1520 {
1521         gpio_tab[GPIO1][12].in_out = GPIO_OUT;      /* DMA_ACK(1) */
1522         gpio_tab[GPIO1][12].alt_nb = GPIO_ALT2;
1523
1524         gpio_tab[GPIO1][13].in_out = GPIO_BI;       /* DMA_EOT/TC(1) */
1525         gpio_tab[GPIO1][13].alt_nb = GPIO_ALT2;
1526
1527         gpio_tab[GPIO1][14].in_out = GPIO_IN;       /* DMA_REQ(0) */
1528         gpio_tab[GPIO1][14].alt_nb = GPIO_ALT2;
1529
1530         gpio_tab[GPIO1][15].in_out = GPIO_OUT;      /* DMA_ACK(0) */
1531         gpio_tab[GPIO1][15].alt_nb = GPIO_ALT2;
1532
1533         gpio_tab[GPIO1][16].in_out = GPIO_BI;       /* DMA_EOT/TC(0) */
1534         gpio_tab[GPIO1][16].alt_nb = GPIO_ALT2;
1535 }
1536
1537 /*----------------------------------------------------------------------------+
1538   | update_dma_c_d_ios().
1539   +----------------------------------------------------------------------------*/
1540 void update_dma_c_d_ios(void)
1541 {
1542         gpio_tab[GPIO0][0].in_out = GPIO_IN;        /* DMA_REQ(2) */
1543         gpio_tab[GPIO0][0].alt_nb = GPIO_ALT2;
1544
1545         gpio_tab[GPIO0][1].in_out = GPIO_OUT;       /* DMA_ACK(2) */
1546         gpio_tab[GPIO0][1].alt_nb = GPIO_ALT2;
1547
1548         gpio_tab[GPIO0][2].in_out = GPIO_BI;        /* DMA_EOT/TC(2) */
1549         gpio_tab[GPIO0][2].alt_nb = GPIO_ALT2;
1550
1551         gpio_tab[GPIO0][3].in_out = GPIO_IN;        /* DMA_REQ(3) */
1552         gpio_tab[GPIO0][3].alt_nb = GPIO_ALT2;
1553
1554         gpio_tab[GPIO0][4].in_out = GPIO_OUT;       /* DMA_ACK(3) */
1555         gpio_tab[GPIO0][4].alt_nb = GPIO_ALT2;
1556
1557         gpio_tab[GPIO0][5].in_out = GPIO_BI;        /* DMA_EOT/TC(3) */
1558         gpio_tab[GPIO0][5].alt_nb = GPIO_ALT2;
1559
1560 }
1561
1562 /*----------------------------------------------------------------------------+
1563   | update_ebc_master_ios().
1564   +----------------------------------------------------------------------------*/
1565 void update_ebc_master_ios(void)
1566 {
1567         gpio_tab[GPIO0][27].in_out = GPIO_IN;       /* EXT_EBC_REQ */
1568         gpio_tab[GPIO0][27].alt_nb = GPIO_ALT1;
1569
1570         gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* EBC_EXT_HDLA */
1571         gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1572
1573         gpio_tab[GPIO0][30].in_out = GPIO_OUT;      /* EBC_EXT_ACK */
1574         gpio_tab[GPIO0][30].alt_nb = GPIO_ALT1;
1575
1576         gpio_tab[GPIO0][31].in_out = GPIO_OUT;      /* EBC_EXR_BUSREQ */
1577         gpio_tab[GPIO0][31].alt_nb = GPIO_ALT1;
1578 }
1579
1580 /*----------------------------------------------------------------------------+
1581   | update_usb2_device_ios().
1582   +----------------------------------------------------------------------------*/
1583 void update_usb2_device_ios(void)
1584 {
1585         gpio_tab[GPIO0][26].in_out = GPIO_IN;       /* USB2D_RXVALID */
1586         gpio_tab[GPIO0][26].alt_nb = GPIO_ALT2;
1587
1588         gpio_tab[GPIO0][27].in_out = GPIO_IN;       /* USB2D_RXERROR */
1589         gpio_tab[GPIO0][27].alt_nb = GPIO_ALT2;
1590
1591         gpio_tab[GPIO0][28].in_out = GPIO_OUT;      /* USB2D_TXVALID */
1592         gpio_tab[GPIO0][28].alt_nb = GPIO_ALT2;
1593
1594         gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* USB2D_PAD_SUSPNDM */
1595         gpio_tab[GPIO0][29].alt_nb = GPIO_ALT2;
1596
1597         gpio_tab[GPIO0][30].in_out = GPIO_OUT;      /* USB2D_XCVRSELECT */
1598         gpio_tab[GPIO0][30].alt_nb = GPIO_ALT2;
1599
1600         gpio_tab[GPIO0][31].in_out = GPIO_OUT;      /* USB2D_TERMSELECT */
1601         gpio_tab[GPIO0][31].alt_nb = GPIO_ALT2;
1602
1603         gpio_tab[GPIO1][0].in_out = GPIO_OUT;       /* USB2D_OPMODE0 */
1604         gpio_tab[GPIO1][0].alt_nb = GPIO_ALT1;
1605
1606         gpio_tab[GPIO1][1].in_out = GPIO_OUT;       /* USB2D_OPMODE1 */
1607         gpio_tab[GPIO1][1].alt_nb = GPIO_ALT1;
1608
1609 }
1610
1611 /*----------------------------------------------------------------------------+
1612   | update_pci_patch_ios().
1613   +----------------------------------------------------------------------------*/
1614 void update_pci_patch_ios(void)
1615 {
1616         gpio_tab[GPIO0][29].in_out = GPIO_OUT;      /* EBC_EXT_HDLA */
1617         gpio_tab[GPIO0][29].alt_nb = GPIO_ALT1;
1618 }
1619
1620 /*----------------------------------------------------------------------------+
1621   |   set_chip_gpio_configuration(unsigned char gpio_core)
1622   |   Put the core impacted by clock modification and sharing in reset.
1623   |   Config the select registers to resolve the sharing depending of the config.
1624   |   Configure the GPIO registers.
1625   |
1626   +----------------------------------------------------------------------------*/
1627 void set_chip_gpio_configuration(unsigned char gpio_core)
1628 {
1629         unsigned char i=0, j=0, reg_offset = 0;
1630         unsigned long gpio_reg, gpio_core_add;
1631
1632         /* GPIO config of the GPIOs 0 to 31 */
1633         for (i=0; i<GPIO_MAX; i++, j++)
1634         {
1635                 if (i == GPIO_MAX/2)
1636                 {
1637                         reg_offset = 4;
1638                         j = i-16;
1639                 }
1640
1641                 gpio_core_add = gpio_tab[gpio_core][i].add;
1642
1643                 if ( (gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
1644                      (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1645                 {
1646                         switch (gpio_tab[gpio_core][i].alt_nb)
1647                         {
1648                         case GPIO_SEL:
1649                                 break;
1650
1651                         case GPIO_ALT1:
1652                                 gpio_reg = in32(GPIO_IS1(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1653                                 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1654                                 out32(GPIO_IS1(gpio_core_add+reg_offset), gpio_reg);
1655                                 break;
1656
1657                         case GPIO_ALT2:
1658                                 gpio_reg = in32(GPIO_IS2(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1659                                 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1660                                 out32(GPIO_IS2(gpio_core_add+reg_offset), gpio_reg);
1661                                 break;
1662
1663                         case GPIO_ALT3:
1664                                 gpio_reg = in32(GPIO_IS3(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1665                                 gpio_reg = gpio_reg | (GPIO_IN_SEL >> (j*2));
1666                                 out32(GPIO_IS3(gpio_core_add+reg_offset), gpio_reg);
1667                                 break;
1668                         }
1669                 }
1670                 if ( (gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
1671                      (gpio_tab[gpio_core][i].in_out == GPIO_BI ))
1672                 {
1673
1674                         switch (gpio_tab[gpio_core][i].alt_nb)
1675                         {
1676                         case GPIO_SEL:
1677                                 break;
1678                         case GPIO_ALT1:
1679                                 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1680                                 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1681                                 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1682                                 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1683                                 gpio_reg = gpio_reg | (GPIO_ALT1_SEL >> (j*2));
1684                                 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1685                                 break;
1686                         case GPIO_ALT2:
1687                                 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1688                                 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1689                                 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1690                                 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1691                                 gpio_reg = gpio_reg | (GPIO_ALT2_SEL >> (j*2));
1692                                 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1693                                 break;
1694                         case GPIO_ALT3:
1695                                 gpio_reg = in32(GPIO_OS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1696                                 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1697                                 out32(GPIO_OS(gpio_core_add+reg_offset), gpio_reg);
1698                                 gpio_reg = in32(GPIO_TS(gpio_core_add+reg_offset)) & ~(GPIO_MASK >> (j*2));
1699                                 gpio_reg = gpio_reg | (GPIO_ALT3_SEL >> (j*2));
1700                                 out32(GPIO_TS(gpio_core_add+reg_offset), gpio_reg);
1701                                 break;
1702                         }
1703                 }
1704         }
1705 }
1706
1707 /*----------------------------------------------------------------------------+
1708   | force_bup_core_selection.
1709   +----------------------------------------------------------------------------*/
1710 void force_bup_core_selection(core_selection_t *core_select_P, config_validity_t *config_val_P)
1711 {
1712         /* Pointer invalid */
1713         if (core_select_P == NULL)
1714         {
1715                 printf("Configuration invalid pointer 1\n");
1716                 for (;;)
1717                         ;
1718         }
1719
1720         /* L4 Selection */
1721         *(core_select_P+UART_CORE0)            = CORE_SELECTED;
1722         *(core_select_P+UART_CORE1)            = CORE_SELECTED;
1723         *(core_select_P+UART_CORE2)            = CORE_SELECTED;
1724         *(core_select_P+UART_CORE3)            = CORE_SELECTED;
1725
1726         /* RMII Selection */
1727         *(core_select_P+RMII_SEL)               = CORE_SELECTED;
1728
1729         /* External Interrupt 0-9 selection */
1730         *(core_select_P+UIC_0_3)                = CORE_SELECTED;
1731         *(core_select_P+UIC_4_9)                = CORE_SELECTED;
1732
1733         *(core_select_P+SCP_CORE)               = CORE_SELECTED;
1734         *(core_select_P+DMA_CHANNEL_CD)         = CORE_SELECTED;
1735         *(core_select_P+PACKET_REJ_FUNC_AVAIL)  = CORE_SELECTED;
1736         *(core_select_P+USB1_DEVICE)            = CORE_SELECTED;
1737
1738         if (is_nand_selected()) {
1739                 *(core_select_P+NAND_FLASH)     = CORE_SELECTED;
1740         }
1741
1742         *config_val_P = CONFIG_IS_VALID;
1743
1744 }
1745
1746 /*----------------------------------------------------------------------------+
1747   | configure_ppc440ep_pins.
1748   +----------------------------------------------------------------------------*/
1749 void configure_ppc440ep_pins(void)
1750 {
1751         uart_config_nb_t uart_configuration;
1752         config_validity_t config_val = CONFIG_IS_INVALID;
1753
1754         /* Create Core Selection Table */
1755         core_selection_t ppc440ep_core_selection[MAX_CORE_SELECT_NB] =
1756                 {
1757                         CORE_NOT_SELECTED,      /* IIC_CORE, */
1758                         CORE_NOT_SELECTED,      /* SPC_CORE, */
1759                         CORE_NOT_SELECTED,      /* DMA_CHANNEL_AB, */
1760                         CORE_NOT_SELECTED,      /* UIC_4_9, */
1761                         CORE_NOT_SELECTED,      /* USB2_HOST, */
1762                         CORE_NOT_SELECTED,      /* DMA_CHANNEL_CD, */
1763                         CORE_NOT_SELECTED,      /* USB2_DEVICE, */
1764                         CORE_NOT_SELECTED,      /* PACKET_REJ_FUNC_AVAIL, */
1765                         CORE_NOT_SELECTED,      /* USB1_DEVICE, */
1766                         CORE_NOT_SELECTED,      /* EBC_MASTER, */
1767                         CORE_NOT_SELECTED,      /* NAND_FLASH, */
1768                         CORE_NOT_SELECTED,      /* UART_CORE0, */
1769                         CORE_NOT_SELECTED,      /* UART_CORE1, */
1770                         CORE_NOT_SELECTED,      /* UART_CORE2, */
1771                         CORE_NOT_SELECTED,      /* UART_CORE3, */
1772                         CORE_NOT_SELECTED,      /* MII_SEL, */
1773                         CORE_NOT_SELECTED,      /* RMII_SEL, */
1774                         CORE_NOT_SELECTED,      /* SMII_SEL, */
1775                         CORE_NOT_SELECTED,      /* PACKET_REJ_FUNC_EN */
1776                         CORE_NOT_SELECTED,      /* UIC_0_3 */
1777                         CORE_NOT_SELECTED,      /* USB1_HOST */
1778                         CORE_NOT_SELECTED       /* PCI_PATCH */
1779                 };
1780
1781
1782         /* Table Default Initialisation + FPGA Access */
1783         init_default_gpio();
1784         set_chip_gpio_configuration(GPIO0);
1785         set_chip_gpio_configuration(GPIO1);
1786
1787         /* Update Table */
1788         force_bup_core_selection(ppc440ep_core_selection, &config_val);
1789 #if 0 /* test-only */
1790         /* If we are running PIBS 1, force known configuration */
1791         update_core_selection_table(ppc440ep_core_selection, &config_val);
1792 #endif
1793
1794         /*----------------------------------------------------------------------------+
1795           | SDR + ios table update + fpga initialization
1796           +----------------------------------------------------------------------------*/
1797         unsigned long sdr0_pfc1     = 0;
1798         unsigned long sdr0_usb0     = 0;
1799         unsigned long sdr0_mfr      = 0;
1800
1801         /* PCI Always selected */
1802
1803         /* I2C Selection */
1804         if (ppc440ep_core_selection[IIC_CORE] == CORE_SELECTED)
1805         {
1806                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
1807                 iic1_selection_in_fpga();
1808         }
1809
1810         /* SCP Selection */
1811         if (ppc440ep_core_selection[SCP_CORE] == CORE_SELECTED)
1812         {
1813                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
1814                 scp_selection_in_fpga();
1815         }
1816
1817         /* UIC 0:3 Selection */
1818         if (ppc440ep_core_selection[UIC_0_3] == CORE_SELECTED)
1819         {
1820                 update_uic_0_3_irq_ios();
1821                 dma_a_b_unselect_in_fpga();
1822         }
1823
1824         /* UIC 4:9 Selection */
1825         if (ppc440ep_core_selection[UIC_4_9] == CORE_SELECTED)
1826         {
1827                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_UICIRQ5_SEL;
1828                 update_uic_4_9_irq_ios();
1829         }
1830
1831         /* DMA AB Selection */
1832         if (ppc440ep_core_selection[DMA_CHANNEL_AB] == CORE_SELECTED)
1833         {
1834                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_DIS_MASK) | SDR0_PFC1_DIS_DMAR_SEL;
1835                 update_dma_a_b_ios();
1836                 dma_a_b_selection_in_fpga();
1837         }
1838
1839         /* DMA CD Selection */
1840         if (ppc440ep_core_selection[DMA_CHANNEL_CD] == CORE_SELECTED)
1841         {
1842                 update_dma_c_d_ios();
1843                 dma_c_d_selection_in_fpga();
1844         }
1845
1846         /* EBC Master Selection */
1847         if (ppc440ep_core_selection[EBC_MASTER] == CORE_SELECTED)
1848         {
1849                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_ERE_MASK) | SDR0_PFC1_ERE_EXTR_SEL;
1850                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1851                 update_ebc_master_ios();
1852         }
1853
1854         /* PCI Patch Enable */
1855         if (ppc440ep_core_selection[PCI_PATCH] == CORE_SELECTED)
1856         {
1857                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_EBCHR_SEL;
1858                 update_pci_patch_ios();
1859         }
1860
1861         /* USB2 Host Selection - Not Implemented in PowerPC 440EP Pass1 */
1862         if (ppc440ep_core_selection[USB2_HOST] == CORE_SELECTED)
1863         {
1864                 /* Not Implemented in PowerPC 440EP Pass1-Pass2 */
1865                 printf("Invalid configuration => USB2 Host selected\n");
1866                 for (;;)
1867                         ;
1868                 /*usb2_host_selection_in_fpga(); */
1869         }
1870
1871         /* USB2.0 Device Selection */
1872         if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
1873         {
1874                 update_usb2_device_ios();
1875                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UES_MASK) | SDR0_PFC1_UES_USB2D_SEL;
1876                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_DISABLE;
1877
1878                 mfsdr(sdr_usb0, sdr0_usb0);
1879                 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1880                 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB20D_DEVSEL;
1881                 mtsdr(sdr_usb0, sdr0_usb0);
1882
1883                 usb2_device_selection_in_fpga();
1884         }
1885
1886         /* USB1.1 Device Selection */
1887         if (ppc440ep_core_selection[USB1_DEVICE] == CORE_SELECTED)
1888         {
1889                 mfsdr(sdr_usb0, sdr0_usb0);
1890                 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_USB_DEVSEL_MASK;
1891                 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_USB11D_DEVSEL;
1892                 mtsdr(sdr_usb0, sdr0_usb0);
1893         }
1894
1895         /* USB1.1 Host Selection */
1896         if (ppc440ep_core_selection[USB1_HOST] == CORE_SELECTED)
1897         {
1898                 mfsdr(sdr_usb0, sdr0_usb0);
1899                 sdr0_usb0 = sdr0_usb0 &~SDR0_USB0_LEEN_MASK;
1900                 sdr0_usb0 = sdr0_usb0 | SDR0_USB0_LEEN_ENABLE;
1901                 mtsdr(sdr_usb0, sdr0_usb0);
1902         }
1903
1904         /* NAND Flash Selection */
1905         if (ppc440ep_core_selection[NAND_FLASH] == CORE_SELECTED)
1906         {
1907                 update_ndfc_ios();
1908
1909 #if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
1910                 mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL   |
1911                       SDR0_CUST0_NDFC_ENABLE    |
1912                       SDR0_CUST0_NDFC_BW_8_BIT  |
1913                       SDR0_CUST0_NDFC_ARE_MASK  |
1914                       SDR0_CUST0_CHIPSELGAT_EN1 |
1915                       SDR0_CUST0_CHIPSELGAT_EN2);
1916 #else
1917                 mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL   |
1918                       SDR0_CUST0_NDFC_ENABLE    |
1919                       SDR0_CUST0_NDFC_BW_8_BIT  |
1920                       SDR0_CUST0_NDFC_ARE_MASK  |
1921                       SDR0_CUST0_CHIPSELGAT_EN0 |
1922                       SDR0_CUST0_CHIPSELGAT_EN2);
1923 #endif
1924
1925                 ndfc_selection_in_fpga();
1926         }
1927         else
1928         {
1929                 /* Set Mux on EMAC */
1930                 mtsdr(sdr_cust0, SDR0_CUST0_MUX_EMAC_SEL);
1931         }
1932
1933         /* MII Selection */
1934         if (ppc440ep_core_selection[MII_SEL] == CORE_SELECTED)
1935         {
1936                 update_zii_ios();
1937                 mfsdr(sdr_mfr, sdr0_mfr);
1938                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_MII;
1939                 mtsdr(sdr_mfr, sdr0_mfr);
1940
1941                 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_MII);
1942         }
1943
1944         /* RMII Selection */
1945         if (ppc440ep_core_selection[RMII_SEL] == CORE_SELECTED)
1946         {
1947                 update_zii_ios();
1948                 mfsdr(sdr_mfr, sdr0_mfr);
1949                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
1950                 mtsdr(sdr_mfr, sdr0_mfr);
1951
1952                 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_RMII);
1953         }
1954
1955         /* SMII Selection */
1956         if (ppc440ep_core_selection[SMII_SEL] == CORE_SELECTED)
1957         {
1958                 update_zii_ios();
1959                 mfsdr(sdr_mfr, sdr0_mfr);
1960                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_SMII;
1961                 mtsdr(sdr_mfr, sdr0_mfr);
1962
1963                 set_phy_configuration_through_fpga(ZMII_CONFIGURATION_IS_SMII);
1964         }
1965
1966         /* UART Selection */
1967         uart_configuration = get_uart_configuration();
1968         switch (uart_configuration)
1969         {
1970         case L1:         /* L1 Selection */
1971                 /* UART0 8 pins Only */
1972                 /*sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR; */
1973                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) |SDR0_PFC1_U0ME_CTS_RTS;   /* Chip Pb */
1974                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_8PINS;
1975                 break;
1976         case L2:         /* L2 Selection */
1977                 /* UART0 and UART1 4 pins */
1978                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1979                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1980                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1981                 break;
1982         case L3:         /* L3 Selection */
1983                 /* UART0 4 pins, UART1 and UART2 2 pins */
1984                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1985                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1986                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1987                 break;
1988         case L4:         /* L4 Selection */
1989                 /* UART0, UART1, UART2 and UART3 2 pins */
1990                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_DSR_DTR;
1991                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
1992                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_DSR_DTR;
1993                 break;
1994         }
1995         update_uart_ios(uart_configuration);
1996
1997         /* UART Selection in all cases */
1998         uart_selection_in_fpga(uart_configuration);
1999
2000         /* Packet Reject Function Available */
2001         if (ppc440ep_core_selection[PACKET_REJ_FUNC_AVAIL] == CORE_SELECTED)
2002         {
2003                 /* Set UPR Bit in SDR0_PFC1 Register */
2004                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_UPR_MASK) | SDR0_PFC1_UPR_ENABLE;
2005         }
2006
2007         /* Packet Reject Function Enable */
2008         if (ppc440ep_core_selection[PACKET_REJ_FUNC_EN] == CORE_SELECTED)
2009         {
2010                 mfsdr(sdr_mfr, sdr0_mfr);
2011                 sdr0_mfr = (sdr0_mfr & ~SDR0_MFR_PKT_REJ_MASK) | SDR0_MFR_PKT_REJ_EN;;
2012                 mtsdr(sdr_mfr, sdr0_mfr);
2013         }
2014
2015         /* Perform effective access to hardware */
2016         mtsdr(sdr_pfc1, sdr0_pfc1);
2017         set_chip_gpio_configuration(GPIO0);
2018         set_chip_gpio_configuration(GPIO1);
2019
2020         /* USB2.0 Device Reset must be done after GPIO setting */
2021         if (ppc440ep_core_selection[USB2_DEVICE] == CORE_SELECTED)
2022                 usb2_device_reset_through_fpga();
2023
2024 }