board/advantech/imx8qm_rom7720_a1/spl.c

   1 // SPDX-License-Identifier:     GPL-2.0+
   2 /*
   3  * Copyright 2017-2018 NXP
   4  */
   5 #include <common.h>
   6 #include <dm.h>
   7 #include <image.h>
   8 #include <init.h>
   9 #include <log.h>
  10 #include <spl.h>
  11 #include <fsl_esdhc.h>
  12 #include <asm/global_data.h>
  13
  14 #include <asm/io.h>
  15 #include <asm/gpio.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/sci/sci.h>
  18 #include <asm/arch/imx8-pins.h>
  19 #include <asm/arch/iomux.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #define ESDHC_PAD_CTRL  ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  24                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  25                 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  26                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  27
  28 #define ESDHC_CLK_PAD_CTRL      ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
  29                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  30                 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  31                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  32
  33 #define ENET_INPUT_PAD_CTRL     ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
  34                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  35                 (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
  36                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  37
  38 #define ENET_NORMAL_PAD_CTRL    ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  39                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  40                 (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
  41                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  42
  43 #define FSPI_PAD_CTRL   ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  44                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  45                 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  46                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  47
  48 #define GPIO_PAD_CTRL   ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  49                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  50                 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  51                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  52
  53 #define I2C_PAD_CTRL    ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
  54                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  55                 (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
  56                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  57
  58 #define UART_PAD_CTRL   ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
  59                 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  60                 (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  61                 (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  62 #ifdef CONFIG_FSL_ESDHC
  63
  64 #define USDHC1_CD_GPIO  IMX_GPIO_NR(5, 22)
  65 #define USDHC2_CD_GPIO  IMX_GPIO_NR(4, 12)
  66
  67 static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
  68         {USDHC1_BASE_ADDR, 0, 8},
  69         {USDHC2_BASE_ADDR, 0, 4},
  70         {USDHC3_BASE_ADDR, 0, 4},
  71 };
  72
  73 static iomux_cfg_t emmc0[] = {
  74         SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
  75         SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  76         SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  77         SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  78         SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  79         SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  80         SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  81         SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  82         SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  83         SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  84         SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  85         SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  86 };
  87
  88 static iomux_cfg_t usdhc2_sd[] = {
  89         SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
  90         SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  91         SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  92         SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  93         SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  94         SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  95         SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  96         SC_P_USDHC2_WP   | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  97         SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
  98 };
  99
 100 int board_mmc_init(struct bd_info *bis)
 101 {
 102         int i, ret;
 103
 104         /*
 105          * According to the board_mmc_init() the following map is done:
 106          * (U-Boot device node)    (Physical Port)
 107          * mmc0                    USDHC1
 108          * mmc1                    USDHC2
 109          * mmc2                    USDHC3
 110          */
 111         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 112                 switch (i) {
 113                 case 0:
 114                         ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
 115                         if (ret != SC_ERR_NONE)
 116                                 return ret;
 117
 118                         imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
 119                         init_clk_usdhc(0);
 120                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 121                         break;
 122                 case 1:
 123                         ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
 124                         if (ret != SC_ERR_NONE)
 125                                 return ret;
 126                         ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
 127                         if (ret != SC_ERR_NONE)
 128                                 return ret;
 129
 130                         imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
 131                         init_clk_usdhc(2);
 132                         usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 133                         gpio_request(USDHC2_CD_GPIO, "sd2_cd");
 134                         gpio_direction_input(USDHC2_CD_GPIO);
 135                         break;
 136                 default:
 137                         printf("Warning: you configured more USDHC controllers"
 138                                 "(%d) than supported by the board\n", i + 1);
 139                         return 0;
 140                 }
 141                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 142                 if (ret) {
 143                         printf("Warning: failed to initialize mmc dev %d\n", i);
 144                         return ret;
 145                 }
 146         }
 147
 148         return 0;
 149 }
 150
 151 int board_mmc_getcd(struct mmc *mmc)
 152 {
 153         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 154         int ret = 0;
 155
 156         switch (cfg->esdhc_base) {
 157         case USDHC1_BASE_ADDR:
 158                 ret = 1;
 159                 break;
 160         case USDHC2_BASE_ADDR:
 161                 ret = !gpio_get_value(USDHC1_CD_GPIO);
 162                 break;
 163         case USDHC3_BASE_ADDR:
 164                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 165                 break;
 166         }
 167
 168         return ret;
 169 }
 170
 171 #endif /* CONFIG_FSL_ESDHC */
 172
 173 void spl_board_init(void)
 174 {
 175 #if defined(CONFIG_SPL_SPI)
 176         if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
 177                 if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
 178                         puts("Warning: failed to initialize FSPI0\n");
 179                 }
 180         }
 181 #endif
 182
 183         puts("Normal Boot\n");
 184 }
 185
 186 void spl_board_prepare_for_boot(void)
 187 {
 188 #if defined(CONFIG_SPL_SPI)
 189         if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
 190                 if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
 191                         puts("Warning: failed to turn off FSPI0\n");
 192                 }
 193         }
 194 #endif
 195 }
 196
 197 #ifdef CONFIG_SPL_LOAD_FIT
 198 int board_fit_config_name_match(const char *name)
 199 {
 200         /* Just empty function now - can't decide what to choose */
 201         debug("%s: %s\n", __func__, name);
 202
 203         return 0;
 204 }
 205 #endif
 206
 207 void board_init_f(ulong dummy)
 208 {
 209         /* Clear global data */
 210         memset((void *)gd, 0, sizeof(gd_t));
 211
 212         arch_cpu_init();
 213
 214         board_early_init_f();
 215
 216         timer_init();
 217
 218         preloader_console_init();
 219
 220         /* Clear the BSS. */
 221         memset(__bss_start, 0, __bss_end - __bss_start);
 222
 223         board_init_r(NULL, 0);
 224 }