1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/soc.h>
14 #include <linux/delay.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 /* IO expander I2C device */
19 #define I2C_IO_EXP_ADDR 0x22
20 #define I2C_IO_CFG_REG_0 0x6
21 #define I2C_IO_DATA_OUT_REG_0 0x2
22 #define I2C_IO_REG_0_SATA_OFF 2
23 #define I2C_IO_REG_0_USB_H_OFF 1
25 /* The pin control values are the same for DB and Espressobin */
26 #define PINCTRL_NB_REG_VALUE 0x000173fa
27 #define PINCTRL_SB_REG_VALUE 0x00007a23
29 /* Ethernet switch registers */
30 /* SMI addresses for multi-chip mode */
31 #define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p))
32 #define MVEBU_SW_G2_SMI_ADDR (28)
35 #define MVEBU_SW_SMI_DATA_REG (1)
36 #define MVEBU_SW_SMI_CMD_REG (0)
37 #define SW_SMI_CMD_REG_ADDR_OFF 0
38 #define SW_SMI_CMD_DEV_ADDR_OFF 5
39 #define SW_SMI_CMD_SMI_OP_OFF 10
40 #define SW_SMI_CMD_SMI_MODE_OFF 12
41 #define SW_SMI_CMD_SMI_BUSY_OFF 15
43 /* Single-chip mode */
44 /* Switch Port Registers */
45 #define MVEBU_SW_LINK_CTRL_REG (1)
46 #define MVEBU_SW_PORT_CTRL_REG (4)
47 #define MVEBU_SW_PORT_BASE_VLAN (6)
49 /* Global 2 Registers */
50 #define MVEBU_G2_SMI_PHY_CMD_REG (24)
51 #define MVEBU_G2_SMI_PHY_DATA_REG (25)
53 int board_early_init_f(void)
60 /* adress of boot parameters */
61 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
66 /* Board specific AHCI / SATA enable code */
67 int board_ahci_enable(void)
73 /* Only DB requres this configuration */
74 if (!of_machine_is_compatible("marvell,armada-3720-db"))
77 /* Configure IO exander PCA9555: 7bit address 0x22 */
78 ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
80 printf("Cannot find PCA9555: %d\n", ret);
84 ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
86 printf("Failed to read IO expander value via I2C\n");
91 * Enable SATA power via IO expander connected via I2C by setting
92 * the corresponding bit to output mode to enable power for SATA
94 buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
95 ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
97 printf("Failed to set IO expander via I2C\n");
104 /* Board specific xHCI enable code */
105 int board_xhci_enable(fdt_addr_t base)
111 /* Only DB requres this configuration */
112 if (!of_machine_is_compatible("marvell,armada-3720-db"))
115 /* Configure IO exander PCA9555: 7bit address 0x22 */
116 ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
118 printf("Cannot find PCA9555: %d\n", ret);
122 printf("Enable USB VBUS\n");
125 * Read configuration (direction) and set VBUS pin as output
126 * (reset pin = output)
128 ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
130 printf("Failed to read IO expander value via I2C\n");
133 buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
134 ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
136 printf("Failed to set IO expander via I2C\n");
140 /* Read VBUS output value and disable it */
141 ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
143 printf("Failed to read IO expander value via I2C\n");
146 buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
147 ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
149 printf("Failed to set IO expander via I2C\n");
154 * Required delay for configuration to settle - must wait for
155 * power on port is disabled in case VBUS signal was high,
156 * required 3 seconds delay to let VBUS signal fully settle down
160 /* Enable VBUS power: Set output value of VBUS pin as enabled */
161 buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
162 ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
164 printf("Failed to set IO expander via I2C\n");
168 mdelay(500); /* required delay to let output value settle */
173 /* Helper function for accessing switch devices in multi-chip connection mode */
174 static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
175 int smi_addr, int reg, u16 value)
179 if (bus->write(bus, dev_smi_addr, 0,
180 MVEBU_SW_SMI_DATA_REG, value) != 0) {
181 printf("Error writing to the PHY addr=%02x reg=%02x\n",
186 smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
187 (1 << SW_SMI_CMD_SMI_MODE_OFF) |
188 (1 << SW_SMI_CMD_SMI_OP_OFF) |
189 (smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
190 (reg << SW_SMI_CMD_REG_ADDR_OFF);
191 if (bus->write(bus, dev_smi_addr, 0,
192 MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
193 printf("Error writing to the PHY addr=%02x reg=%02x\n",
201 /* Bring-up board-specific network stuff */
202 int board_network_enable(struct mii_dev *bus)
204 if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
208 * FIXME: remove this code once Topaz driver gets available
209 * A3720 Community Board Only
210 * Configure Topaz switch (88E6341)
211 * Restrict output to ports 1,2,3 only from port 0 (CPU)
212 * Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
214 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
215 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
216 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
217 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
218 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
219 MVEBU_SW_PORT_BASE_VLAN, BIT(0));
221 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
222 MVEBU_SW_PORT_CTRL_REG, 0x7f);
223 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
224 MVEBU_SW_PORT_CTRL_REG, 0x7f);
225 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
226 MVEBU_SW_PORT_CTRL_REG, 0x7f);
227 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
228 MVEBU_SW_PORT_CTRL_REG, 0x7f);
230 /* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
231 mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
232 MVEBU_SW_LINK_CTRL_REG, 0xe002);
234 /* Power up PHY 1, 2, 3 (through Global 2 registers) */
235 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
236 MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
237 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
238 MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
239 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
240 MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
241 mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
242 MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);