1 // SPDX-License-Identifier: GPL-2.0+
4 * Jason Cooper <u-boot@lakedaemon.net>
7 * Marvell Semiconductor <www.marvell.com>
8 * Written-by: Siddarth Gore <gores@marvell.com>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15 #include <asm/arch/mpp.h>
16 #include "dreamplug.h"
18 DECLARE_GLOBAL_DATA_PTR;
20 int board_early_init_f(void)
23 * default gpio configuration
24 * There are maximum 64 gpios controlled through 2 sets of registers
25 * the below configuration configures mainly initial LED status
27 mvebu_config_gpio(DREAMPLUG_OE_VAL_LOW,
28 DREAMPLUG_OE_VAL_HIGH,
29 DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
31 /* Multi-Purpose Pins Functionality configuration */
32 static const u32 kwmpp_config[] = {
33 MPP0_SPI_SCn, /* SPI Flash */
43 MPP10_UART0_TXD, /* Serial */
45 MPP12_SD_CLK, /* SDIO Slot */
53 MPP20_GE1_0, /* Gigabit Ethernet */
69 MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
80 MPP47_GPIO, /* Bluetooth LED */
81 MPP48_GPIO, /* Wifi LED */
82 MPP49_GPIO, /* Wifi AP LED */
85 kirkwood_mpp_conf(kwmpp_config, NULL);
91 /* adress of boot parameters */
92 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
97 #ifdef CONFIG_RESET_PHY_R
98 void mv_phy_88e1116_init(char *name)
103 if (miiphy_set_current_dev(name))
106 /* command to read PHY dev address */
107 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
108 printf("Err..%s could not read PHY dev address\n",
114 * Enable RGMII delay on Tx and Rx for CPU port
115 * Ref: sec 4.7.2 of chip datasheet
117 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
118 miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, ®);
119 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
120 miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
121 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
124 miiphy_reset(name, devadr);
126 printf("88E1116 Initialized on %s\n", name);
131 /* configure and initialize both PHY's */
132 mv_phy_88e1116_init("egiga0");
133 mv_phy_88e1116_init("egiga1");
135 #endif /* CONFIG_RESET_PHY_R */