1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (c) 2011 The Chromium OS Authors.
6 #ifndef __X86_CACHE_H__
7 #define __X86_CACHE_H__
10 * Use CONFIG_SYS_CACHELINE_SIZE (which is set to 64-bytes) for DMA alignment.
12 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
14 static inline void wbinvd(void)
16 asm volatile ("wbinvd" : : : "memory");
19 static inline void invd(void)
21 asm volatile("invd" : : : "memory");
24 /* Enable caches and write buffer */
25 void enable_caches(void);
27 /* Disable caches and write buffer */
28 void disable_caches(void);
30 #endif /* __X86_CACHE_H__ */