2 * From coreboot src/soc/intel/broadwell/include/soc/pm.h
4 * Copyright (C) 2016 Google, Inc.
6 * SPDX-License-Identifier: GPL-2.0
9 #ifndef __ASM_ARCH_PM_H
10 #define __ASM_ARCH_PM_H
13 #define WAK_STS (1 << 15)
14 #define PCIEXPWAK_STS (1 << 14)
15 #define PRBTNOR_STS (1 << 11)
16 #define RTC_STS (1 << 10)
17 #define PWRBTN_STS (1 << 8)
18 #define GBL_STS (1 << 5)
19 #define BM_STS (1 << 4)
20 #define TMROF_STS (1 << 0)
22 #define PCIEXPWAK_DIS (1 << 14)
23 #define RTC_EN (1 << 10)
24 #define PWRBTN_EN (1 << 8)
25 #define GBL_EN (1 << 5)
26 #define TMROF_EN (1 << 0)
28 #define SLP_EN (1 << 13)
29 #define SLP_TYP (7 << 10)
30 #define SLP_TYP_SHIFT 10
36 #define GBL_RLS (1 << 2)
37 #define BM_RLD (1 << 1)
38 #define SCI_EN (1 << 0)
41 #define XHCI_SMI_EN (1 << 31)
42 #define ME_SMI_EN (1 << 30)
43 #define GPIO_UNLOCK_SMI_EN (1 << 27)
44 #define INTEL_USB2_EN (1 << 18)
45 #define LEGACY_USB2_EN (1 << 17)
46 #define PERIODIC_EN (1 << 14)
47 #define TCO_EN (1 << 13)
48 #define MCSMI_EN (1 << 11)
49 #define BIOS_RLS (1 << 7)
50 #define SWSMI_TMR_EN (1 << 6)
51 #define APMC_EN (1 << 5)
52 #define SLP_SMI_EN (1 << 4)
53 #define LEGACY_USB_EN (1 << 3)
54 #define BIOS_EN (1 << 2)
56 #define GBL_SMI_EN (1 << 0)
59 #define UPWRC_WS (1 << 8)
60 #define UPWRC_WE (1 << 1)
61 #define UPWRC_SMI (1 << 0)
63 #define SWGPE_CTRL (1 << 1)
64 #define DEVACT_STS 0x44
67 #define TCO_TMR_HLT (1 << 11)
69 #define DMISCI_STS (1 << 9)
71 #define TCO2_STS_SECOND_TO (1 << 1)
73 #define GPE0_REG_MAX 4
74 #define GPE0_REG_SIZE 32
75 #define GPE0_STS(x) (0x80 + (x * 4))
76 #define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */
77 #define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */
78 #define GPE_94_64 2 /* 0x88/0x98 = GPE[94:64] */
79 #define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */
80 #define WADT_STS (1 << 18)
81 #define GP27_STS (1 << 16)
82 #define PME_B0_STS (1 << 13)
83 #define ME_SCI_STS (1 << 12)
84 #define PME_STS (1 << 11)
85 #define BATLOW_STS (1 << 10)
86 #define PCI_EXP_STS (1 << 9)
87 #define SMB_WAK_STS (1 << 7)
88 #define TCOSCI_STS (1 << 6)
89 #define SWGPE_STS (1 << 2)
90 #define HOT_PLUG_STS (1 << 1)
91 #define GPE0_EN(x) (0x90 + (x * 4))
92 #define WADT_en (1 << 18)
93 #define GP27_EN (1 << 16)
94 #define PME_B0_EN (1 << 13)
95 #define ME_SCI_EN (1 << 12)
96 #define PME_EN (1 << 11)
97 #define BATLOW_EN (1 << 10)
98 #define PCI_EXP_EN (1 << 9)
99 #define TCOSCI_EN (1 << 6)
100 #define SWGPE_EN (1 << 2)
101 #define HOT_PLUG_EN (1 << 1)
103 #define MAINBOARD_POWER_OFF 0
104 #define MAINBOARD_POWER_ON 1
105 #define MAINBOARD_POWER_KEEP 2
107 #define SLEEP_STATE_S0 0
108 #define SLEEP_STATE_S3 3
109 #define SLEEP_STATE_S5 5
111 struct chipset_power_state {
117 uint32_t gpe0_sts[4];
122 int prev_sleep_state;
123 uint16_t hsio_version;
124 uint16_t hsio_checksum;
127 void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps);