1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
6 #ifndef _ASM_MPC85xx_CONFIG_H_
7 #define _ASM_MPC85xx_CONFIG_H_
9 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 * This macro should be removed when we no longer care about backwards
13 * compatibility with older operating systems.
15 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
17 #include <fsl_ddrc_version.h>
19 #if defined(CONFIG_ARCH_MPC8548)
20 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
21 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
22 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
23 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
25 #elif defined(CONFIG_ARCH_P1010)
26 #define CONFIG_FSL_SDHC_V2_3
28 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
30 /* P1011 is single core version of P1020 */
31 #elif defined(CONFIG_ARCH_P1011)
34 #elif defined(CONFIG_ARCH_P1020)
37 #elif defined(CONFIG_ARCH_P1021)
39 #define QE_MURAM_SIZE 0x6000UL
41 #define QE_NUM_OF_SNUM 28
43 #elif defined(CONFIG_ARCH_P1023)
44 #define CONFIG_SYS_NUM_FMAN 1
45 #define CONFIG_SYS_NUM_FM1_DTSEC 2
46 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
47 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
48 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
50 /* P1024 is lower end variant of P1020 */
51 #elif defined(CONFIG_ARCH_P1024)
54 /* P1025 is lower end variant of P1021 */
55 #elif defined(CONFIG_ARCH_P1025)
57 #define QE_MURAM_SIZE 0x6000UL
59 #define QE_NUM_OF_SNUM 28
61 #elif defined(CONFIG_ARCH_P2020)
62 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
63 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
64 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
65 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
67 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
68 #define CONFIG_SYS_NUM_FMAN 1
69 #define CONFIG_SYS_NUM_FM1_DTSEC 5
70 #define CONFIG_SYS_NUM_FM1_10GEC 1
71 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
72 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
73 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
74 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
75 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
77 #elif defined(CONFIG_ARCH_P3041)
78 #define CONFIG_SYS_NUM_FMAN 1
79 #define CONFIG_SYS_NUM_FM1_DTSEC 5
80 #define CONFIG_SYS_NUM_FM1_10GEC 1
81 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
82 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
83 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
84 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
85 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
87 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
88 #define CONFIG_SYS_NUM_FMAN 2
89 #define CONFIG_SYS_NUM_FM1_DTSEC 4
90 #define CONFIG_SYS_NUM_FM2_DTSEC 4
91 #define CONFIG_SYS_NUM_FM1_10GEC 1
92 #define CONFIG_SYS_NUM_FM2_10GEC 1
93 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
94 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
95 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
96 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
97 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
98 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
100 #elif defined(CONFIG_ARCH_P5040)
101 #define CONFIG_SYS_NUM_FMAN 2
102 #define CONFIG_SYS_NUM_FM1_DTSEC 5
103 #define CONFIG_SYS_NUM_FM1_10GEC 1
104 #define CONFIG_SYS_NUM_FM2_DTSEC 5
105 #define CONFIG_SYS_NUM_FM2_10GEC 1
106 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
107 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
109 #elif defined(CONFIG_ARCH_BSC9131)
110 #define CONFIG_FSL_SDHC_V2_3
111 #define CONFIG_TSECV2
112 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
114 #elif defined(CONFIG_ARCH_BSC9132)
115 #define CONFIG_FSL_SDHC_V2_3
116 #define CONFIG_TSECV2
117 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
119 #elif defined(CONFIG_ARCH_T4240)
120 #ifdef CONFIG_ARCH_T4240
121 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
122 #define CONFIG_SYS_NUM_FM1_DTSEC 8
123 #define CONFIG_SYS_NUM_FM1_10GEC 2
124 #define CONFIG_SYS_NUM_FM2_DTSEC 8
125 #define CONFIG_SYS_NUM_FM2_10GEC 2
127 #define CONFIG_SYS_NUM_FM1_DTSEC 6
128 #define CONFIG_SYS_NUM_FM1_10GEC 1
129 #define CONFIG_SYS_NUM_FM2_DTSEC 8
130 #define CONFIG_SYS_NUM_FM2_10GEC 1
132 #define CONFIG_SYS_FSL_SRDS_1
133 #define CONFIG_SYS_FSL_SRDS_2
134 #define CONFIG_SYS_FSL_SRDS_3
135 #define CONFIG_SYS_FSL_SRDS_4
136 #define CONFIG_SYS_NUM_FMAN 2
137 #define CONFIG_SYS_PME_CLK 0
138 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
139 #define CONFIG_SYS_FM1_CLK 3
140 #define CONFIG_SYS_FM2_CLK 3
141 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
142 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
143 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
144 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
146 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
147 #define CONFIG_SYS_FSL_SRDS_1
148 #define CONFIG_SYS_FSL_SRDS_2
149 #define CONFIG_SYS_NUM_FMAN 1
150 #define CONFIG_SYS_FM1_CLK 0
151 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
152 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
154 #ifdef CONFIG_ARCH_B4860
155 #define CONFIG_MAX_DSP_CPUS 12
156 #define CONFIG_NUM_DSP_CPUS 6
157 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
158 #define CONFIG_SYS_NUM_FM1_DTSEC 6
159 #define CONFIG_SYS_NUM_FM1_10GEC 2
160 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
161 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
162 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
164 #define CONFIG_MAX_DSP_CPUS 2
165 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
166 #define CONFIG_SYS_NUM_FM1_DTSEC 4
167 #define CONFIG_SYS_NUM_FM1_10GEC 0
170 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
171 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
172 #define CONFIG_SYS_FSL_SRDS_1
173 #define CONFIG_SYS_NUM_FMAN 1
174 #define CONFIG_SYS_NUM_FM1_DTSEC 5
175 #define CONFIG_PME_PLAT_CLK_DIV 2
176 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
177 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
178 #define CONFIG_FM_PLAT_CLK_DIV 1
179 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
180 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
181 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
182 #define QE_MURAM_SIZE 0x6000UL
183 #define MAX_QE_RISC 1
184 #define QE_NUM_OF_SNUM 28
186 #elif defined(CONFIG_ARCH_T1024)
187 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
188 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
189 #define CONFIG_SYS_FSL_SRDS_1
190 #define CONFIG_SYS_NUM_FMAN 1
191 #define CONFIG_SYS_NUM_FM1_DTSEC 4
192 #define CONFIG_SYS_NUM_FM1_10GEC 1
193 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
194 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
195 #define CONFIG_SYS_FM1_CLK 0
196 #define CONFIG_QBMAN_CLK_DIV 1
197 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
198 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
199 #define QE_MURAM_SIZE 0x6000UL
200 #define MAX_QE_RISC 1
201 #define QE_NUM_OF_SNUM 28
203 #elif defined(CONFIG_ARCH_T2080)
204 #define CONFIG_SYS_NUM_FMAN 1
205 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
206 #define CONFIG_SYS_FSL_SRDS_1
207 #if defined(CONFIG_ARCH_T2080)
208 #define CONFIG_SYS_NUM_FM1_DTSEC 8
209 #define CONFIG_SYS_NUM_FM1_10GEC 4
210 #define CONFIG_SYS_FSL_SRDS_2
211 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
212 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
213 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
215 #define CONFIG_PME_PLAT_CLK_DIV 1
216 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
217 #define CONFIG_SYS_FM1_CLK 0
218 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
219 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
220 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
223 #elif defined(CONFIG_ARCH_C29X)
224 #define CONFIG_FSL_SDHC_V2_3
225 #define CONFIG_TSECV2_1
226 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
227 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
231 #endif /* _ASM_MPC85xx_CONFIG_H_ */