1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
6 #ifndef _ASM_MPC85xx_CONFIG_H_
7 #define _ASM_MPC85xx_CONFIG_H_
9 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 * This macro should be removed when we no longer care about backwards
13 * compatibility with older operating systems.
15 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
17 #include <fsl_ddrc_version.h>
20 #define CONFIG_SYS_FSL_IFC_BE
22 #if defined(CONFIG_ARCH_MPC8548)
23 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
24 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
25 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
26 #define CONFIG_SYS_FSL_RMU
27 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
29 #elif defined(CONFIG_ARCH_P1010)
30 #define CONFIG_FSL_SDHC_V2_3
32 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
33 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
34 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
35 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
37 /* P1011 is single core version of P1020 */
38 #elif defined(CONFIG_ARCH_P1011)
41 #elif defined(CONFIG_ARCH_P1020)
44 #elif defined(CONFIG_ARCH_P1021)
46 #define QE_MURAM_SIZE 0x6000UL
48 #define QE_NUM_OF_SNUM 28
50 #elif defined(CONFIG_ARCH_P1023)
51 #define CONFIG_SYS_NUM_FMAN 1
52 #define CONFIG_SYS_NUM_FM1_DTSEC 2
53 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
54 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
55 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
56 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
58 /* P1024 is lower end variant of P1020 */
59 #elif defined(CONFIG_ARCH_P1024)
62 /* P1025 is lower end variant of P1021 */
63 #elif defined(CONFIG_ARCH_P1025)
65 #define QE_MURAM_SIZE 0x6000UL
67 #define QE_NUM_OF_SNUM 28
69 #elif defined(CONFIG_ARCH_P2020)
70 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
71 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
72 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
73 #define CONFIG_SYS_FSL_RMU
74 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
76 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
77 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
78 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
79 #define CONFIG_SYS_NUM_FMAN 1
80 #define CONFIG_SYS_NUM_FM1_DTSEC 5
81 #define CONFIG_SYS_NUM_FM1_10GEC 1
82 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
83 #define CONFIG_SYS_FSL_TBCLK_DIV 32
84 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
85 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
86 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
87 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
88 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
89 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
90 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
91 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
93 #elif defined(CONFIG_ARCH_P3041)
94 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
95 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
96 #define CONFIG_SYS_NUM_FMAN 1
97 #define CONFIG_SYS_NUM_FM1_DTSEC 5
98 #define CONFIG_SYS_NUM_FM1_10GEC 1
99 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
100 #define CONFIG_SYS_FSL_TBCLK_DIV 32
101 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
102 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
103 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
104 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
105 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
106 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
107 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
108 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
110 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
111 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
112 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
113 #define CONFIG_SYS_NUM_FMAN 2
114 #define CONFIG_SYS_NUM_FM1_DTSEC 4
115 #define CONFIG_SYS_NUM_FM2_DTSEC 4
116 #define CONFIG_SYS_NUM_FM1_10GEC 1
117 #define CONFIG_SYS_NUM_FM2_10GEC 1
118 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
119 #define CONFIG_SYS_FSL_TBCLK_DIV 16
120 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
121 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
122 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
123 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
124 #define CONFIG_SYS_FSL_RMU
125 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
126 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
128 #elif defined(CONFIG_ARCH_P5040)
129 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
130 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
131 #define CONFIG_SYS_NUM_FMAN 2
132 #define CONFIG_SYS_NUM_FM1_DTSEC 5
133 #define CONFIG_SYS_NUM_FM1_10GEC 1
134 #define CONFIG_SYS_NUM_FM2_DTSEC 5
135 #define CONFIG_SYS_NUM_FM2_10GEC 1
136 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
137 #define CONFIG_SYS_FSL_TBCLK_DIV 16
138 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
139 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
140 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
141 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
142 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
144 #elif defined(CONFIG_ARCH_BSC9131)
145 #define CONFIG_FSL_SDHC_V2_3
146 #define CONFIG_TSECV2
147 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
148 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
149 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
151 #elif defined(CONFIG_ARCH_BSC9132)
152 #define CONFIG_FSL_SDHC_V2_3
153 #define CONFIG_TSECV2
154 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
155 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
156 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
157 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
158 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
159 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
160 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
162 #elif defined(CONFIG_ARCH_T4240)
163 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
164 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
165 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
166 #ifdef CONFIG_ARCH_T4240
167 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
168 #define CONFIG_SYS_NUM_FM1_DTSEC 8
169 #define CONFIG_SYS_NUM_FM1_10GEC 2
170 #define CONFIG_SYS_NUM_FM2_DTSEC 8
171 #define CONFIG_SYS_NUM_FM2_10GEC 2
173 #define CONFIG_SYS_NUM_FM1_DTSEC 6
174 #define CONFIG_SYS_NUM_FM1_10GEC 1
175 #define CONFIG_SYS_NUM_FM2_DTSEC 8
176 #define CONFIG_SYS_NUM_FM2_10GEC 1
178 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
179 #define CONFIG_SYS_FSL_SRDS_1
180 #define CONFIG_SYS_FSL_SRDS_2
181 #define CONFIG_SYS_FSL_SRDS_3
182 #define CONFIG_SYS_FSL_SRDS_4
183 #define CONFIG_SYS_NUM_FMAN 2
184 #define CONFIG_SYS_PME_CLK 0
185 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
186 #define CONFIG_SYS_FMAN_V3
187 #define CONFIG_SYS_FM1_CLK 3
188 #define CONFIG_SYS_FM2_CLK 3
189 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
190 #define CONFIG_SYS_FSL_TBCLK_DIV 16
191 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
192 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
193 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
194 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
195 #define CONFIG_SYS_FSL_SRIO_LIODN
196 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
197 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
198 #define CONFIG_SYS_FSL_PCI_VER_3_X
200 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
201 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
202 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
203 #define CONFIG_SYS_FSL_SRDS_1
204 #define CONFIG_SYS_FSL_SRDS_2
205 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
206 #define CONFIG_SYS_NUM_FMAN 1
207 #define CONFIG_SYS_FM1_CLK 0
208 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
209 #define CONFIG_SYS_FMAN_V3
210 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
211 #define CONFIG_SYS_FSL_TBCLK_DIV 16
212 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
213 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
215 #ifdef CONFIG_ARCH_B4860
216 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
217 #define CONFIG_MAX_DSP_CPUS 12
218 #define CONFIG_NUM_DSP_CPUS 6
219 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
220 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
221 #define CONFIG_SYS_NUM_FM1_DTSEC 6
222 #define CONFIG_SYS_NUM_FM1_10GEC 2
223 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
224 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
225 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
226 #define CONFIG_SYS_FSL_SRIO_LIODN
228 #define CONFIG_MAX_DSP_CPUS 2
229 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
230 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
231 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
232 #define CONFIG_SYS_NUM_FM1_DTSEC 4
233 #define CONFIG_SYS_NUM_FM1_10GEC 0
236 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
237 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
238 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
239 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
240 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
241 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
242 #define CONFIG_SYS_FSL_SRDS_1
243 #define CONFIG_SYS_NUM_FMAN 1
244 #define CONFIG_SYS_NUM_FM1_DTSEC 5
245 #define CONFIG_PME_PLAT_CLK_DIV 2
246 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
247 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
248 #define CONFIG_SYS_FMAN_V3
249 #define CONFIG_FM_PLAT_CLK_DIV 1
250 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
251 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
252 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
253 #define CONFIG_SYS_FSL_TBCLK_DIV 16
254 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
255 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
256 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
257 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
258 #define QE_MURAM_SIZE 0x6000UL
259 #define MAX_QE_RISC 1
260 #define QE_NUM_OF_SNUM 28
262 #elif defined(CONFIG_ARCH_T1024)
263 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
264 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
265 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
266 #define CONFIG_SYS_FMAN_V3
267 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
268 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
269 #define CONFIG_SYS_FSL_SRDS_1
270 #define CONFIG_SYS_NUM_FMAN 1
271 #define CONFIG_SYS_NUM_FM1_DTSEC 4
272 #define CONFIG_SYS_NUM_FM1_10GEC 1
273 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
274 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
275 #define CONFIG_SYS_FM1_CLK 0
276 #define CONFIG_QBMAN_CLK_DIV 1
277 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
278 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
279 #define CONFIG_SYS_FSL_TBCLK_DIV 16
280 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
281 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
282 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
283 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
284 #define QE_MURAM_SIZE 0x6000UL
285 #define MAX_QE_RISC 1
286 #define QE_NUM_OF_SNUM 28
288 #elif defined(CONFIG_ARCH_T2080)
289 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
290 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
291 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
292 #define CONFIG_SYS_FSL_QMAN_V3
293 #define CONFIG_SYS_NUM_FMAN 1
294 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
295 #define CONFIG_SYS_FSL_SRDS_1
296 #define CONFIG_SYS_FSL_PCI_VER_3_X
297 #if defined(CONFIG_ARCH_T2080)
298 #define CONFIG_SYS_NUM_FM1_DTSEC 8
299 #define CONFIG_SYS_NUM_FM1_10GEC 4
300 #define CONFIG_SYS_FSL_SRDS_2
301 #define CONFIG_SYS_FSL_SRIO_LIODN
302 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
303 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
304 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
306 #define CONFIG_PME_PLAT_CLK_DIV 1
307 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
308 #define CONFIG_SYS_FM1_CLK 0
309 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
310 #define CONFIG_SYS_FMAN_V3
311 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
312 #define CONFIG_SYS_FSL_TBCLK_DIV 16
313 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
314 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
315 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
316 #define CONFIG_SYS_FSL_ISBC_VER 2
317 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
320 #elif defined(CONFIG_ARCH_C29X)
321 #define CONFIG_FSL_SDHC_V2_3
322 #define CONFIG_TSECV2_1
323 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
324 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
325 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
329 #if !defined(CONFIG_ARCH_C29X)
330 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
333 #endif /* _ASM_MPC85xx_CONFIG_H_ */