8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
16 prompt "Target select"
19 config TARGET_SOCRATES
20 bool "Support socrates"
24 bool "Support P3041DS"
27 select BOARD_LATE_INIT if CHAIN_OF_TRUST
32 bool "Support P4080DS"
35 select BOARD_LATE_INIT if CHAIN_OF_TRUST
40 bool "Support P5040DS"
43 select BOARD_LATE_INIT if CHAIN_OF_TRUST
47 config TARGET_MPC8548CDS
48 bool "Support MPC8548CDS"
52 config TARGET_P1010RDB_PA
53 bool "Support P1010RDB_PA"
55 select BOARD_LATE_INIT if CHAIN_OF_TRUST
62 config TARGET_P1010RDB_PB
63 bool "Support P1010RDB_PB"
65 select BOARD_LATE_INIT if CHAIN_OF_TRUST
72 config TARGET_P1020RDB_PC
73 bool "Support P1020RDB-PC"
81 config TARGET_P1020RDB_PD
82 bool "Support P1020RDB-PD"
90 config TARGET_P2020RDB
91 bool "Support P2020RDB-PC"
99 config TARGET_P2041RDB
100 bool "Support P2041RDB"
102 select BOARD_LATE_INIT if CHAIN_OF_TRUST
107 config TARGET_QEMU_PPCE500
108 bool "Support qemu-ppce500"
109 select ARCH_QEMU_E500
112 config TARGET_T1024RDB
113 bool "Support T1024RDB"
115 select BOARD_LATE_INIT if CHAIN_OF_TRUST
118 select FSL_DDR_INTERACTIVE
122 config TARGET_T1042RDB
123 bool "Support T1042RDB"
125 select BOARD_LATE_INIT if CHAIN_OF_TRUST
129 config TARGET_T1042D4RDB
130 bool "Support T1042D4RDB"
132 select BOARD_LATE_INIT if CHAIN_OF_TRUST
137 config TARGET_T1042RDB_PI
138 bool "Support T1042RDB_PI"
140 select BOARD_LATE_INIT if CHAIN_OF_TRUST
145 config TARGET_T2080QDS
146 bool "Support T2080QDS"
148 select BOARD_LATE_INIT if CHAIN_OF_TRUST
151 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
152 select FSL_DDR_INTERACTIVE
155 config TARGET_T2080RDB
156 bool "Support T2080RDB"
158 select BOARD_LATE_INIT if CHAIN_OF_TRUST
164 config TARGET_T4160RDB
165 bool "Support T4160RDB"
171 config TARGET_T4240RDB
172 bool "Support T4240RDB"
176 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
180 config TARGET_KMP204X
181 bool "Support kmp204x"
184 config TARGET_KMCENT2
185 bool "Support kmcent2"
188 config TARGET_XPEDITE520X
189 bool "Support xpedite520x"
192 config TARGET_XPEDITE537X
193 bool "Support xpedite537x"
195 # Use DDR3 controller with DDR2 DIMMs on this board
196 select SYS_FSL_DDRC_GEN3
198 config TARGET_XPEDITE550X
199 bool "Support xpedite550x"
202 config TARGET_UCP1020
203 bool "Support uCP1020"
215 select SYS_FSL_DDR_VER_47
216 select SYS_FSL_ERRATUM_A004477
217 select SYS_FSL_ERRATUM_A005871
218 select SYS_FSL_ERRATUM_A006379
219 select SYS_FSL_ERRATUM_A006384
220 select SYS_FSL_ERRATUM_A006475
221 select SYS_FSL_ERRATUM_A006593
222 select SYS_FSL_ERRATUM_A007075
223 select SYS_FSL_ERRATUM_A007186
224 select SYS_FSL_ERRATUM_A007212
225 select SYS_FSL_ERRATUM_A009942
226 select SYS_FSL_HAS_DDR3
227 select SYS_FSL_HAS_SEC
228 select SYS_FSL_QORIQ_CHASSIS2
229 select SYS_FSL_SEC_BE
230 select SYS_FSL_SEC_COMPAT_4
242 select SYS_FSL_DDR_VER_47
243 select SYS_FSL_ERRATUM_A004477
244 select SYS_FSL_ERRATUM_A005871
245 select SYS_FSL_ERRATUM_A006379
246 select SYS_FSL_ERRATUM_A006384
247 select SYS_FSL_ERRATUM_A006475
248 select SYS_FSL_ERRATUM_A006593
249 select SYS_FSL_ERRATUM_A007075
250 select SYS_FSL_ERRATUM_A007186
251 select SYS_FSL_ERRATUM_A007212
252 select SYS_FSL_ERRATUM_A007907
253 select SYS_FSL_ERRATUM_A009942
254 select SYS_FSL_HAS_DDR3
255 select SYS_FSL_HAS_SEC
256 select SYS_FSL_QORIQ_CHASSIS2
257 select SYS_FSL_SEC_BE
258 select SYS_FSL_SEC_COMPAT_4
268 select SYS_FSL_DDR_VER_44
269 select SYS_FSL_ERRATUM_A004477
270 select SYS_FSL_ERRATUM_A005125
271 select SYS_FSL_ERRATUM_ESDHC111
272 select SYS_FSL_HAS_DDR3
273 select SYS_FSL_HAS_SEC
274 select SYS_FSL_SEC_BE
275 select SYS_FSL_SEC_COMPAT_4
284 select SYS_FSL_DDR_VER_46
285 select SYS_FSL_ERRATUM_A004477
286 select SYS_FSL_ERRATUM_A005125
287 select SYS_FSL_ERRATUM_A005434
288 select SYS_FSL_ERRATUM_ESDHC111
289 select SYS_FSL_ERRATUM_I2C_A004447
290 select SYS_FSL_ERRATUM_IFC_A002769
291 select FSL_PCIE_RESET
292 select SYS_FSL_HAS_DDR3
293 select SYS_FSL_HAS_SEC
294 select SYS_FSL_SEC_BE
295 select SYS_FSL_SEC_COMPAT_4
296 select SYS_PPC_E500_USE_DEBUG_TLB
307 select SYS_FSL_DDR_VER_46
308 select SYS_FSL_ERRATUM_A005125
309 select SYS_FSL_ERRATUM_ESDHC111
310 select FSL_PCIE_RESET
311 select SYS_FSL_HAS_DDR3
312 select SYS_FSL_HAS_SEC
313 select SYS_FSL_SEC_BE
314 select SYS_FSL_SEC_COMPAT_6
315 select SYS_PPC_E500_USE_DEBUG_TLB
324 select SYS_FSL_ERRATUM_A004508
325 select SYS_FSL_ERRATUM_A005125
326 select FSL_PCIE_RESET
327 select SYS_FSL_HAS_DDR2
328 select SYS_FSL_HAS_DDR3
329 select SYS_FSL_HAS_SEC
330 select SYS_FSL_SEC_BE
331 select SYS_FSL_SEC_COMPAT_2
332 select SYS_PPC_E500_USE_DEBUG_TLB
341 select SYS_FSL_HAS_DDR1
346 select SYS_FSL_ERRATUM_A005125
347 select FSL_PCIE_RESET
348 select SYS_FSL_HAS_DDR2
349 select SYS_FSL_HAS_SEC
350 select SYS_FSL_SEC_BE
351 select SYS_FSL_SEC_COMPAT_2
352 select SYS_PPC_E500_USE_DEBUG_TLB
358 select SYS_FSL_ERRATUM_A005125
359 select SYS_FSL_ERRATUM_NMG_DDR120
360 select SYS_FSL_ERRATUM_NMG_LBC103
361 select SYS_FSL_ERRATUM_NMG_ETSEC129
362 select SYS_FSL_ERRATUM_I2C_A004447
363 select FSL_PCIE_RESET
364 select SYS_FSL_HAS_DDR2
365 select SYS_FSL_HAS_DDR1
366 select SYS_FSL_HAS_SEC
367 select SYS_FSL_SEC_BE
368 select SYS_FSL_SEC_COMPAT_2
369 select SYS_PPC_E500_USE_DEBUG_TLB
375 select SYS_FSL_HAS_DDR1
380 select SYS_FSL_ERRATUM_A004508
381 select SYS_FSL_ERRATUM_A005125
382 select SYS_FSL_ERRATUM_DDR_115
383 select SYS_FSL_ERRATUM_DDR111_DDR134
384 select FSL_PCIE_RESET
385 select SYS_FSL_HAS_DDR2
386 select SYS_FSL_HAS_DDR3
387 select SYS_FSL_HAS_SEC
388 select SYS_FSL_SEC_BE
389 select SYS_FSL_SEC_COMPAT_2
390 select SYS_PPC_E500_USE_DEBUG_TLB
397 select SYS_FSL_ERRATUM_A004477
398 select SYS_FSL_ERRATUM_A004508
399 select SYS_FSL_ERRATUM_A005125
400 select SYS_FSL_ERRATUM_A005275
401 select SYS_FSL_ERRATUM_A006261
402 select SYS_FSL_ERRATUM_A007075
403 select SYS_FSL_ERRATUM_ESDHC111
404 select SYS_FSL_ERRATUM_I2C_A004447
405 select SYS_FSL_ERRATUM_IFC_A002769
406 select SYS_FSL_ERRATUM_P1010_A003549
407 select SYS_FSL_ERRATUM_SEC_A003571
408 select SYS_FSL_ERRATUM_IFC_A003399
409 select FSL_PCIE_RESET
410 select SYS_FSL_HAS_DDR3
411 select SYS_FSL_HAS_SEC
412 select SYS_FSL_SEC_BE
413 select SYS_FSL_SEC_COMPAT_4
414 select SYS_PPC_E500_USE_DEBUG_TLB
427 select SYS_FSL_ERRATUM_A004508
428 select SYS_FSL_ERRATUM_A005125
429 select SYS_FSL_ERRATUM_ELBC_A001
430 select SYS_FSL_ERRATUM_ESDHC111
431 select FSL_PCIE_DISABLE_ASPM
432 select SYS_FSL_HAS_DDR3
433 select SYS_FSL_HAS_SEC
434 select SYS_FSL_SEC_BE
435 select SYS_FSL_SEC_COMPAT_2
436 select SYS_PPC_E500_USE_DEBUG_TLB
442 select SYS_FSL_ERRATUM_A004508
443 select SYS_FSL_ERRATUM_A005125
444 select SYS_FSL_ERRATUM_ELBC_A001
445 select SYS_FSL_ERRATUM_ESDHC111
446 select FSL_PCIE_DISABLE_ASPM
447 select FSL_PCIE_RESET
448 select SYS_FSL_HAS_DDR3
449 select SYS_FSL_HAS_SEC
450 select SYS_FSL_SEC_BE
451 select SYS_FSL_SEC_COMPAT_2
452 select SYS_PPC_E500_USE_DEBUG_TLB
463 select SYS_FSL_ERRATUM_A004508
464 select SYS_FSL_ERRATUM_A005125
465 select SYS_FSL_ERRATUM_ELBC_A001
466 select SYS_FSL_ERRATUM_ESDHC111
467 select FSL_PCIE_DISABLE_ASPM
468 select FSL_PCIE_RESET
469 select SYS_FSL_HAS_DDR3
470 select SYS_FSL_HAS_SEC
471 select SYS_FSL_SEC_BE
472 select SYS_FSL_SEC_COMPAT_2
473 select SYS_PPC_E500_USE_DEBUG_TLB
484 select SYS_FSL_ERRATUM_A004508
485 select SYS_FSL_ERRATUM_A005125
486 select SYS_FSL_ERRATUM_I2C_A004447
487 select FSL_PCIE_RESET
488 select SYS_FSL_HAS_DDR3
489 select SYS_FSL_HAS_SEC
490 select SYS_FSL_SEC_BE
491 select SYS_FSL_SEC_COMPAT_4
497 select SYS_FSL_ERRATUM_A004508
498 select SYS_FSL_ERRATUM_A005125
499 select SYS_FSL_ERRATUM_ELBC_A001
500 select SYS_FSL_ERRATUM_ESDHC111
501 select FSL_PCIE_DISABLE_ASPM
502 select FSL_PCIE_RESET
503 select SYS_FSL_HAS_DDR3
504 select SYS_FSL_HAS_SEC
505 select SYS_FSL_SEC_BE
506 select SYS_FSL_SEC_COMPAT_2
507 select SYS_PPC_E500_USE_DEBUG_TLB
519 select SYS_FSL_ERRATUM_A004508
520 select SYS_FSL_ERRATUM_A005125
521 select SYS_FSL_ERRATUM_ELBC_A001
522 select SYS_FSL_ERRATUM_ESDHC111
523 select FSL_PCIE_DISABLE_ASPM
524 select FSL_PCIE_RESET
525 select SYS_FSL_HAS_DDR3
526 select SYS_FSL_HAS_SEC
527 select SYS_FSL_SEC_BE
528 select SYS_FSL_SEC_COMPAT_2
529 select SYS_PPC_E500_USE_DEBUG_TLB
537 select SYS_FSL_ERRATUM_A004477
538 select SYS_FSL_ERRATUM_A004508
539 select SYS_FSL_ERRATUM_A005125
540 select SYS_FSL_ERRATUM_ESDHC111
541 select SYS_FSL_ERRATUM_ESDHC_A001
542 select FSL_PCIE_RESET
543 select SYS_FSL_HAS_DDR3
544 select SYS_FSL_HAS_SEC
545 select SYS_FSL_SEC_BE
546 select SYS_FSL_SEC_COMPAT_2
547 select SYS_PPC_E500_USE_DEBUG_TLB
557 select SYS_FSL_ERRATUM_A004510
558 select SYS_FSL_ERRATUM_A004849
559 select SYS_FSL_ERRATUM_A005275
560 select SYS_FSL_ERRATUM_A006261
561 select SYS_FSL_ERRATUM_CPU_A003999
562 select SYS_FSL_ERRATUM_DDR_A003
563 select SYS_FSL_ERRATUM_DDR_A003474
564 select SYS_FSL_ERRATUM_ESDHC111
565 select SYS_FSL_ERRATUM_I2C_A004447
566 select SYS_FSL_ERRATUM_NMG_CPU_A011
567 select SYS_FSL_ERRATUM_SRIO_A004034
568 select SYS_FSL_ERRATUM_USB14
569 select SYS_FSL_HAS_DDR3
570 select SYS_FSL_HAS_SEC
571 select SYS_FSL_QORIQ_CHASSIS1
572 select SYS_FSL_SEC_BE
573 select SYS_FSL_SEC_COMPAT_4
581 select SYS_FSL_DDR_VER_44
582 select SYS_FSL_ERRATUM_A004510
583 select SYS_FSL_ERRATUM_A004849
584 select SYS_FSL_ERRATUM_A005275
585 select SYS_FSL_ERRATUM_A005812
586 select SYS_FSL_ERRATUM_A006261
587 select SYS_FSL_ERRATUM_CPU_A003999
588 select SYS_FSL_ERRATUM_DDR_A003
589 select SYS_FSL_ERRATUM_DDR_A003474
590 select SYS_FSL_ERRATUM_ESDHC111
591 select SYS_FSL_ERRATUM_I2C_A004447
592 select SYS_FSL_ERRATUM_NMG_CPU_A011
593 select SYS_FSL_ERRATUM_SRIO_A004034
594 select SYS_FSL_ERRATUM_USB14
595 select SYS_FSL_HAS_DDR3
596 select SYS_FSL_HAS_SEC
597 select SYS_FSL_QORIQ_CHASSIS1
598 select SYS_FSL_SEC_BE
599 select SYS_FSL_SEC_COMPAT_4
610 select SYS_FSL_DDR_VER_44
611 select SYS_FSL_ERRATUM_A004510
612 select SYS_FSL_ERRATUM_A004580
613 select SYS_FSL_ERRATUM_A004849
614 select SYS_FSL_ERRATUM_A005812
615 select SYS_FSL_ERRATUM_A007075
616 select SYS_FSL_ERRATUM_CPC_A002
617 select SYS_FSL_ERRATUM_CPC_A003
618 select SYS_FSL_ERRATUM_CPU_A003999
619 select SYS_FSL_ERRATUM_DDR_A003
620 select SYS_FSL_ERRATUM_DDR_A003474
621 select SYS_FSL_ERRATUM_ELBC_A001
622 select SYS_FSL_ERRATUM_ESDHC111
623 select SYS_FSL_ERRATUM_ESDHC13
624 select SYS_FSL_ERRATUM_ESDHC135
625 select SYS_FSL_ERRATUM_I2C_A004447
626 select SYS_FSL_ERRATUM_NMG_CPU_A011
627 select SYS_FSL_ERRATUM_SRIO_A004034
628 select SYS_P4080_ERRATUM_CPU22
629 select SYS_P4080_ERRATUM_PCIE_A003
630 select SYS_P4080_ERRATUM_SERDES8
631 select SYS_P4080_ERRATUM_SERDES9
632 select SYS_P4080_ERRATUM_SERDES_A001
633 select SYS_P4080_ERRATUM_SERDES_A005
634 select SYS_FSL_HAS_DDR3
635 select SYS_FSL_HAS_SEC
636 select SYS_FSL_QORIQ_CHASSIS1
637 select SYS_FSL_SEC_BE
638 select SYS_FSL_SEC_COMPAT_4
648 select SYS_FSL_DDR_VER_44
649 select SYS_FSL_ERRATUM_A004510
650 select SYS_FSL_ERRATUM_A004699
651 select SYS_FSL_ERRATUM_A005275
652 select SYS_FSL_ERRATUM_A005812
653 select SYS_FSL_ERRATUM_A006261
654 select SYS_FSL_ERRATUM_DDR_A003
655 select SYS_FSL_ERRATUM_DDR_A003474
656 select SYS_FSL_ERRATUM_ESDHC111
657 select SYS_FSL_ERRATUM_USB14
658 select SYS_FSL_HAS_DDR3
659 select SYS_FSL_HAS_SEC
660 select SYS_FSL_QORIQ_CHASSIS1
661 select SYS_FSL_SEC_BE
662 select SYS_FSL_SEC_COMPAT_4
669 config ARCH_QEMU_E500
676 select SYS_FSL_DDR_VER_50
677 select SYS_FSL_ERRATUM_A008378
678 select SYS_FSL_ERRATUM_A008109
679 select SYS_FSL_ERRATUM_A009663
680 select SYS_FSL_ERRATUM_A009942
681 select SYS_FSL_ERRATUM_ESDHC111
682 select SYS_FSL_HAS_DDR3
683 select SYS_FSL_HAS_DDR4
684 select SYS_FSL_HAS_SEC
685 select SYS_FSL_QORIQ_CHASSIS2
686 select SYS_FSL_SEC_BE
687 select SYS_FSL_SEC_COMPAT_5
698 select SYS_FSL_DDR_VER_50
699 select SYS_FSL_ERRATUM_A008044
700 select SYS_FSL_ERRATUM_A008378
701 select SYS_FSL_ERRATUM_A008109
702 select SYS_FSL_ERRATUM_A009663
703 select SYS_FSL_ERRATUM_A009942
704 select SYS_FSL_ERRATUM_ESDHC111
705 select SYS_FSL_HAS_DDR3
706 select SYS_FSL_HAS_DDR4
707 select SYS_FSL_HAS_SEC
708 select SYS_FSL_QORIQ_CHASSIS2
709 select SYS_FSL_SEC_BE
710 select SYS_FSL_SEC_COMPAT_5
720 select SYS_FSL_DDR_VER_50
721 select SYS_FSL_ERRATUM_A008044
722 select SYS_FSL_ERRATUM_A008378
723 select SYS_FSL_ERRATUM_A008109
724 select SYS_FSL_ERRATUM_A009663
725 select SYS_FSL_ERRATUM_A009942
726 select SYS_FSL_ERRATUM_ESDHC111
727 select SYS_FSL_HAS_DDR3
728 select SYS_FSL_HAS_DDR4
729 select SYS_FSL_HAS_SEC
730 select SYS_FSL_QORIQ_CHASSIS2
731 select SYS_FSL_SEC_BE
732 select SYS_FSL_SEC_COMPAT_5
743 select SYS_FSL_DDR_VER_47
744 select SYS_FSL_ERRATUM_A006379
745 select SYS_FSL_ERRATUM_A006593
746 select SYS_FSL_ERRATUM_A007186
747 select SYS_FSL_ERRATUM_A007212
748 select SYS_FSL_ERRATUM_A007815
749 select SYS_FSL_ERRATUM_A007907
750 select SYS_FSL_ERRATUM_A008109
751 select SYS_FSL_ERRATUM_A009942
752 select SYS_FSL_ERRATUM_ESDHC111
753 select FSL_PCIE_RESET
754 select SYS_FSL_HAS_DDR3
755 select SYS_FSL_HAS_SEC
756 select SYS_FSL_QORIQ_CHASSIS2
757 select SYS_FSL_SEC_BE
758 select SYS_FSL_SEC_COMPAT_4
771 select SYS_FSL_DDR_VER_47
772 select SYS_FSL_ERRATUM_A004468
773 select SYS_FSL_ERRATUM_A005871
774 select SYS_FSL_ERRATUM_A006379
775 select SYS_FSL_ERRATUM_A006593
776 select SYS_FSL_ERRATUM_A007186
777 select SYS_FSL_ERRATUM_A007798
778 select SYS_FSL_ERRATUM_A009942
779 select SYS_FSL_HAS_DDR3
780 select SYS_FSL_HAS_SEC
781 select SYS_FSL_QORIQ_CHASSIS2
782 select SYS_FSL_SEC_BE
783 select SYS_FSL_SEC_COMPAT_4
794 select SYS_FSL_DDR_VER_47
795 select SYS_FSL_ERRATUM_A004468
796 select SYS_FSL_ERRATUM_A005871
797 select SYS_FSL_ERRATUM_A006261
798 select SYS_FSL_ERRATUM_A006379
799 select SYS_FSL_ERRATUM_A006593
800 select SYS_FSL_ERRATUM_A007186
801 select SYS_FSL_ERRATUM_A007798
802 select SYS_FSL_ERRATUM_A007815
803 select SYS_FSL_ERRATUM_A007907
804 select SYS_FSL_ERRATUM_A008109
805 select SYS_FSL_ERRATUM_A009942
806 select SYS_FSL_HAS_DDR3
807 select SYS_FSL_HAS_SEC
808 select SYS_FSL_QORIQ_CHASSIS2
809 select SYS_FSL_SEC_BE
810 select SYS_FSL_SEC_COMPAT_4
818 config MPC85XX_HAVE_RESET_VECTOR
819 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
830 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
836 Enble PowerPC E500MC core
841 Enable PowerPC E6500 core
846 Use Freescale common code for Local Access Window
851 Enable Freescale Secure Boot feature. Normally selected
852 by defconfig. If unsure, do not change.
855 int "Maximum number of CPUs permitted for MPC85xx"
856 default 12 if ARCH_T4240
857 default 8 if ARCH_P4080 || \
859 default 4 if ARCH_B4860 || \
866 default 2 if ARCH_B4420 || \
878 Set this number to the maximum number of possible CPUs in the SoC.
879 SoCs may have multiple clusters with each cluster may have multiple
880 ports. If some ports are reserved but higher ports are used for
881 cores, count the reserved ports. This will allocate enough memory
882 in spin table to properly handle all cores.
884 config SYS_CCSRBAR_DEFAULT
885 hex "Default CCSRBAR address"
886 default 0xff700000 if ARCH_BSC9131 || \
902 default 0xff600000 if ARCH_P1023
903 default 0xfe000000 if ARCH_B4420 || \
915 default 0xe0000000 if ARCH_QEMU_E500
917 Default value of CCSRBAR comes from power-on-reset. It
918 is fixed on each SoC. Some SoCs can have different value
919 if changed by pre-boot regime. The value here must match
920 the current value in SoC. If not sure, do not change.
922 config SYS_FSL_ERRATUM_A004468
925 config SYS_FSL_ERRATUM_A004477
928 config SYS_FSL_ERRATUM_A004508
931 config SYS_FSL_ERRATUM_A004580
934 config SYS_FSL_ERRATUM_A004699
937 config SYS_FSL_ERRATUM_A004849
940 config SYS_FSL_ERRATUM_A004510
943 config SYS_FSL_ERRATUM_A004510_SVR_REV
945 depends on SYS_FSL_ERRATUM_A004510
946 default 0x20 if ARCH_P4080
949 config SYS_FSL_ERRATUM_A004510_SVR_REV2
951 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
954 config SYS_FSL_ERRATUM_A005125
957 config SYS_FSL_ERRATUM_A005434
960 config SYS_FSL_ERRATUM_A005812
963 config SYS_FSL_ERRATUM_A005871
966 config SYS_FSL_ERRATUM_A005275
969 config SYS_FSL_ERRATUM_A006261
972 config SYS_FSL_ERRATUM_A006379
975 config SYS_FSL_ERRATUM_A006384
978 config SYS_FSL_ERRATUM_A006475
981 config SYS_FSL_ERRATUM_A006593
984 config SYS_FSL_ERRATUM_A007075
987 config SYS_FSL_ERRATUM_A007186
990 config SYS_FSL_ERRATUM_A007212
993 config SYS_FSL_ERRATUM_A007815
996 config SYS_FSL_ERRATUM_A007798
999 config SYS_FSL_ERRATUM_A007907
1002 config SYS_FSL_ERRATUM_A008044
1005 config SYS_FSL_ERRATUM_CPC_A002
1008 config SYS_FSL_ERRATUM_CPC_A003
1011 config SYS_FSL_ERRATUM_CPU_A003999
1014 config SYS_FSL_ERRATUM_ELBC_A001
1017 config SYS_FSL_ERRATUM_I2C_A004447
1020 config SYS_FSL_A004447_SVR_REV
1022 depends on SYS_FSL_ERRATUM_I2C_A004447
1023 default 0x00 if ARCH_MPC8548
1024 default 0x10 if ARCH_P1010
1025 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1026 default 0x20 if ARCH_P3041 || ARCH_P4080
1028 config SYS_FSL_ERRATUM_IFC_A002769
1031 config SYS_FSL_ERRATUM_IFC_A003399
1034 config SYS_FSL_ERRATUM_NMG_CPU_A011
1037 config SYS_FSL_ERRATUM_NMG_ETSEC129
1040 config SYS_FSL_ERRATUM_NMG_LBC103
1043 config SYS_FSL_ERRATUM_P1010_A003549
1046 config SYS_FSL_ERRATUM_SATA_A001
1049 config SYS_FSL_ERRATUM_SEC_A003571
1052 config SYS_FSL_ERRATUM_SRIO_A004034
1055 config SYS_FSL_ERRATUM_USB14
1058 config SYS_P4080_ERRATUM_CPU22
1061 config SYS_P4080_ERRATUM_PCIE_A003
1064 config SYS_P4080_ERRATUM_SERDES8
1067 config SYS_P4080_ERRATUM_SERDES9
1070 config SYS_P4080_ERRATUM_SERDES_A001
1073 config SYS_P4080_ERRATUM_SERDES_A005
1076 config FSL_PCIE_DISABLE_ASPM
1079 config FSL_PCIE_RESET
1082 config SYS_FSL_QORIQ_CHASSIS1
1085 config SYS_FSL_QORIQ_CHASSIS2
1088 config SYS_FSL_NUM_LAWS
1089 int "Number of local access windows"
1091 default 32 if ARCH_B4420 || \
1100 default 16 if ARCH_T1024 || \
1103 default 12 if ARCH_BSC9131 || \
1116 default 10 if ARCH_MPC8544 || \
1118 default 8 if ARCH_MPC8540 || \
1121 Number of local access windows. This is fixed per SoC.
1122 If not sure, do not change.
1124 config SYS_FSL_THREADS_PER_CORE
1129 config SYS_NUM_TLBCAMS
1130 int "Number of TLB CAM entries"
1131 default 64 if E500MC
1134 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1135 16 for other E500 SoCs.
1140 config SYS_PPC_E500_USE_DEBUG_TLB
1149 config SYS_PPC_E500_DEBUG_TLB
1150 int "Temporary TLB entry for external debugger"
1151 depends on SYS_PPC_E500_USE_DEBUG_TLB
1152 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1153 default 1 if ARCH_MPC8536
1154 default 2 if ARCH_MPC8572 || \
1161 default 3 if ARCH_P1010 || \
1165 Select a temporary TLB entry to be used during boot to work
1166 around limitations in e500v1 and e500v2 external debugger
1167 support. This reduces the portions of the boot code where
1168 breakpoints and single stepping do not work. The value of this
1169 symbol should be set to the TLB1 entry to be used for this
1170 purpose. If unsure, do not change.
1172 config SYS_FSL_IFC_CLK_DIV
1173 int "Divider of platform clock"
1175 default 2 if ARCH_B4420 || \
1184 Defines divider of platform clock(clock input to
1187 config SYS_FSL_LBC_CLK_DIV
1188 int "Divider of platform clock"
1189 depends on FSL_ELBC || ARCH_MPC8540 || \
1193 default 2 if ARCH_P2041 || \
1200 Defines divider of platform clock(clock input to
1206 source "board/emulation/qemu-ppce500/Kconfig"
1207 source "board/freescale/corenet_ds/Kconfig"
1208 source "board/freescale/mpc8548cds/Kconfig"
1209 source "board/freescale/p1010rdb/Kconfig"
1210 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1211 source "board/freescale/p2041rdb/Kconfig"
1212 source "board/freescale/t102xrdb/Kconfig"
1213 source "board/freescale/t104xrdb/Kconfig"
1214 source "board/freescale/t208xqds/Kconfig"
1215 source "board/freescale/t208xrdb/Kconfig"
1216 source "board/freescale/t4rdb/Kconfig"
1217 source "board/keymile/Kconfig"
1218 source "board/socrates/Kconfig"
1219 source "board/xes/xpedite520x/Kconfig"
1220 source "board/xes/xpedite537x/Kconfig"
1221 source "board/xes/xpedite550x/Kconfig"
1222 source "board/Arcturus/ucp1020/Kconfig"