8 bool "Enable the 'errata' command"
12 This enables the 'errata' command which displays a list of errata
13 work-arounds which are enabled for the current board.
15 config FSL_PREPBL_ESDHC_BOOT_SECTOR
16 bool "Generate QorIQ pre-PBL eSDHC boot sector"
18 depends on SYS_EXTRA_OPTIONS = SDCARD
20 With this option final image would have prepended QorIQ pre-PBL eSDHC
21 boot sector suitable for SD card images. This boot sector instruct
22 BootROM to configure L2 SRAM and eSDHC then load image from SD card
23 into L2 SRAM and finally jump to image entry point.
25 This is alternative to Freescale boot_format tool, but works only for
26 SD card images and only for L2 SRAM booting. U-Boot images generated
27 with this option should not passed to boot_format tool.
29 For other configuration like booting from eSPI or configuring SDRAM
30 please use Freescale boot_format tool without this option. See file
31 doc/README.mpc85xx-sd-spi-boot
33 config FSL_PREPBL_ESDHC_BOOT_SECTOR_START
34 int "QorIQ pre-PBL eSDHC boot sector start offset"
35 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
39 QorIQ pre-PBL eSDHC boot sector may be located on one of the first
40 24 SD card sectors. Select SD card sector on which final U-Boot
41 image (with this boot sector) would be installed.
43 By default first SD card sector (0) is used. But this may be changed
44 to allow installing U-Boot image on some partition (with fixed start
47 Please note that any sector on SD card prior this boot sector must
48 not contain ASCII "BOOT" bytes at sector offset 0x40.
50 config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA
51 int "Relative data sector for QorIQ pre-PBL eSDHC boot sector"
52 depends on FSL_PREPBL_ESDHC_BOOT_SECTOR
56 Select data sector from the beginning of QorIQ pre-PBL eSDHC boot
57 sector on which would be stored raw U-Boot image.
59 By default is it second sector (1) which is the first available free
60 sector (on the first sector is stored boot sector). It can be any
61 sector number which offset in bytes can be expressed by 32-bit number.
63 In case this final U-Boot image (with this boot sector) is put on
64 the FAT32 partition into reserved boot area, this data sector needs
65 to be at least 2 (third sector) because FAT32 use second sector for
69 prompt "Target select"
72 config TARGET_SOCRATES
73 bool "Support socrates"
77 bool "Support P3041DS"
80 select BOARD_LATE_INIT if CHAIN_OF_TRUST
86 bool "Support P4080DS"
89 select BOARD_LATE_INIT if CHAIN_OF_TRUST
95 bool "Support P5040DS"
98 select BOARD_LATE_INIT if CHAIN_OF_TRUST
100 select SYS_FSL_RAID_ENGINE
104 config TARGET_MPC8548CDS
105 bool "Support MPC8548CDS"
108 select SYS_CACHE_SHIFT_5
110 config TARGET_P1010RDB_PA
111 bool "Support P1010RDB_PA"
113 select BOARD_LATE_INIT if CHAIN_OF_TRUST
120 config TARGET_P1010RDB_PB
121 bool "Support P1010RDB_PB"
123 select BOARD_LATE_INIT if CHAIN_OF_TRUST
130 config TARGET_P1020RDB_PC
131 bool "Support P1020RDB-PC"
139 config TARGET_P1020RDB_PD
140 bool "Support P1020RDB-PD"
148 config TARGET_P2020RDB
149 bool "Support P2020RDB-PC"
157 config TARGET_P2041RDB
158 bool "Support P2041RDB"
160 select BOARD_LATE_INIT if CHAIN_OF_TRUST
166 config TARGET_QEMU_PPCE500
167 bool "Support qemu-ppce500"
168 select ARCH_QEMU_E500
171 imply OF_HAS_PRIOR_STAGE
173 config TARGET_T1024RDB
174 bool "Support T1024RDB"
176 select BOARD_LATE_INIT if CHAIN_OF_TRUST
179 select FSL_DDR_INTERACTIVE
183 config TARGET_T1042RDB
184 bool "Support T1042RDB"
186 select BOARD_LATE_INIT if CHAIN_OF_TRUST
190 config TARGET_T1042D4RDB
191 bool "Support T1042D4RDB"
193 select BOARD_LATE_INIT if CHAIN_OF_TRUST
198 config TARGET_T1042RDB_PI
199 bool "Support T1042RDB_PI"
201 select BOARD_LATE_INIT if CHAIN_OF_TRUST
206 config TARGET_T2080QDS
207 bool "Support T2080QDS"
209 select BOARD_LATE_INIT if CHAIN_OF_TRUST
212 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
213 select FSL_DDR_INTERACTIVE
216 config TARGET_T2080RDB
217 bool "Support T2080RDB"
219 select BOARD_LATE_INIT if CHAIN_OF_TRUST
225 config TARGET_T4240RDB
226 bool "Support T4240RDB"
230 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
234 config TARGET_KMP204X
235 bool "Support kmp204x"
238 config TARGET_KMCENT2
239 bool "Support kmcent2"
251 select HETROGENOUS_CLUSTERS
252 select SYS_FSL_DDR_VER_47
253 select SYS_FSL_ERRATUM_A004477
254 select SYS_FSL_ERRATUM_A005871
255 select SYS_FSL_ERRATUM_A006379
256 select SYS_FSL_ERRATUM_A006384
257 select SYS_FSL_ERRATUM_A006475
258 select SYS_FSL_ERRATUM_A006593
259 select SYS_FSL_ERRATUM_A007075
260 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
261 select SYS_FSL_ERRATUM_A007212
262 select SYS_FSL_ERRATUM_A009942
263 select SYS_FSL_HAS_DDR3
264 select SYS_FSL_HAS_SEC
265 select SYS_FSL_QORIQ_CHASSIS2
266 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
267 select SYS_FSL_SEC_BE
268 select SYS_FSL_SEC_COMPAT_4
269 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
270 select SYS_FSL_USB1_PHY_ENABLE
283 select HETROGENOUS_CLUSTERS
284 select SYS_FSL_DDR_VER_47
285 select SYS_FSL_ERRATUM_A004477
286 select SYS_FSL_ERRATUM_A005871
287 select SYS_FSL_ERRATUM_A006379
288 select SYS_FSL_ERRATUM_A006384
289 select SYS_FSL_ERRATUM_A006475
290 select SYS_FSL_ERRATUM_A006593
291 select SYS_FSL_ERRATUM_A007075
292 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
293 select SYS_FSL_ERRATUM_A007212
294 select SYS_FSL_ERRATUM_A007907
295 select SYS_FSL_ERRATUM_A009942
296 select SYS_FSL_HAS_DDR3
297 select SYS_FSL_HAS_SEC
298 select SYS_FSL_QORIQ_CHASSIS2
299 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
300 select SYS_FSL_SEC_BE
301 select SYS_FSL_SEC_COMPAT_4
302 select SYS_FSL_SRIO_LIODN
303 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
304 select SYS_FSL_USB1_PHY_ENABLE
314 select SYS_FSL_DDR_VER_44
315 select SYS_FSL_ERRATUM_A004477
316 select SYS_FSL_ERRATUM_A005125
317 select SYS_FSL_ERRATUM_ESDHC111
318 select SYS_FSL_HAS_DDR3
319 select SYS_FSL_HAS_SEC
320 select SYS_FSL_SEC_BE
321 select SYS_FSL_SEC_COMPAT_4
330 select SYS_FSL_DDR_VER_46
331 select SYS_FSL_ERRATUM_A004477
332 select SYS_FSL_ERRATUM_A005125
333 select SYS_FSL_ERRATUM_A005434
334 select SYS_FSL_ERRATUM_ESDHC111
335 select SYS_FSL_ERRATUM_I2C_A004447
336 select SYS_FSL_ERRATUM_IFC_A002769
337 select FSL_PCIE_RESET
338 select SYS_FSL_HAS_DDR3
339 select SYS_FSL_HAS_SEC
340 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
341 select SYS_FSL_SEC_BE
342 select SYS_FSL_SEC_COMPAT_4
343 select SYS_PPC_E500_USE_DEBUG_TLB
354 select SYS_FSL_DDR_VER_46
355 select SYS_FSL_ERRATUM_A005125
356 select SYS_FSL_ERRATUM_ESDHC111
357 select FSL_PCIE_RESET
358 select SYS_FSL_HAS_DDR3
359 select SYS_FSL_HAS_SEC
360 select SYS_FSL_SEC_BE
361 select SYS_FSL_SEC_COMPAT_6
362 select SYS_PPC_E500_USE_DEBUG_TLB
371 select SYS_FSL_ERRATUM_A004508
372 select SYS_FSL_ERRATUM_A005125
373 select FSL_PCIE_RESET
374 select SYS_FSL_HAS_DDR2
375 select SYS_FSL_HAS_DDR3
376 select SYS_FSL_HAS_SEC
377 select SYS_FSL_SEC_BE
378 select SYS_FSL_SEC_COMPAT_2
379 select SYS_PPC_E500_USE_DEBUG_TLB
388 select SYS_FSL_HAS_DDR1
394 select SYS_CACHE_SHIFT_5
395 select SYS_FSL_ERRATUM_A005125
396 select FSL_PCIE_RESET
397 select SYS_FSL_HAS_DDR2
398 select SYS_FSL_HAS_SEC
399 select SYS_FSL_SEC_BE
400 select SYS_FSL_SEC_COMPAT_2
401 select SYS_PPC_E500_USE_DEBUG_TLB
408 select SYS_FSL_ERRATUM_A005125
409 select SYS_FSL_ERRATUM_NMG_DDR120
410 select SYS_FSL_ERRATUM_NMG_LBC103
411 select SYS_FSL_ERRATUM_NMG_ETSEC129
412 select SYS_FSL_ERRATUM_I2C_A004447
413 select FSL_PCIE_RESET
414 select SYS_FSL_HAS_DDR2
415 select SYS_FSL_HAS_DDR1
416 select SYS_FSL_HAS_SEC
418 select SYS_FSL_SEC_BE
419 select SYS_FSL_SEC_COMPAT_2
420 select SYS_PPC_E500_USE_DEBUG_TLB
426 select SYS_FSL_HAS_DDR1
430 select A003399_NOR_WORKAROUND if SYS_FSL_ERRATUM_IFC_A003399 && !SPL
433 select SYS_CACHE_SHIFT_5
434 select SYS_HAS_SERDES
435 select SYS_FSL_ERRATUM_A004477
436 select SYS_FSL_ERRATUM_A004508
437 select SYS_FSL_ERRATUM_A005125
438 select SYS_FSL_ERRATUM_A005275
439 select SYS_FSL_ERRATUM_A006261
440 select SYS_FSL_ERRATUM_A007075
441 select SYS_FSL_ERRATUM_ESDHC111
442 select SYS_FSL_ERRATUM_I2C_A004447
443 select SYS_FSL_ERRATUM_IFC_A002769
444 select SYS_FSL_ERRATUM_P1010_A003549
445 select SYS_FSL_ERRATUM_SEC_A003571
446 select SYS_FSL_ERRATUM_IFC_A003399
447 select FSL_PCIE_RESET
448 select SYS_FSL_HAS_DDR3
449 select SYS_FSL_HAS_SEC
450 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
451 select SYS_FSL_SEC_BE
452 select SYS_FSL_SEC_COMPAT_4
453 select SYS_FSL_USB1_PHY_ENABLE
454 select SYS_PPC_E500_USE_DEBUG_TLB
468 select SYS_FSL_ERRATUM_A004508
469 select SYS_FSL_ERRATUM_A005125
470 select SYS_FSL_ERRATUM_ELBC_A001
471 select SYS_FSL_ERRATUM_ESDHC111
472 select FSL_PCIE_DISABLE_ASPM
473 select SYS_FSL_HAS_DDR3
474 select SYS_FSL_HAS_SEC
475 select SYS_FSL_SEC_BE
476 select SYS_FSL_SEC_COMPAT_2
477 select SYS_PPC_E500_USE_DEBUG_TLB
484 select SYS_CACHE_SHIFT_5
485 select SYS_FSL_ERRATUM_A004508
486 select SYS_FSL_ERRATUM_A005125
487 select SYS_FSL_ERRATUM_ELBC_A001
488 select SYS_FSL_ERRATUM_ESDHC111
489 select FSL_PCIE_DISABLE_ASPM
490 select FSL_PCIE_RESET
491 select SYS_FSL_HAS_DDR3
492 select SYS_FSL_HAS_SEC
493 select SYS_FSL_SEC_BE
494 select SYS_FSL_SEC_COMPAT_2
495 select SYS_PPC_E500_USE_DEBUG_TLB
506 select SYS_FSL_ERRATUM_A004508
507 select SYS_FSL_ERRATUM_A005125
508 select SYS_FSL_ERRATUM_ELBC_A001
509 select SYS_FSL_ERRATUM_ESDHC111
510 select FSL_PCIE_DISABLE_ASPM
511 select FSL_PCIE_RESET
512 select SYS_FSL_HAS_DDR3
513 select SYS_FSL_HAS_SEC
514 select SYS_FSL_SEC_BE
515 select SYS_FSL_SEC_COMPAT_2
516 select SYS_PPC_E500_USE_DEBUG_TLB
527 select SYS_FSL_ERRATUM_A004508
528 select SYS_FSL_ERRATUM_A005125
529 select SYS_FSL_ERRATUM_I2C_A004447
530 select FSL_PCIE_RESET
531 select SYS_FSL_HAS_DDR3
532 select SYS_FSL_HAS_SEC
533 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
534 select SYS_FSL_SEC_BE
535 select SYS_FSL_SEC_COMPAT_4
541 select SYS_FSL_ERRATUM_A004508
542 select SYS_FSL_ERRATUM_A005125
543 select SYS_FSL_ERRATUM_ELBC_A001
544 select SYS_FSL_ERRATUM_ESDHC111
545 select FSL_PCIE_DISABLE_ASPM
546 select FSL_PCIE_RESET
547 select SYS_FSL_HAS_DDR3
548 select SYS_FSL_HAS_SEC
550 select SYS_FSL_SEC_BE
551 select SYS_FSL_SEC_COMPAT_2
552 select SYS_PPC_E500_USE_DEBUG_TLB
564 select SYS_FSL_ERRATUM_A004508
565 select SYS_FSL_ERRATUM_A005125
566 select SYS_FSL_ERRATUM_ELBC_A001
567 select SYS_FSL_ERRATUM_ESDHC111
568 select FSL_PCIE_DISABLE_ASPM
569 select FSL_PCIE_RESET
570 select SYS_FSL_HAS_DDR3
571 select SYS_FSL_HAS_SEC
572 select SYS_FSL_SEC_BE
573 select SYS_FSL_SEC_COMPAT_2
574 select SYS_PPC_E500_USE_DEBUG_TLB
583 select SYS_CACHE_SHIFT_5
584 select SYS_FSL_ERRATUM_A004477
585 select SYS_FSL_ERRATUM_A004508
586 select SYS_FSL_ERRATUM_A005125
587 select SYS_FSL_ERRATUM_ESDHC111
588 select SYS_FSL_ERRATUM_ESDHC_A001
589 select FSL_PCIE_RESET
590 select SYS_FSL_HAS_DDR3
591 select SYS_FSL_HAS_SEC
592 select SYS_FSL_SEC_BE
593 select SYS_FSL_SEC_COMPAT_2
594 select SYS_PPC_E500_USE_DEBUG_TLB
603 select BACKSIDE_L2_CACHE
606 select SYS_CACHE_SHIFT_6
607 select SYS_FSL_ERRATUM_A004510
608 select SYS_FSL_ERRATUM_A004849
609 select SYS_FSL_ERRATUM_A005275
610 select SYS_FSL_ERRATUM_A006261
611 select SYS_FSL_ERRATUM_CPU_A003999
612 select SYS_FSL_ERRATUM_DDR_A003
613 select SYS_FSL_ERRATUM_DDR_A003474
614 select SYS_FSL_ERRATUM_ESDHC111
615 select SYS_FSL_ERRATUM_I2C_A004447
616 select SYS_FSL_ERRATUM_NMG_CPU_A011
617 select SYS_FSL_ERRATUM_SRIO_A004034
618 select SYS_FSL_ERRATUM_USB14
619 select SYS_FSL_HAS_DDR3
620 select SYS_FSL_HAS_SEC
621 select SYS_FSL_QORIQ_CHASSIS1
622 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
623 select SYS_FSL_SEC_BE
624 select SYS_FSL_SEC_COMPAT_4
625 select SYS_FSL_USB1_PHY_ENABLE
626 select SYS_FSL_USB2_PHY_ENABLE
632 select BACKSIDE_L2_CACHE
636 select SYS_CACHE_SHIFT_6
637 select SYS_FSL_DDR_VER_44
638 select SYS_FSL_ERRATUM_A004510
639 select SYS_FSL_ERRATUM_A004849
640 select SYS_FSL_ERRATUM_A005275
641 select SYS_FSL_ERRATUM_A005812
642 select SYS_FSL_ERRATUM_A006261
643 select SYS_FSL_ERRATUM_CPU_A003999
644 select SYS_FSL_ERRATUM_DDR_A003
645 select SYS_FSL_ERRATUM_DDR_A003474
646 select SYS_FSL_ERRATUM_ESDHC111
647 select SYS_FSL_ERRATUM_I2C_A004447
648 select SYS_FSL_ERRATUM_NMG_CPU_A011
649 select SYS_FSL_ERRATUM_SRIO_A004034
650 select SYS_FSL_ERRATUM_USB14
651 select SYS_FSL_HAS_DDR3
652 select SYS_FSL_HAS_SEC
653 select SYS_FSL_QORIQ_CHASSIS1
654 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
655 select SYS_FSL_SEC_BE
656 select SYS_FSL_SEC_COMPAT_4
657 select SYS_FSL_USB1_PHY_ENABLE
658 select SYS_FSL_USB2_PHY_ENABLE
667 select BACKSIDE_L2_CACHE
671 select SYS_CACHE_SHIFT_6
672 select SYS_FSL_DDR_VER_44
673 select SYS_FSL_ERRATUM_A004510
674 select SYS_FSL_ERRATUM_A004580
675 select SYS_FSL_ERRATUM_A004849
676 select SYS_FSL_ERRATUM_A005812
677 select SYS_FSL_ERRATUM_A007075
678 select SYS_FSL_ERRATUM_CPC_A002
679 select SYS_FSL_ERRATUM_CPC_A003
680 select SYS_FSL_ERRATUM_CPU_A003999
681 select SYS_FSL_ERRATUM_DDR_A003
682 select SYS_FSL_ERRATUM_DDR_A003474
683 select SYS_FSL_ERRATUM_ELBC_A001
684 select SYS_FSL_ERRATUM_ESDHC111
685 select SYS_FSL_ERRATUM_ESDHC13
686 select SYS_FSL_ERRATUM_ESDHC135
687 select SYS_FSL_ERRATUM_I2C_A004447
688 select SYS_FSL_ERRATUM_NMG_CPU_A011
689 select SYS_FSL_ERRATUM_SRIO_A004034
690 select SYS_FSL_PCIE_COMPAT_P4080_PCIE
691 select SYS_P4080_ERRATUM_CPU22
692 select SYS_P4080_ERRATUM_PCIE_A003
693 select SYS_P4080_ERRATUM_SERDES8
694 select SYS_P4080_ERRATUM_SERDES9
695 select SYS_P4080_ERRATUM_SERDES_A001
696 select SYS_P4080_ERRATUM_SERDES_A005
697 select SYS_FSL_HAS_DDR3
698 select SYS_FSL_HAS_SEC
699 select SYS_FSL_QORIQ_CHASSIS1
701 select SYS_FSL_SEC_BE
702 select SYS_FSL_SEC_COMPAT_4
710 select BACKSIDE_L2_CACHE
714 select SYS_CACHE_SHIFT_6
715 select SYS_FSL_DDR_VER_44
716 select SYS_FSL_ERRATUM_A004510
717 select SYS_FSL_ERRATUM_A004699
718 select SYS_FSL_ERRATUM_A005275
719 select SYS_FSL_ERRATUM_A005812
720 select SYS_FSL_ERRATUM_A006261
721 select SYS_FSL_ERRATUM_DDR_A003
722 select SYS_FSL_ERRATUM_DDR_A003474
723 select SYS_FSL_ERRATUM_ESDHC111
724 select SYS_FSL_ERRATUM_USB14
725 select SYS_FSL_HAS_DDR3
726 select SYS_FSL_HAS_SEC
727 select SYS_FSL_QORIQ_CHASSIS1
728 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
729 select SYS_FSL_SEC_BE
730 select SYS_FSL_SEC_COMPAT_4
731 select SYS_FSL_USB1_PHY_ENABLE
732 select SYS_FSL_USB2_PHY_ENABLE
739 config ARCH_QEMU_E500
741 select SYS_CACHE_SHIFT_5
745 select BACKSIDE_L2_CACHE
750 select SYS_CACHE_SHIFT_6
751 select SYS_FSL_DDR_VER_50
752 select SYS_FSL_ERRATUM_A008378
753 select SYS_FSL_ERRATUM_A008109
754 select SYS_FSL_ERRATUM_A009663
755 select SYS_FSL_ERRATUM_A009942
756 select SYS_FSL_ERRATUM_ESDHC111
757 select SYS_FSL_HAS_DDR3
758 select SYS_FSL_HAS_DDR4
759 select SYS_FSL_HAS_SEC
760 select SYS_FSL_QORIQ_CHASSIS2
761 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
762 select SYS_FSL_SEC_BE
763 select SYS_FSL_SEC_COMPAT_5
764 select SYS_FSL_SINGLE_SOURCE_CLK
765 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
766 select SYS_FSL_USB_DUAL_PHY_ENABLE
775 select BACKSIDE_L2_CACHE
780 select SYS_CACHE_SHIFT_6
781 select SYS_FSL_DDR_VER_50
782 select SYS_FSL_ERRATUM_A008044
783 select SYS_FSL_ERRATUM_A008378
784 select SYS_FSL_ERRATUM_A008109
785 select SYS_FSL_ERRATUM_A009663
786 select SYS_FSL_ERRATUM_A009942
787 select SYS_FSL_ERRATUM_ESDHC111
788 select SYS_FSL_HAS_DDR3
789 select SYS_FSL_HAS_DDR4
790 select SYS_FSL_HAS_SEC
791 select SYS_FSL_QORIQ_CHASSIS2
792 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
793 select SYS_FSL_SEC_BE
794 select SYS_FSL_SEC_COMPAT_5
795 select SYS_FSL_SINGLE_SOURCE_CLK
796 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
797 select SYS_FSL_USB_DUAL_PHY_ENABLE
805 select BACKSIDE_L2_CACHE
810 select SYS_CACHE_SHIFT_6
811 select SYS_FSL_DDR_VER_50
812 select SYS_FSL_ERRATUM_A008044
813 select SYS_FSL_ERRATUM_A008378
814 select SYS_FSL_ERRATUM_A008109
815 select SYS_FSL_ERRATUM_A009663
816 select SYS_FSL_ERRATUM_A009942
817 select SYS_FSL_ERRATUM_ESDHC111
818 select SYS_FSL_HAS_DDR3
819 select SYS_FSL_HAS_DDR4
820 select SYS_FSL_HAS_SEC
821 select SYS_FSL_QORIQ_CHASSIS2
822 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
823 select SYS_FSL_SEC_BE
824 select SYS_FSL_SEC_COMPAT_5
825 select SYS_FSL_SINGLE_SOURCE_CLK
826 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
827 select SYS_FSL_USB_DUAL_PHY_ENABLE
839 select SYS_CACHE_SHIFT_6
840 select SYS_FSL_DDR_VER_47
841 select SYS_FSL_ERRATUM_A006379
842 select SYS_FSL_ERRATUM_A006593
843 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
844 select SYS_FSL_ERRATUM_A007212
845 select SYS_FSL_ERRATUM_A007815
846 select SYS_FSL_ERRATUM_A007907
847 select SYS_FSL_ERRATUM_A008109
848 select SYS_FSL_ERRATUM_A009942
849 select SYS_FSL_ERRATUM_ESDHC111
850 select FSL_PCIE_RESET
851 select SYS_FSL_HAS_DDR3
852 select SYS_FSL_HAS_SEC
853 select SYS_FSL_QORIQ_CHASSIS2
854 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
855 select SYS_FSL_SEC_BE
856 select SYS_FSL_SEC_COMPAT_4
857 select SYS_FSL_SRIO_LIODN
858 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
859 select SYS_FSL_USB_DUAL_PHY_ENABLE
874 select SYS_CACHE_SHIFT_6
875 select SYS_FSL_DDR_VER_47
876 select SYS_FSL_ERRATUM_A004468
877 select SYS_FSL_ERRATUM_A005871
878 select SYS_FSL_ERRATUM_A006261
879 select SYS_FSL_ERRATUM_A006379
880 select SYS_FSL_ERRATUM_A006593
881 select SYS_FSL_ERRATUM_A007186 if CHAIN_OF_TRUST
882 select SYS_FSL_ERRATUM_A007798
883 select SYS_FSL_ERRATUM_A007815
884 select SYS_FSL_ERRATUM_A007907
885 select SYS_FSL_ERRATUM_A008109
886 select SYS_FSL_ERRATUM_A009942
887 select SYS_FSL_HAS_DDR3
888 select SYS_FSL_HAS_SEC
889 select SYS_FSL_QORIQ_CHASSIS2
890 select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
891 select SYS_FSL_SEC_BE
892 select SYS_FSL_SEC_COMPAT_4
893 select SYS_FSL_SRIO_LIODN
894 select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
895 select SYS_FSL_USB_DUAL_PHY_ENABLE
903 config MPC85XX_HAVE_RESET_VECTOR
904 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
908 bool "toggle branch predition"
918 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc
925 Enble PowerPC E500MC core
934 Enable PowerPC E6500 core
939 Use Freescale common code for Local Access Window
941 config HETROGENOUS_CLUSTERS
945 int "Maximum number of CPUs permitted for MPC85xx"
946 default 12 if ARCH_T4240
947 default 8 if ARCH_P4080
948 default 4 if ARCH_B4860 || \
955 default 2 if ARCH_B4420 || \
966 Set this number to the maximum number of possible CPUs in the SoC.
967 SoCs may have multiple clusters with each cluster may have multiple
968 ports. If some ports are reserved but higher ports are used for
969 cores, count the reserved ports. This will allocate enough memory
970 in spin table to properly handle all cores.
972 config SYS_CCSRBAR_DEFAULT
973 hex "Default CCSRBAR address"
974 default 0xff700000 if ARCH_BSC9131 || \
989 default 0xff600000 if ARCH_P1023
990 default 0xfe000000 if ARCH_B4420 || \
1001 default 0xe0000000 if ARCH_QEMU_E500
1003 Default value of CCSRBAR comes from power-on-reset. It
1004 is fixed on each SoC. Some SoCs can have different value
1005 if changed by pre-boot regime. The value here must match
1006 the current value in SoC. If not sure, do not change.
1008 config A003399_NOR_WORKAROUND
1011 Enables a workaround for IFC erratum A003399. It is only required
1014 config A008044_WORKAROUND
1017 Enables a workaround for T1040/T1042 erratum A008044. It is only
1018 required during NAND boot and valid for Rev 1.0 SoC revision
1020 config SYS_FSL_ERRATUM_A004468
1023 config SYS_FSL_ERRATUM_A004477
1026 config SYS_FSL_ERRATUM_A004508
1029 config SYS_FSL_ERRATUM_A004580
1032 config SYS_FSL_ERRATUM_A004699
1035 config SYS_FSL_ERRATUM_A004849
1038 config SYS_FSL_ERRATUM_A004510
1041 config SYS_FSL_ERRATUM_A004510_SVR_REV
1043 depends on SYS_FSL_ERRATUM_A004510
1044 default 0x20 if ARCH_P4080
1047 config SYS_FSL_ERRATUM_A004510_SVR_REV2
1049 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041))
1052 config SYS_FSL_ERRATUM_A005125
1055 config SYS_FSL_ERRATUM_A005434
1058 config SYS_FSL_ERRATUM_A005812
1061 config SYS_FSL_ERRATUM_A005871
1064 config SYS_FSL_ERRATUM_A005275
1067 config SYS_FSL_ERRATUM_A006261
1070 config SYS_FSL_ERRATUM_A006379
1073 config SYS_FSL_ERRATUM_A006384
1076 config SYS_FSL_ERRATUM_A006475
1079 config SYS_FSL_ERRATUM_A006593
1082 config SYS_FSL_ERRATUM_A007075
1085 config SYS_FSL_ERRATUM_A007186
1088 config SYS_FSL_ERRATUM_A007212
1091 config SYS_FSL_ERRATUM_A007815
1094 config SYS_FSL_ERRATUM_A007798
1097 config SYS_FSL_ERRATUM_A007907
1100 config SYS_FSL_ERRATUM_A008044
1102 select A008044_WORKAROUND if MTD_RAW_NAND
1104 config SYS_FSL_ERRATUM_CPC_A002
1107 config SYS_FSL_ERRATUM_CPC_A003
1110 config SYS_FSL_ERRATUM_CPU_A003999
1113 config SYS_FSL_ERRATUM_ELBC_A001
1116 config SYS_FSL_ERRATUM_I2C_A004447
1119 config SYS_FSL_A004447_SVR_REV
1121 depends on SYS_FSL_ERRATUM_I2C_A004447
1122 default 0x00 if ARCH_MPC8548
1123 default 0x10 if ARCH_P1010
1124 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132
1125 default 0x20 if ARCH_P3041 || ARCH_P4080
1127 config SYS_FSL_ERRATUM_IFC_A002769
1130 config SYS_FSL_ERRATUM_IFC_A003399
1133 config SYS_FSL_ERRATUM_NMG_CPU_A011
1136 config SYS_FSL_ERRATUM_NMG_ETSEC129
1139 config SYS_FSL_ERRATUM_NMG_LBC103
1142 config SYS_FSL_ERRATUM_P1010_A003549
1145 config SYS_FSL_ERRATUM_SATA_A001
1148 config SYS_FSL_ERRATUM_SEC_A003571
1151 config SYS_FSL_ERRATUM_SRIO_A004034
1154 config SYS_FSL_ERRATUM_USB14
1157 config SYS_HAS_SERDES
1160 config SYS_P4080_ERRATUM_CPU22
1163 config SYS_P4080_ERRATUM_PCIE_A003
1166 config SYS_P4080_ERRATUM_SERDES8
1169 config SYS_P4080_ERRATUM_SERDES9
1172 config SYS_P4080_ERRATUM_SERDES_A001
1175 config SYS_P4080_ERRATUM_SERDES_A005
1178 config FSL_PCIE_DISABLE_ASPM
1181 config FSL_PCIE_RESET
1184 config SYS_FSL_RAID_ENGINE
1190 config SYS_FSL_QORIQ_CHASSIS1
1193 config SYS_FSL_QORIQ_CHASSIS2
1196 config SYS_FSL_NUM_LAWS
1197 int "Number of local access windows"
1199 default 32 if ARCH_B4420 || \
1207 default 16 if ARCH_T1024 || \
1210 default 12 if ARCH_BSC9131 || \
1222 default 10 if ARCH_MPC8544 || \
1224 default 8 if ARCH_MPC8540 || \
1227 Number of local access windows. This is fixed per SoC.
1228 If not sure, do not change.
1230 config SYS_FSL_CORES_PER_CLUSTER
1232 depends on SYS_FSL_QORIQ_CHASSIS2
1233 default 4 if ARCH_B4860 || ARCH_T2080 || ARCH_T4240
1234 default 2 if ARCH_B4420
1235 default 1 if ARCH_T1024 || ARCH_T1040 || ARCH_T1042
1237 config SYS_FSL_THREADS_PER_CORE
1239 depends on SYS_FSL_QORIQ_CHASSIS2
1243 config SYS_NUM_TLBCAMS
1244 int "Number of TLB CAM entries"
1245 default 64 if E500MC
1248 Number of TLB CAM entries for Book-E chips. 64 for E500MC,
1249 16 for other E500 SoCs.
1251 if HETROGENOUS_CLUSTERS
1259 config PPC_CLUSTER_START
1263 config DSP_CLUSTER_START
1275 config SYS_ETVPE_CLK
1280 config BACKSIDE_L2_CACHE
1286 config SYS_PPC_E500_USE_DEBUG_TLB
1292 config SYS_PPC_E500_DEBUG_TLB
1293 int "Temporary TLB entry for external debugger"
1294 depends on SYS_PPC_E500_USE_DEBUG_TLB
1295 default 0 if ARCH_MPC8544 || ARCH_MPC8548
1296 default 1 if ARCH_MPC8536
1297 default 2 if ARCH_P1011 || \
1303 default 3 if ARCH_P1010 || \
1307 Select a temporary TLB entry to be used during boot to work
1308 around limitations in e500v1 and e500v2 external debugger
1309 support. This reduces the portions of the boot code where
1310 breakpoints and single stepping do not work. The value of this
1311 symbol should be set to the TLB1 entry to be used for this
1312 purpose. If unsure, do not change.
1314 config SYS_FSL_IFC_CLK_DIV
1315 int "Divider of platform clock"
1317 default 2 if ARCH_B4420 || \
1325 Defines divider of platform clock(clock input to
1328 config SYS_FSL_LBC_CLK_DIV
1329 int "Divider of platform clock"
1330 depends on FSL_ELBC || ARCH_MPC8540 || \
1334 default 2 if ARCH_P2041 || \
1341 Defines divider of platform clock(clock input to
1344 config ENABLE_36BIT_PHYS
1345 bool "Enable 36bit physical address space support"
1347 config SYS_BOOK3E_HV
1348 bool "Category E.HV is supported"
1358 config SYS_CPC_REINIT_F
1361 The CPC is configured as SRAM at the time of U-Boot entry and is
1362 required to be re-initialized.
1367 config SYS_CACHE_STASHING
1368 bool "Enable cache stashing"
1370 config SYS_FSL_PCIE_COMPAT_P4080_PCIE
1373 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
1376 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
1379 config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
1382 config SYS_FSL_PCIE_COMPAT
1384 depends on FSL_CORENET
1385 default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE
1386 default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22
1387 default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24
1388 default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30
1390 Defines the string to utilize when trying to match PCIe device tree
1391 nodes for the given platform.
1393 config SYS_FSL_SINGLE_SOURCE_CLK
1396 config SYS_FSL_SRIO_LIODN
1399 config SYS_FSL_TBCLK_DIV
1401 default 32 if ARCH_P2041 || ARCH_P3041
1402 default 16 if ARCH_P4080 || ARCH_P5040 || ARCH_T4240 || ARCH_B4860 || \
1403 ARCH_B4420 || ARCH_T1040 || ARCH_T1042 || \
1404 ARCH_T1024 || ARCH_T2080
1407 Defines the core time base clock divider ratio compared to the system
1408 clock. On most PQ3 devices this is 8, on newer QorIQ devices it can
1409 be 16 or 32. The ratio varies from SoC to Soc.
1411 config SYS_FSL_USB1_PHY_ENABLE
1414 config SYS_FSL_USB2_PHY_ENABLE
1417 config SYS_FSL_USB_DUAL_PHY_ENABLE
1420 config SYS_MPC85XX_NO_RESETVEC
1421 bool "Discard resetvec section and move bootpg section up"
1424 If this variable is specified, the section .resetvec is not kept and
1425 the section .bootpg is placed in the previous 4k of the .text section.
1427 config SPL_SYS_MPC85XX_NO_RESETVEC
1428 bool "Discard resetvec section and move bootpg section up, in SPL"
1429 depends on MPC85xx && SPL
1431 If this variable is specified, the section .resetvec is not kept and
1432 the section .bootpg is placed in the previous 4k of the .text section,
1433 of the SPL portion of the binary.
1435 config TPL_SYS_MPC85XX_NO_RESETVEC
1436 bool "Discard resetvec section and move bootpg section up, in TPL"
1437 depends on MPC85xx && TPL
1439 If this variable is specified, the section .resetvec is not kept and
1440 the section .bootpg is placed in the previous 4k of the .text section,
1441 of the SPL portion of the binary.
1446 source "board/emulation/qemu-ppce500/Kconfig"
1447 source "board/freescale/corenet_ds/Kconfig"
1448 source "board/freescale/mpc8548cds/Kconfig"
1449 source "board/freescale/p1010rdb/Kconfig"
1450 source "board/freescale/p1_p2_rdb_pc/Kconfig"
1451 source "board/freescale/p2041rdb/Kconfig"
1452 source "board/freescale/t102xrdb/Kconfig"
1453 source "board/freescale/t104xrdb/Kconfig"
1454 source "board/freescale/t208xqds/Kconfig"
1455 source "board/freescale/t208xrdb/Kconfig"
1456 source "board/freescale/t4rdb/Kconfig"
1457 source "board/socrates/Kconfig"