arch/powerpc/cpu/mpc83xx/cpu_init.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <asm-offsets.h>
   8 #include <mpc83xx.h>
   9 #include <ioports.h>
  10 #include <asm/io.h>
  11 #include <asm/processor.h>
  12 #include <fsl_qe.h>
  13 #ifdef CONFIG_USB_EHCI_FSL
  14 #include <usb/ehci-ci.h>
  15 #endif
  16 #include <linux/delay.h>
  17 #ifdef CONFIG_QE
  18 #include <fsl_qe.h>
  19 #endif
  20
  21 #include "lblaw/lblaw.h"
  22 #include "elbc/elbc.h"
  23 #include "sysio/sysio.h"
  24 #include "arbiter/arbiter.h"
  25 #include "initreg/initreg.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #ifdef CONFIG_QE
  30 extern qe_iop_conf_t qe_iop_conf_tab[];
  31 extern void qe_config_iopin(u8 port, u8 pin, int dir,
  32                          int open_drain, int assign);
  33
  34 #if !defined(CONFIG_PINCTRL)
  35 static void config_qe_ioports(void)
  36 {
  37         u8      port, pin;
  38         int     dir, open_drain, assign;
  39         int     i;
  40
  41         for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
  42                 port            = qe_iop_conf_tab[i].port;
  43                 pin             = qe_iop_conf_tab[i].pin;
  44                 dir             = qe_iop_conf_tab[i].dir;
  45                 open_drain      = qe_iop_conf_tab[i].open_drain;
  46                 assign          = qe_iop_conf_tab[i].assign;
  47                 qe_config_iopin(port, pin, dir, open_drain, assign);
  48         }
  49 }
  50 #endif
  51 #endif
  52
  53 /*
  54  * Breathe some life into the CPU...
  55  *
  56  * Set up the memory map,
  57  * initialize a bunch of registers,
  58  * initialize the UPM's
  59  */
  60 void cpu_init_f (volatile immap_t * im)
  61 {
  62         __be32 sccr_mask =
  63 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
  64                 SCCR_ENCCM |
  65 #endif
  66 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
  67                 SCCR_PCICM |
  68 #endif
  69 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM        /* PCIE1 clock mode */
  70                 SCCR_PCIEXP1CM |
  71 #endif
  72 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM        /* PCIE2 clock mode */
  73                 SCCR_PCIEXP2CM |
  74 #endif
  75 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
  76                 SCCR_TSECCM |
  77 #endif
  78 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
  79                 SCCR_TSEC1CM |
  80 #endif
  81 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
  82                 SCCR_TSEC2CM |
  83 #endif
  84 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
  85                 SCCR_TSEC1ON |
  86 #endif
  87 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
  88                 SCCR_TSEC2ON |
  89 #endif
  90 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
  91                 SCCR_USBMPHCM |
  92 #endif
  93 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
  94                 SCCR_USBDRCM |
  95 #endif
  96 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
  97                 SCCR_SATACM |
  98 #endif
  99                 0;
 100         __be32 sccr_val =
 101 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
 102                 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
 103 #endif
 104 #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
 105                 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
 106 #endif
 107 #ifdef CONFIG_SYS_SCCR_PCIEXP1CM        /* PCIE1 clock mode */
 108                 (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
 109 #endif
 110 #ifdef CONFIG_SYS_SCCR_PCIEXP2CM        /* PCIE2 clock mode */
 111                 (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
 112 #endif
 113 #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
 114                 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
 115 #endif
 116 #ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
 117                 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
 118 #endif
 119 #ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
 120                 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
 121 #endif
 122 #ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
 123                 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
 124 #endif
 125 #ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
 126                 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
 127 #endif
 128 #ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
 129                 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
 130 #endif
 131 #ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
 132                 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
 133 #endif
 134 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 135                 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
 136 #endif
 137                 0;
 138
 139         /* Pointer is writable since we allocated a register for it */
 140         gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
 141
 142         /* global data region was cleared in start.S */
 143
 144         /* system performance tweaking */
 145         clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
 146
 147         clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
 148
 149         clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
 150
 151         /* RSR - Reset Status Register - clear all status (4.6.1.3) */
 152         gd->arch.reset_status = __raw_readl(&im->reset.rsr);
 153         __raw_writel(~(RSR_RES), &im->reset.rsr);
 154
 155         /* AER - Arbiter Event Register - store status */
 156         gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
 157         gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
 158
 159         /*
 160          * RMR - Reset Mode Register
 161          * contains checkstop reset enable (4.6.1.4)
 162          */
 163         __raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
 164
 165         /* LCRR - Clock Ratio Register (10.3.1.16)
 166          * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
 167          */
 168         clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
 169         __raw_readl(&im->im_lbc.lcrr);
 170         isync();
 171
 172         /* Enable Time Base & Decrementer ( so we will have udelay() )*/
 173         setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
 174
 175         /* System General Purpose Register */
 176 #ifdef CONFIG_SYS_SICRH
 177 #if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
 178         /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 179         __raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
 180                      &im->sysconf.sicrh);
 181 #else
 182         __raw_writel(CONFIG_SYS_SICRH, &im->sysconf.sicrh);
 183 #endif
 184 #endif
 185 #ifdef CONFIG_SYS_SICRL
 186         __raw_writel(CONFIG_SYS_SICRL, &im->sysconf.sicrl);
 187 #endif
 188 #ifdef CONFIG_SYS_GPR1
 189         __raw_writel(CONFIG_SYS_GPR1, &im->sysconf.gpr1);
 190 #endif
 191 #ifdef CONFIG_SYS_DDRCDR /* DDR control driver register */
 192         __raw_writel(CONFIG_SYS_DDRCDR, &im->sysconf.ddrcdr);
 193 #endif
 194 #ifdef CONFIG_SYS_OBIR /* Output buffer impedance register */
 195         __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
 196 #endif
 197
 198 #if !defined(CONFIG_PINCTRL)
 199 #ifdef CONFIG_QE
 200         /* Config QE ioports */
 201         config_qe_ioports();
 202 #endif
 203 #endif
 204
 205         /* Set up preliminary BR/OR regs */
 206         init_early_memctl_regs();
 207
 208         /* Local Access window setup */
 209 #if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
 210         im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
 211         im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
 212 #else
 213 #error  CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
 214 #endif
 215
 216 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
 217         im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
 218         im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
 219 #endif
 220 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 221         im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
 222         im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
 223 #endif
 224 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
 225         im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
 226         im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
 227 #endif
 228 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
 229         im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
 230         im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
 231 #endif
 232 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
 233         im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
 234         im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
 235 #endif
 236 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
 237         im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
 238         im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
 239 #endif
 240 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
 241         im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
 242         im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
 243 #endif
 244 #ifdef CONFIG_SYS_GPIO1_PRELIM
 245         im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
 246         im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
 247 #endif
 248 #ifdef CONFIG_SYS_GPIO2_PRELIM
 249         im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
 250         im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 251 #endif
 252 #if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
 253         uint32_t temp;
 254         struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
 255
 256         /* Configure interface. */
 257         setbits_be32(&ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
 258
 259         /* Wait for clock to stabilize */
 260         do {
 261                 temp = __raw_readl(&ehci->control);
 262                 udelay(1000);
 263         } while (!(temp & PHY_CLK_VALID));
 264 #endif
 265 }
 266
 267 int cpu_init_r (void)
 268 {
 269 #ifdef CONFIG_QE
 270         uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
 271
 272         qe_init(qe_base);
 273         qe_reset();
 274 #endif
 275         return 0;
 276 }
 277
 278 /*
 279  * Print out the bus arbiter event
 280  */
 281 #if defined(CONFIG_DISPLAY_AER_FULL)
 282 static int print_83xx_arb_event(int force)
 283 {
 284         static char* event[] = {
 285                 "Address Time Out",
 286                 "Data Time Out",
 287                 "Address Only Transfer Type",
 288                 "External Control Word Transfer Type",
 289                 "Reserved Transfer Type",
 290                 "Transfer Error",
 291                 "reserved",
 292                 "reserved"
 293         };
 294         static char* master[] = {
 295                 "e300 Core Data Transaction",
 296                 "reserved",
 297                 "e300 Core Instruction Fetch",
 298                 "reserved",
 299                 "TSEC1",
 300                 "TSEC2",
 301                 "USB MPH",
 302                 "USB DR",
 303                 "Encryption Core",
 304                 "I2C Boot Sequencer",
 305                 "JTAG",
 306                 "reserved",
 307                 "eSDHC",
 308                 "PCI1",
 309                 "PCI2",
 310                 "DMA",
 311                 "QUICC Engine 00",
 312                 "QUICC Engine 01",
 313                 "QUICC Engine 10",
 314                 "QUICC Engine 11",
 315                 "reserved",
 316                 "reserved",
 317                 "reserved",
 318                 "reserved",
 319                 "SATA1",
 320                 "SATA2",
 321                 "SATA3",
 322                 "SATA4",
 323                 "reserved",
 324                 "PCI Express 1",
 325                 "PCI Express 2",
 326                 "TDM-DMAC"
 327         };
 328         static char *transfer[] = {
 329                 "Address-only, Clean Block",
 330                 "Address-only, lwarx reservation set",
 331                 "Single-beat or Burst write",
 332                 "reserved",
 333                 "Address-only, Flush Block",
 334                 "reserved",
 335                 "Burst write",
 336                 "reserved",
 337                 "Address-only, sync",
 338                 "Address-only, tlbsync",
 339                 "Single-beat or Burst read",
 340                 "Single-beat or Burst read",
 341                 "Address-only, Kill Block",
 342                 "Address-only, icbi",
 343                 "Burst read",
 344                 "reserved",
 345                 "Address-only, eieio",
 346                 "reserved",
 347                 "Single-beat write",
 348                 "reserved",
 349                 "ecowx - Illegal single-beat write",
 350                 "reserved",
 351                 "reserved",
 352                 "reserved",
 353                 "Address-only, TLB Invalidate",
 354                 "reserved",
 355                 "Single-beat or Burst read",
 356                 "reserved",
 357                 "eciwx - Illegal single-beat read",
 358                 "reserved",
 359                 "Burst read",
 360                 "reserved"
 361         };
 362
 363         int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
 364                     >> AEATR_EVENT_SHIFT;
 365         int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
 366                       >> AEATR_MSTR_ID_SHIFT;
 367         int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
 368                    >> AEATR_TBST_SHIFT;
 369         int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
 370                     >> AEATR_TSIZE_SHIFT;
 371         int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
 372                     >> AEATR_TTYPE_SHIFT;
 373
 374         if (!force && !gd->arch.arbiter_event_address)
 375                 return 0;
 376
 377         puts("Arbiter Event Status:\n");
 378         printf("       Event Address: 0x%08lX\n",
 379                gd->arch.arbiter_event_address);
 380         printf("       Event Type:    0x%1x  = %s\n", etype, event[etype]);
 381         printf("       Master ID:     0x%02x = %s\n", mstr_id, master[mstr_id]);
 382         printf("       Transfer Size: 0x%1x  = %d bytes\n", (tbst<<3) | tsize,
 383                                 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
 384         printf("       Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
 385
 386         return gd->arch.arbiter_event_address;
 387 }
 388
 389 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
 390
 391 static int print_83xx_arb_event(int force)
 392 {
 393         if (!force && !gd->arch.arbiter_event_address)
 394                 return 0;
 395
 396         printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
 397                 gd->arch.arbiter_event_attributes,
 398                 gd->arch.arbiter_event_address);
 399
 400         return gd->arch.arbiter_event_address;
 401 }
 402 #endif /* CONFIG_DISPLAY_AER_xxxx */
 403
 404 #ifndef CONFIG_CPU_MPC83XX
 405 /*
 406  * Figure out the cause of the reset
 407  */
 408 int prt_83xx_rsr(void)
 409 {
 410         static struct {
 411                 ulong mask;
 412                 char *desc;
 413         } bits[] = {
 414                 {
 415                 RSR_SWSR, "Software Soft"}, {
 416                 RSR_SWHR, "Software Hard"}, {
 417                 RSR_JSRS, "JTAG Soft"}, {
 418                 RSR_CSHR, "Check Stop"}, {
 419                 RSR_SWRS, "Software Watchdog"}, {
 420                 RSR_BMRS, "Bus Monitor"}, {
 421                 RSR_SRS,  "External/Internal Soft"}, {
 422                 RSR_HRS,  "External/Internal Hard"}
 423         };
 424         static int n = ARRAY_SIZE(bits);
 425         ulong rsr = gd->arch.reset_status;
 426         int i;
 427         char *sep;
 428
 429         puts("Reset Status:");
 430
 431         sep = " ";
 432         for (i = 0; i < n; i++)
 433                 if (rsr & bits[i].mask) {
 434                         printf("%s%s", sep, bits[i].desc);
 435                         sep = ", ";
 436                 }
 437         puts("\n");
 438
 439 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
 440         print_83xx_arb_event(rsr & RSR_BMRS);
 441 #endif
 442         puts("\n");
 443
 444         return 0;
 445 }
 446 #endif