1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2016 Andes Technology Corporation
4 * Nobuhiro Lin, Andes Technology Corporation <nobuhiro@andestech.com>
5 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
11 /* Hardware register bases */
13 /* Static Memory Controller (SRAM) */
14 #define CONFIG_FTSMC020_BASE 0xe0400000
16 #define CONFIG_FTDMAC020_BASE 0xf0c00000
17 /* AHB-to-APB Bridge */
18 #define CONFIG_FTAPBBRG020S_01_BASE 0xf0000000
20 #define CONFIG_RESERVED_01_BASE 0xe0500000
22 #define CONFIG_RESERVED_02_BASE 0xf0800000
24 #define CONFIG_RESERVED_03_BASE 0xf0900000
26 #define CONFIG_FTMAC100_BASE 0xe0100000
28 #define CONFIG_RESERVED_04_BASE 0xf1000000
30 /* APB Device definitions */
33 #define CONFIG_FTUART010_01_BASE 0xf0200000
35 #define CONFIG_FTUART010_02_BASE 0xf0300000
37 #define CONFIG_FTTMR010_BASE 0xf0400000
39 #define CONFIG_FTWDT010_BASE 0xf0500000
41 #define CONFIG_FTRTC010_BASE 0xf0600000
43 #define CONFIG_FTGPIO010_BASE 0xf0700000
45 #define CONFIG_FTIIC010_BASE 0xf0a00000
47 /* The following address was not defined in Linux */
49 /* Synchronous Serial Port Controller (SSP) 01 */
50 #define CONFIG_FTSSP010_01_BASE 0xf0d00000
51 #endif /* __AE3XX_H */