1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2011 Andes Technology Corporation
4 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
5 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
15 #include <asm/macro.h>
16 #include <generated/asm-offsets.h>
19 * parameters for the SDRAM controller
21 #define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
22 #define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
23 #define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
24 #define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
25 #define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
26 #define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
28 #define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
29 #define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
30 #define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
31 #define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
33 #define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
34 #define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
38 * for Orca and Emerald
40 #define BOARD_ID_REG 0x104
41 #define BOARD_ID_FAMILY_MASK 0xfff000
42 #define BOARD_ID_FAMILY_V5 0x556000
43 #define BOARD_ID_FAMILY_K7 0x74b000
46 * parameters for the static memory controller
48 #define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
49 #define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
51 #define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
52 #define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
55 * parameters for the ahbc controller
57 #define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
58 #define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
61 * for Orca and Emerald
63 #define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
64 #define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
67 * parameters for the pmu controoler
69 #define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
72 * numeric 7 segment display
75 write32 CONFIG_DEBUG_LED, \num
79 * Waiting for SDRAM to set up
82 li $r0, CONFIG_FTSDMC021_BASE
84 lwi $r1, [$r0+FTSDMC021_CR2]
94 * There are 2 bank connected to FTSMC020 on AG101
95 * BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
96 * we need to set onboard SDRAM before remap and relocation.
101 * for Orca and Emerald
102 * disable write protection and reset bank size
104 li $r0, SMC_BANK0_CR_A
109 li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
111 li $r4, BOARD_ID_FAMILY_MASK
113 li $r4, BOARD_ID_FAMILY_K7
115 beqz $r4, use_flash_16bit_boot
117 use_flash_32bit_boot:
122 use_flash_16bit_boot:
125 /* SRAM bank0 config */
130 /* config AHB Controller */
134 * config PMU controller
136 /* ftpmu010_dlldis_disable, must do it in lowleve_init */
138 setbf32 PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS ! 0x00010000
141 * config SDRAM controller
144 write32 SDMC_TP1_A, SDMC_TP1_D ! 0x00011312
146 write32 SDMC_TP2_A, SDMC_TP2_D ! 0x00480180
148 write32 SDMC_CR1_A, SDMC_CR1_D ! 0x00002326
151 write32 SDMC_CR2_A, FTSDMC021_CR2_IPREC ! 0x00000010
155 write32 SDMC_CR2_A, FTSDMC021_CR2_ISMR ! 0x00000004
159 write32 SDMC_CR2_A, FTSDMC021_CR2_IREF ! 0x00000008
167 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
174 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
183 #ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
190 #endif /* __NDS32_N1213_43U1H__ */
194 write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001800
195 write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001880
197 /* clear empty BSR registers */
199 li $r4, CONFIG_FTSDMC021_BASE
201 swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
202 swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
204 #ifdef CONFIG_MEM_REMAP
206 * Copy ROM code to SDRAM base for memory remap layout.
207 * This is not the real relocation, the real relocation is the function
208 * relocate_code() is start.S which supports the systems is memory
212 * Doing memory remap is essential for preparing some non-OS or RTOS
215 * This is also a must on ADP-AG101 board.
216 * The reason is because the ROM/FLASH circuit on PCB board.
217 * AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
218 * ROM/FLASH is used to boot.
220 * When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
221 * and the FLASH is connected to BANK1.
222 * When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
223 * and the FLASH is connected to BANK0.
224 * It will occur problem when doing flash probing if the flash is at
225 * BANK0 (0x00000000) while memory remapping was skipped.
227 * Other board like ADP-AG101P may not enable this since there is only
228 * a FLASH connected to bank0.
232 * for Orca and Emerald
233 * read sdram base address automatically
237 li $r4, 0xfff00000 /* r4 = bank6 base */
240 la $r5, _start@GOTOFF
249 * MEM remap bit is operational
250 * - use it to map writeable memory at 0x00000000, in place of flash
251 * - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
252 * - after remap: flash/rom 0x80000000, sdram: 0x00000000
255 write32 SDMC_B0_BSR_A, 0x00001000
256 write32 SDMC_B1_BSR_A, 0x00001200
257 li $r5, CONFIG_SYS_TEXT_BASE /* flash base address */
258 add $r11, $r11, $r5 /* add flash address offset for ret */
261 setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
264 * for Orca and Emerald
265 * extend sdram size from 256MB to 2GB
276 * for Orca and Emerald
277 * extend rom base from 256MB to 2GB
286 #endif /* #ifdef CONFIG_MEM_REMAP */
293 * Some of Andes CPU version support FPU coprocessor, if so,
294 * and toolchain support FPU instruction set, we should enable it.
296 #if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
298 mfsr $r0, $CPU_VER /* enable FPU if it exists */
301 beqz $r0, 1f /* skip if no COP */
302 mfsr $r0, $FUCOP_EXIST
304 beqz $r0, 1f /* skip if no FPU */
314 li $r8, (CONFIG_DEBUG_LED)
317 #endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */