1 menu "MIPS architecture"
8 default "mips32" if CPU_MIPS32
9 default "mips64" if CPU_MIPS64
12 prompt "Target select"
17 select HAS_FIXED_TIMER_FREQUENCY
18 select BOARD_EARLY_INIT_R
23 select DYNAMIC_IO_PORT_BASE
25 select MIPS_INSERT_BOOT_CONFIG
26 select SYS_CACHE_SHIFT_6
30 select PCI_MAP_SYSTEM_MEMORY
31 select ROM_EXCEPTION_VECTORS
32 select SUPPORTS_BIG_ENDIAN
33 select SUPPORTS_CPU_MIPS32_R1
34 select SUPPORTS_CPU_MIPS32_R2
35 select SUPPORTS_CPU_MIPS32_R6
36 select SUPPORTS_CPU_MIPS64_R1
37 select SUPPORTS_CPU_MIPS64_R2
38 select SUPPORTS_CPU_MIPS64_R6
39 select SUPPORTS_LITTLE_ENDIAN
44 bool "Support QCA/Atheros ath79"
45 select HAS_FIXED_TIMER_FREQUENCY
51 bool "Support MSCC VCore-III"
52 select HAS_FIXED_TIMER_FREQUENCY
57 bool "Support BMIPS SoCs"
58 select HAS_FIXED_TIMER_FREQUENCY
68 bool "Support MediaTek MIPS platforms"
69 select HAS_FIXED_TIMER_FREQUENCY
72 select DISPLAY_CPUINFO
84 select LAST_STAGE_INIT
87 select ROM_EXCEPTION_VECTORS
88 select SUPPORTS_CPU_MIPS32_R1
89 select SUPPORTS_CPU_MIPS32_R2
90 select SUPPORTS_LITTLE_ENDIAN
94 bool "Support Ingenic JZ47xx"
96 select HAS_FIXED_TIMER_FREQUENCY
101 bool "Support Marvell Octeon CN7xxx platforms"
102 select ARCH_EARLY_INIT_R
103 select CPU_CAVIUM_OCTEON
104 select DISPLAY_CPUINFO
105 select DMA_ADDR_T_64BIT
113 select MIPS_MACH_EARLY_INIT
114 select MIPS_TUNE_OCTEON3
115 select ROM_EXCEPTION_VECTORS
116 select SUPPORTS_BIG_ENDIAN
117 select SUPPORTS_CPU_MIPS64_OCTEON
124 bool "Support Microchip PIC32"
125 select HAS_FIXED_TIMER_FREQUENCY
131 bool "Support Boston"
132 select HAS_FIXED_TIMER_FREQUENCY
137 select SYS_CACHE_SHIFT_6
139 select OF_BOARD_SETUP
141 select ROM_EXCEPTION_VECTORS
142 select SUPPORTS_BIG_ENDIAN
143 select SUPPORTS_CPU_MIPS32_R1
144 select SUPPORTS_CPU_MIPS32_R2
145 select SUPPORTS_CPU_MIPS32_R6
146 select SUPPORTS_CPU_MIPS64_R1
147 select SUPPORTS_CPU_MIPS64_R2
148 select SUPPORTS_CPU_MIPS64_R6
149 select SUPPORTS_LITTLE_ENDIAN
152 config TARGET_XILFPGA
153 bool "Support Imagination Xilfpga"
154 select HAS_FIXED_TIMER_FREQUENCY
159 select SYS_CACHE_SHIFT_4
161 select ROM_EXCEPTION_VECTORS
162 select SUPPORTS_CPU_MIPS32_R1
163 select SUPPORTS_CPU_MIPS32_R2
164 select SUPPORTS_LITTLE_ENDIAN
167 This supports IMGTEC MIPSfpga platform
171 source "board/imgtec/boston/Kconfig"
172 source "board/imgtec/malta/Kconfig"
173 source "board/imgtec/xilfpga/Kconfig"
174 source "arch/mips/mach-ath79/Kconfig"
175 source "arch/mips/mach-mscc/Kconfig"
176 source "arch/mips/mach-bmips/Kconfig"
177 source "arch/mips/mach-jz47xx/Kconfig"
178 source "arch/mips/mach-pic32/Kconfig"
179 source "arch/mips/mach-mtmips/Kconfig"
180 source "arch/mips/mach-octeon/Kconfig"
185 prompt "CPU selection"
186 default CPU_MIPS32_R2
189 bool "MIPS32 Release 1"
190 depends on SUPPORTS_CPU_MIPS32_R1
193 Choose this option to build an U-Boot for release 1 through 5 of the
197 bool "MIPS32 Release 2"
198 depends on SUPPORTS_CPU_MIPS32_R2
201 Choose this option to build an U-Boot for release 2 through 5 of the
205 bool "MIPS32 Release 6"
206 depends on SUPPORTS_CPU_MIPS32_R6
209 Choose this option to build an U-Boot for release 6 or later of the
213 bool "MIPS64 Release 1"
214 depends on SUPPORTS_CPU_MIPS64_R1
217 Choose this option to build a kernel for release 1 through 5 of the
221 bool "MIPS64 Release 2"
222 depends on SUPPORTS_CPU_MIPS64_R2
225 Choose this option to build a kernel for release 2 through 5 of the
229 bool "MIPS64 Release 6"
230 depends on SUPPORTS_CPU_MIPS64_R6
233 Choose this option to build a kernel for release 6 or later of the
236 config CPU_MIPS64_OCTEON
237 bool "Marvell Octeon series of CPUs"
238 depends on SUPPORTS_CPU_MIPS64_OCTEON
241 Choose this option for Marvell Octeon CPUs. These CPUs are between
242 MIPS64 R5 and R6 with other extensions.
248 config ROM_EXCEPTION_VECTORS
249 bool "Build U-Boot image with exception vectors"
251 Enable this to include exception vectors in the U-Boot image. This is
252 required if the U-Boot entry point is equal to the address of the
253 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu,
254 U-Boot booted from parallel NOR flash).
255 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL).
256 In that case the image size will be reduced by 0x500 bytes.
258 config SYS_MIPS_TIMER_FREQ
259 int "Fixed MIPS CPU timer frequency in Hz"
260 depends on HAS_FIXED_TIMER_FREQUENCY
262 Configures a fixed CPU timer frequency.
265 hex "MIPS CM GCR Base Address"
267 default 0x16100000 if TARGET_BOSTON
270 The physical base address at which to map the MIPS Coherence Manager
271 Global Configuration Registers (GCRs). This should be set such that
272 the GCRs occupy a region of the physical address space which is
273 otherwise unused, or at minimum that software doesn't need to access.
275 config MIPS_CACHE_INDEX_BASE
276 hex "Index base address for cache initialisation"
277 default 0x80000000 if CPU_MIPS32
278 default 0xffffffff80000000 if CPU_MIPS64
280 This is the base address for a memory block, which is used for
281 initialising the cache lines. This is also the base address of a memory
282 block which is used for loading and filling cache lines when
283 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected.
284 Normally this is CKSEG0. If the MIPS system needs to move this block
285 to some SRAM or ScratchPad RAM, adapt this option accordingly.
287 config MIPS_MACH_EARLY_INIT
288 bool "Enable mach specific very early init code"
290 Use this to enable the call to mips_mach_early_init() very early
291 from start.S. This function can be used e.g. to do some very early
292 CPU / SoC intitialization or image copying. Its called very early
293 and at this stage the PC might not match the linking address
294 (CONFIG_TEXT_BASE) - no absolute jump done until this call.
296 config MIPS_CACHE_SETUP
297 bool "Allow generic start code to initialize and setup caches"
298 default n if SKIP_LOWLEVEL_INIT
301 This allows the generic start code to invoke the generic initialization
302 of the CPU caches. Disabling this can be useful for RAM boot scenarios
303 (EJTAG, SPL payload) or for machines which don't need cache initialization
304 or which want to provide their own cache implementation.
308 config MIPS_CACHE_DISABLE
309 bool "Allow generic start code to initially disable caches"
310 default n if SKIP_LOWLEVEL_INIT
313 This allows the generic start code to initially disable the CPU caches
314 and run uncached until the caches are initialized and enabled. Disabling
315 this can be useful on machines which don't need cache initialization or
316 which want to provide their own cache implementation.
320 config MIPS_RELOCATION_TABLE_SIZE
321 hex "Relocation table size"
325 A table of relocation data will be appended to the U-Boot binary
326 and parsed in relocate_code() to fix up all offsets in the relocated
329 This option allows the amount of space reserved for the table to be
330 adjusted in a range from 256 up to 64k. The default is 32k and should
331 be ok in most cases. Reduce this value to shrink the size of U-Boot
334 The build will fail and a valid size suggested if this is too small.
336 If unsure, leave at the default value.
338 config RESTORE_EXCEPTION_VECTOR_BASE
339 bool "Restore exception vector base before booting linux kernel"
341 In U-Boot the exception vector base will be moved to top of memory,
342 to be used to display register dump when exception occurs.
343 But some old linux kernel does not honor the base set in CP0_EBASE.
344 A modified exception vector base will cause kernel crash.
346 This option will restore the exception vector base to its previous
351 config OVERRIDE_EXCEPTION_VECTOR_BASE
352 bool "Override the exception vector base to be restored"
353 depends on RESTORE_EXCEPTION_VECTOR_BASE
355 Enable this option if you want to use a different exception vector
356 base rather than the previously saved one.
358 config NEW_EXCEPTION_VECTOR_BASE
359 hex "New exception vector base"
360 depends on OVERRIDE_EXCEPTION_VECTOR_BASE
361 range 0x80000000 0xbffff000
364 The exception vector base to be restored before booting linux kernel
366 config INIT_STACK_WITHOUT_MALLOC_F
367 bool "Do not reserve malloc space on initial stack"
369 Enable this option if you don't want to reserve malloc space on
370 initial stack. This is useful if the initial stack can't hold large
371 malloc space. Platform should set the malloc_base later when DRAM is
374 config SPL_INIT_STACK_WITHOUT_MALLOC_F
375 bool "Do not reserve malloc space on initial stack in SPL"
377 Enable this option if you don't want to reserve malloc space on
378 initial stack. This is useful if the initial stack can't hold large
379 malloc space. Platform should set the malloc_base later when DRAM is
382 config SPL_LOADER_SUPPORT
385 Enable this option if you want to use SPL loaders without DM enabled.
389 menu "OS boot interface"
391 config MIPS_BOOT_CMDLINE_LEGACY
392 bool "Hand over legacy command line to Linux kernel"
395 Enable this option if you want U-Boot to hand over the Yamon-style
396 command line to the kernel. All bootargs will be prepared as argc/argv
397 compatible list. The argument count (argc) is stored in register $a0.
398 The address of the argument list (argv) is stored in register $a1.
400 config MIPS_BOOT_ENV_LEGACY
401 bool "Hand over legacy environment to Linux kernel"
404 Enable this option if you want U-Boot to hand over the Yamon-style
405 environment to the kernel. Information like memory size, initrd
406 address and size will be prepared as zero-terminated key/value list.
407 The address of the environment is stored in register $a2.
410 bool "Hand over a flattened device tree to Linux kernel"
412 Enable this option if you want U-Boot to hand over a flattened
413 device tree to the kernel. According to UHI register $a0 will be set
414 to -2 and the FDT address is stored in $a1.
418 config SUPPORTS_BIG_ENDIAN
421 config SUPPORTS_LITTLE_ENDIAN
424 config SUPPORTS_CPU_MIPS32_R1
427 config SUPPORTS_CPU_MIPS32_R2
430 config SUPPORTS_CPU_MIPS32_R6
433 config SUPPORTS_CPU_MIPS64_R1
436 config SUPPORTS_CPU_MIPS64_R2
439 config SUPPORTS_CPU_MIPS64_R6
442 config SUPPORTS_CPU_MIPS64_OCTEON
445 config HAS_FIXED_TIMER_FREQUENCY
448 config CPU_CAVIUM_OCTEON
453 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6
457 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6
458 default y if CPU_MIPS64_OCTEON
463 config MIPS_TUNE_14KC
466 config MIPS_TUNE_24KC
469 config MIPS_TUNE_34KC
472 config MIPS_TUNE_74KC
475 config MIPS_TUNE_OCTEON3
487 config SYS_MIPS_CACHE_INIT_RAM_LOAD
490 config MIPS_INIT_STACK_IN_SRAM
493 Select this if the initial stack frame could be setup in SRAM.
494 Normally the initial stack frame is set up in DRAM which is often
495 only available after lowlevel_init. With this option the initial
496 stack frame and the early C environment is set up before
497 lowlevel_init. Thus lowlevel_init does not need to be implemented
500 config MIPS_SRAM_INIT
502 depends on MIPS_INIT_STACK_IN_SRAM
504 Select this if the SRAM for initial stack needs to be initialized
505 before it can be used. If enabled, a function mips_sram_init() will
506 be called just before setup_stack_gd.
508 config DMA_ADDR_T_64BIT
511 Select this to enable 64-bit DMA addressing
513 config SYS_DCACHE_SIZE
517 The total size of the L1 Dcache, if known at compile time.
519 config SYS_DCACHE_LINE_SIZE
523 The size of L1 Dcache lines, if known at compile time.
525 config SYS_ICACHE_SIZE
529 The total size of the L1 ICache, if known at compile time.
531 config SYS_ICACHE_LINE_SIZE
535 The size of L1 Icache lines, if known at compile time.
537 config SYS_SCACHE_LINE_SIZE
541 The size of L2 cache lines, if known at compile time.
544 config SYS_CACHE_SIZE_AUTO
545 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
546 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \
547 SYS_SCACHE_LINE_SIZE = 0
549 Select this (or let it be auto-selected by not defining any cache
550 sizes) in order to allow U-Boot to automatically detect the sizes
551 of caches at runtime. This has a small cost in code size & runtime
552 so if you know the cache configuration for your system at compile
553 time it would be beneficial to configure it.
558 Select this if your system includes an L2 cache and you want U-Boot
559 to initialise & maintain it.
561 config DYNAMIC_IO_PORT_BASE
567 Select this if your system contains a MIPS Coherence Manager and you
568 wish U-Boot to configure it or make use of it to retrieve system
569 information such as cache configuration.
571 config MIPS_INSERT_BOOT_CONFIG
574 Enable this to insert some board-specific boot configuration in
575 the U-Boot binary at offset 0x10.
577 config MIPS_BOOT_CONFIG_WORD0
579 depends on MIPS_INSERT_BOOT_CONFIG
580 default 0x420 if TARGET_MALTA
583 Value which is inserted as boot config word 0.
585 config MIPS_BOOT_CONFIG_WORD1
587 depends on MIPS_INSERT_BOOT_CONFIG
590 Value which is inserted as boot config word 1.