1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
9 #include <clock_legacy.h>
10 #include <asm/global_data.h>
11 #include <asm/processor.h>
13 #include <asm/immap.h>
16 DECLARE_GLOBAL_DATA_PTR;
19 * Low Power Divider specifications
21 #define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */
22 #define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */
24 #define CLOCK_PLL_FVCO_MAX 540000000
25 #define CLOCK_PLL_FVCO_MIN 300000000
27 #define CLOCK_PLL_FSYS_MAX 266666666
28 #define CLOCK_PLL_FSYS_MIN 100000000
31 void clock_enter_limp(int lpdiv)
33 ccm_t *ccm = (ccm_t *)MMAP_CCM;
36 /* Check bounds of divider */
37 if (lpdiv < CLOCK_LPD_MIN)
38 lpdiv = CLOCK_LPD_MIN;
39 if (lpdiv > CLOCK_LPD_MAX)
40 lpdiv = CLOCK_LPD_MAX;
42 /* Round divider down to nearest power of two */
43 for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
45 #ifdef CONFIG_MCF5445x
46 /* Apply the divider to the system clock */
47 clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
50 /* Enable Limp Mode */
51 setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
55 * brief Exit Limp mode
56 * warning The PLL should be set and locked prior to exiting Limp mode
58 void clock_exit_limp(void)
60 ccm_t *ccm = (ccm_t *)MMAP_CCM;
61 pll_t *pll = (pll_t *)MMAP_PLL;
64 clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
66 /* Wait for the PLL to lock */
67 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
71 #ifdef CONFIG_MCF5441x
72 void setup_5441x_clocks(void)
74 ccm_t *ccm = (ccm_t *)MMAP_CCM;
75 pll_t *pll = (pll_t *)MMAP_PLL;
76 int temp, vco = 0, bootmod_ccr, pdr;
78 bootmod_ccr = (in_be16(&ccm->ccr) & CCM_CCR_BOOTMOD) >> 14;
80 switch (bootmod_ccr) {
82 out_be32(&pll->pcr, 0x00000013);
83 out_be32(&pll->pdr, 0x00e70c61);
92 /*Change frequency for Modelo SER1 USB host*/
93 #ifdef CONFIG_LOW_MCFCLK
94 temp = in_be32(&pll->pcr);
97 out_be32(&pll->pcr, temp);
99 temp = in_be32(&pll->pdr);
102 out_be32(&pll->pdr, temp);
106 setbits_be16(&ccm->misccr2, 0x02);
108 vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) *
109 CONFIG_SYS_INPUT_CLKSRC;
110 gd->arch.vco_clk = vco;
112 gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
114 pdr = in_be32(&pll->pdr);
115 temp = (pdr & PLL_DR_OUTDIV1_BITS) + 1;
116 gd->cpu_clk = vco / temp; /* cpu clock */
117 gd->arch.flb_clk = vco / temp; /* FlexBus clock */
118 gd->arch.flb_clk >>= 1;
119 if (in_be16(&ccm->misccr2) & 2) /* fsys/4 */
120 gd->arch.flb_clk >>= 1;
122 temp = ((pdr & PLL_DR_OUTDIV2_BITS) >> 5) + 1;
123 gd->bus_clk = vco / temp; /* bus clock */
125 temp = ((pdr & PLL_DR_OUTDIV3_BITS) >> 10) + 1;
126 gd->arch.sdhc_clk = vco / temp;
130 #ifdef CONFIG_MCF5445x
131 void setup_5445x_clocks(void)
133 ccm_t *ccm = (ccm_t *)MMAP_CCM;
134 pll_t *pll = (pll_t *)MMAP_PLL;
135 int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
136 int pllmult_pci[] = { 12, 6, 16, 8 };
137 int vco = 0, temp, fbtemp, pcrvalue;
138 int *pPllmult = NULL;
146 /* To determine PCI is present or not */
147 if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
148 ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
149 pPllmult = &pllmult_pci[0];
150 fbpll_mask = 3; /* 11b */
155 pPllmult = &pllmult_nopci[0];
156 fbpll_mask = 7; /* 111b */
163 #ifdef CONFIG_M54451EVB
164 /* No external logic to read the bootmode, hard coded from built */
170 /* default value is 16 mul, set to 20 mul */
171 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
172 out_be32(&pll->pcr, pcrvalue);
173 while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
180 vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
182 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
183 /* invaild range, re-set in PCR */
184 int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
187 j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
188 for (i = j; i < 0xFF; i++) {
189 vco = i * CONFIG_SYS_INPUT_CLKSRC;
190 if (vco >= CLOCK_PLL_FVCO_MIN) {
192 if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
198 pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
199 fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
200 pcrvalue |= ((i << 24) | fbtemp);
202 out_be32(&pll->pcr, pcrvalue);
204 gd->arch.vco_clk = vco; /* Vco clock */
205 } else if (bootmode == 2) {
207 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
208 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
210 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
211 pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
212 out_be32(&pll->pcr, pcrvalue);
213 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
215 gd->arch.vco_clk = vco; /* Vco clock */
216 } else if (bootmode == 3) {
218 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
219 gd->arch.vco_clk = vco; /* Vco clock */
222 if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
225 gd->arch.inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
227 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
228 gd->cpu_clk = vco / temp; /* cpu clock */
230 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
231 gd->bus_clk = vco / temp; /* bus clock */
233 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
234 gd->arch.flb_clk = vco / temp; /* FlexBus clock */
238 temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
239 gd->pci_clk = vco / temp; /* PCI clock */
244 #ifdef CONFIG_SYS_I2C_FSL
245 gd->arch.i2c1_clk = gd->bus_clk;
250 /* get_clocks() fills in gd->cpu_clock and gd->bus_clk */
253 #ifdef CONFIG_MCF5441x
254 setup_5441x_clocks();
256 #ifdef CONFIG_MCF5445x
257 setup_5445x_clocks();
260 #ifdef CONFIG_SYS_FSL_I2C
261 gd->arch.i2c1_clk = gd->bus_clk;