arch/arm/mach-uniphier/dram/ddrphy-ld4.c

   1 /*
   2  * Copyright (C) 2014      Panasonic Corporation
   3  * Copyright (C) 2015-2016 Socionext Inc.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/errno.h>
  10 #include <linux/io.h>
  11 #include <linux/printk.h>
  12
  13 #include "ddrphy-init.h"
  14 #include "ddrphy-regs.h"
  15
  16 enum dram_freq {
  17         DRAM_FREQ_1333M,
  18         DRAM_FREQ_1600M,
  19         DRAM_FREQ_NR,
  20 };
  21
  22 static u32 ddrphy_ptr0[DRAM_FREQ_NR] = {0x0a806844, 0x0c807d04};
  23 static u32 ddrphy_ptr1[DRAM_FREQ_NR] = {0x208e0124, 0x2710015E};
  24 static u32 ddrphy_ptr3[DRAM_FREQ_NR] = {0x0f051616, 0x12061A80};
  25 static u32 ddrphy_ptr4[DRAM_FREQ_NR] = {0x06ae08d6, 0x08027100};
  26 static u32 ddrphy_dtpr0[DRAM_FREQ_NR] = {0x85589955, 0x999cbb66};
  27 static u32 ddrphy_dtpr1[DRAM_FREQ_NR] = {0x1a8363c0, 0x1a878400};
  28 static u32 ddrphy_dtpr2[DRAM_FREQ_NR] = {0x5002c200, 0xa00214f8};
  29 static u32 ddrphy_mr0[DRAM_FREQ_NR] = {0x00000b51, 0x00000d71};
  30 static u32 ddrphy_mr2[DRAM_FREQ_NR] = {0x00000290, 0x00000298};
  31
  32 int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus)
  33 {
  34         enum dram_freq freq_e;
  35         u32 tmp;
  36
  37         switch (freq) {
  38         case 1333:
  39                 freq_e = DRAM_FREQ_1333M;
  40                 break;
  41         case 1600:
  42                 freq_e = DRAM_FREQ_1600M;
  43                 break;
  44         default:
  45                 pr_err("unsupported DRAM frequency %d MHz\n", freq);
  46                 return -EINVAL;
  47         }
  48
  49         writel(0x0300c473, phy_base + PHY_PGCR1);
  50         writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0);
  51         writel(ddrphy_ptr1[freq_e], phy_base + PHY_PTR1);
  52         writel(0x00083DEF, phy_base + PHY_PTR2);
  53         writel(ddrphy_ptr3[freq_e], phy_base + PHY_PTR3);
  54         writel(ddrphy_ptr4[freq_e], phy_base + PHY_PTR4);
  55         writel(0xF004001A, phy_base + PHY_DSGCR);
  56
  57         /* change the value of the on-die pull-up/pull-down registors */
  58         tmp = readl(phy_base + PHY_DXCCR);
  59         tmp &= ~0x0ee0;
  60         tmp |= PHY_DXCCR_DQSNRES_688_OHM | PHY_DXCCR_DQSRES_688_OHM;
  61         writel(tmp, phy_base + PHY_DXCCR);
  62
  63         writel(0x0000040B, phy_base + PHY_DCR);
  64         writel(ddrphy_dtpr0[freq_e], phy_base + PHY_DTPR0);
  65         writel(ddrphy_dtpr1[freq_e], phy_base + PHY_DTPR1);
  66         writel(ddrphy_dtpr2[freq_e], phy_base + PHY_DTPR2);
  67         writel(ddrphy_mr0[freq_e], phy_base + PHY_MR0);
  68         writel(0x00000006, phy_base + PHY_MR1);
  69         writel(ddrphy_mr2[freq_e], phy_base + PHY_MR2);
  70         writel(ddr3plus ? 0x00000800 : 0x00000000, phy_base + PHY_MR3);
  71
  72         while (!(readl(phy_base + PHY_PGSR0) & PHY_PGSR0_IDONE))
  73                 ;
  74
  75         writel(0x0300C473, phy_base + PHY_PGCR1);
  76         writel(0x0000005D, phy_base + PHY_ZQ_BASE + PHY_ZQ_CR1);
  77
  78         return 0;
  79 }