arch/arm/mach-socfpga/system_manager_gen5.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
   4  */
   5
   6 #include <common.h>
   7 #include <asm/io.h>
   8 #include <asm/arch/system_manager.h>
   9 #include <asm/arch/fpga_manager.h>
  10
  11 /*
  12  * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
  13  * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
  14  * CONFIG_SYSMGR_ISWGRP_HANDOFF.
  15  */
  16 static void populate_sysmgr_fpgaintf_module(void)
  17 {
  18         u32 handoff_val = 0;
  19
  20         /* ISWGRP_HANDOFF_FPGAINTF */
  21         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_ISWGRP_HANDOFF_OFFSET(2));
  22
  23         /* Enable the signal for those HPS peripherals that use FPGA. */
  24         if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_NAND_USEFPGA) ==
  25             SYSMGR_FPGAINTF_USEFPGA)
  26                 handoff_val |= SYSMGR_FPGAINTF_NAND;
  27         if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_RGMII1_USEFPGA) ==
  28             SYSMGR_FPGAINTF_USEFPGA)
  29                 handoff_val |= SYSMGR_FPGAINTF_EMAC1;
  30         if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SDMMC_USEFPGA) ==
  31             SYSMGR_FPGAINTF_USEFPGA)
  32                 handoff_val |= SYSMGR_FPGAINTF_SDMMC;
  33         if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_RGMII0_USEFPGA) ==
  34             SYSMGR_FPGAINTF_USEFPGA)
  35                 handoff_val |= SYSMGR_FPGAINTF_EMAC0;
  36         if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SPIM0_USEFPGA) ==
  37             SYSMGR_FPGAINTF_USEFPGA)
  38                 handoff_val |= SYSMGR_FPGAINTF_SPIM0;
  39         if (readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SPIM1_USEFPGA) ==
  40             SYSMGR_FPGAINTF_USEFPGA)
  41                 handoff_val |= SYSMGR_FPGAINTF_SPIM1;
  42
  43         /* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
  44         based on pinmux setting */
  45         setbits_le32(socfpga_get_sysmgr_addr() +
  46                      SYSMGR_ISWGRP_HANDOFF_OFFSET(2),
  47                      handoff_val);
  48
  49         handoff_val = readl(socfpga_get_sysmgr_addr() +
  50                             SYSMGR_ISWGRP_HANDOFF_OFFSET(2));
  51         if (fpgamgr_test_fpga_ready()) {
  52                 /* Enable the required signals only */
  53                 writel(handoff_val,
  54                        socfpga_get_sysmgr_addr() +
  55                        SYSMGR_GEN5_FPGAINFGRP_MODULE);
  56         }
  57 }
  58
  59 /*
  60  * Configure all the pin muxes
  61  */
  62 void sysmgr_pinmux_init(void)
  63 {
  64         u32 regs = (u32)socfpga_get_sysmgr_addr() + SYSMGR_GEN5_EMACIO;
  65         const u8 *sys_mgr_init_table;
  66         unsigned int len;
  67         int i;
  68
  69         sysmgr_get_pinmux_table(&sys_mgr_init_table, &len);
  70
  71         for (i = 0; i < len; i++) {
  72                 writel(sys_mgr_init_table[i], regs);
  73                 regs += sizeof(regs);
  74         }
  75
  76         populate_sysmgr_fpgaintf_module();
  77 }
  78
  79 /*
  80  * This bit allows the bootrom to configure the IOs after a warm reset.
  81  */
  82 void sysmgr_config_warmrstcfgio(int enable)
  83 {
  84         if (enable)
  85                 setbits_le32(socfpga_get_sysmgr_addr() +
  86                              SYSMGR_GEN5_ROMCODEGRP_CTRL,
  87                              SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
  88         else
  89                 clrbits_le32(socfpga_get_sysmgr_addr() +
  90                              SYSMGR_GEN5_ROMCODEGRP_CTRL,
  91                              SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
  92 }