arch/arm/mach-socfpga/Kconfig

   1 if ARCH_SOCFPGA
   2
   3 config SPL_LIBCOMMON_SUPPORT
   4         default y
   5
   6 config SPL_LIBDISK_SUPPORT
   7         default y
   8
   9 config TARGET_SOCFPGA_ARRIA5
  10         bool
  11         select TARGET_SOCFPGA_GEN5
  12
  13 config TARGET_SOCFPGA_CYCLONE5
  14         bool
  15         select TARGET_SOCFPGA_GEN5
  16
  17 config TARGET_SOCFPGA_GEN5
  18         bool
  19
  20 choice
  21         prompt "Altera SOCFPGA board select"
  22         optional
  23
  24 config TARGET_SOCFPGA_ARRIA5_SOCDK
  25         bool "Altera SOCFPGA SoCDK (Arria V)"
  26         select TARGET_SOCFPGA_ARRIA5
  27
  28 config TARGET_SOCFPGA_CYCLONE5_SOCDK
  29         bool "Altera SOCFPGA SoCDK (Cyclone V)"
  30         select TARGET_SOCFPGA_CYCLONE5
  31
  32 config TARGET_SOCFPGA_DENX_MCVEVK
  33         bool "DENX MCVEVK (Cyclone V)"
  34         select TARGET_SOCFPGA_CYCLONE5
  35
  36 config TARGET_SOCFPGA_EBV_SOCRATES
  37         bool "EBV SoCrates (Cyclone V)"
  38         select TARGET_SOCFPGA_CYCLONE5
  39
  40 config TARGET_SOCFPGA_IS1
  41         bool "IS1 (Cyclone V)"
  42         select TARGET_SOCFPGA_CYCLONE5
  43
  44 config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  45         bool "samtec VIN|ING FPGA (Cyclone V)"
  46         select TARGET_SOCFPGA_CYCLONE5
  47
  48 config TARGET_SOCFPGA_SR1500
  49         bool "SR1500 (Cyclone V)"
  50         select TARGET_SOCFPGA_CYCLONE5
  51
  52 config TARGET_SOCFPGA_TERASIC_DE0_NANO
  53         bool "Terasic DE0-Nano-Atlas (Cyclone V)"
  54         select TARGET_SOCFPGA_CYCLONE5
  55
  56 config TARGET_SOCFPGA_TERASIC_SOCKIT
  57         bool "Terasic SoCkit (Cyclone V)"
  58         select TARGET_SOCFPGA_CYCLONE5
  59
  60 endchoice
  61
  62 config SYS_BOARD
  63         default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  64         default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  65         default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  66         default "is1" if TARGET_SOCFPGA_IS1
  67         default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
  68         default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  69         default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  70         default "sr1500" if TARGET_SOCFPGA_SR1500
  71         default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  72
  73 config SYS_VENDOR
  74         default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
  75         default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  76         default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
  77         default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
  78         default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  79         default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  80         default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
  81
  82 config SYS_SOC
  83         default "socfpga"
  84
  85 config SYS_CONFIG_NAME
  86         default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
  87         default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
  88         default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
  89         default "socfpga_is1" if TARGET_SOCFPGA_IS1
  90         default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
  91         default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
  92         default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
  93         default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
  94         default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
  95
  96 endif