arch/arm/mach-omap2/omap4/hwinit.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *
   4  * Common functions for OMAP4 based boards
   5  *
   6  * (C) Copyright 2010
   7  * Texas Instruments, <www.ti.com>
   8  *
   9  * Author :
  10  *      Aneesh V        <aneesh@ti.com>
  11  *      Steve Sakoman   <steve@sakoman.com>
  12  */
  13 #include <common.h>
  14 #include <palmas.h>
  15 #include <asm/armv7.h>
  16 #include <asm/arch/cpu.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <linux/sizes.h>
  19 #include <asm/emif.h>
  20 #include <asm/arch/gpio.h>
  21 #include <asm/omap_common.h>
  22
  23 u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
  24
  25 static const struct gpio_bank gpio_bank_44xx[6] = {
  26         { (void *)OMAP44XX_GPIO1_BASE },
  27         { (void *)OMAP44XX_GPIO2_BASE },
  28         { (void *)OMAP44XX_GPIO3_BASE },
  29         { (void *)OMAP44XX_GPIO4_BASE },
  30         { (void *)OMAP44XX_GPIO5_BASE },
  31         { (void *)OMAP44XX_GPIO6_BASE },
  32 };
  33
  34 const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
  35
  36 #ifdef CONFIG_SPL_BUILD
  37 /*
  38  * Some tuning of IOs for optimal power and performance
  39  */
  40 void do_io_settings(void)
  41 {
  42         u32 lpddr2io;
  43
  44         u32 omap4_rev = omap_revision();
  45
  46         if (omap4_rev == OMAP4430_ES1_0)
  47                 lpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;
  48         else if (omap4_rev == OMAP4430_ES2_0)
  49                 lpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;
  50         else
  51                 lpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;
  52
  53         /* EMIF1 */
  54         writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
  55         writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
  56         /* No pull for GR10 as per hw team's recommendation */
  57         writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
  58                 (*ctrl)->control_lpddr2io1_2);
  59         writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
  60
  61         /* EMIF2 */
  62         writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
  63         writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
  64         /* No pull for GR10 as per hw team's recommendation */
  65         writel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,
  66                 (*ctrl)->control_lpddr2io2_2);
  67         writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
  68
  69         /*
  70          * Some of these settings (TRIM values) come from eFuse and are
  71          * in turn programmed in the eFuse at manufacturing time after
  72          * calibration of the device. Do the software over-ride only if
  73          * the device is not correctly trimmed
  74          */
  75         if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
  76
  77                 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
  78                         (*ctrl)->control_ldosram_iva_voltage_ctrl);
  79
  80                 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
  81                         (*ctrl)->control_ldosram_mpu_voltage_ctrl);
  82
  83                 writel(LDOSRAM_VOLT_CTRL_OVERRIDE,
  84                         (*ctrl)->control_ldosram_core_voltage_ctrl);
  85         }
  86
  87         /*
  88          * Over-ride the register
  89          *      i. unconditionally for all 4430
  90          *      ii. only if un-trimmed for 4460
  91          */
  92         if (!readl((*ctrl)->control_efuse_1))
  93                 writel(CONTROL_EFUSE_1_OVERRIDE, (*ctrl)->control_efuse_1);
  94
  95         if ((omap4_rev < OMAP4460_ES1_0) || !readl((*ctrl)->control_efuse_2))
  96                 writel(CONTROL_EFUSE_2_OVERRIDE, (*ctrl)->control_efuse_2);
  97 }
  98 #endif /* CONFIG_SPL_BUILD */
  99
 100 /* dummy fuction for omap4 */
 101 void config_data_eye_leveling_samples(u32 emif_base)
 102 {
 103 }
 104
 105 void init_omap_revision(void)
 106 {
 107         /*
 108          * For some of the ES2/ES1 boards ID_CODE is not reliable:
 109          * Also, ES1 and ES2 have different ARM revisions
 110          * So use ARM revision for identification
 111          */
 112         unsigned int arm_rev = cortex_rev();
 113
 114         switch (arm_rev) {
 115         case MIDR_CORTEX_A9_R0P1:
 116                 *omap_si_rev = OMAP4430_ES1_0;
 117                 break;
 118         case MIDR_CORTEX_A9_R1P2:
 119                 switch (readl(CONTROL_ID_CODE)) {
 120                 case OMAP4_CONTROL_ID_CODE_ES2_0:
 121                         *omap_si_rev = OMAP4430_ES2_0;
 122                         break;
 123                 case OMAP4_CONTROL_ID_CODE_ES2_1:
 124                         *omap_si_rev = OMAP4430_ES2_1;
 125                         break;
 126                 case OMAP4_CONTROL_ID_CODE_ES2_2:
 127                         *omap_si_rev = OMAP4430_ES2_2;
 128                         break;
 129                 default:
 130                         *omap_si_rev = OMAP4430_ES2_0;
 131                         break;
 132                 }
 133                 break;
 134         case MIDR_CORTEX_A9_R1P3:
 135                 *omap_si_rev = OMAP4430_ES2_3;
 136                 break;
 137         case MIDR_CORTEX_A9_R2P10:
 138                 switch (readl(CONTROL_ID_CODE)) {
 139                 case OMAP4470_CONTROL_ID_CODE_ES1_0:
 140                         *omap_si_rev = OMAP4470_ES1_0;
 141                         break;
 142                 case OMAP4460_CONTROL_ID_CODE_ES1_1:
 143                         *omap_si_rev = OMAP4460_ES1_1;
 144                         break;
 145                 case OMAP4460_CONTROL_ID_CODE_ES1_0:
 146                 default:
 147                         *omap_si_rev = OMAP4460_ES1_0;
 148                         break;
 149                 }
 150                 break;
 151         default:
 152                 *omap_si_rev = OMAP4430_SILICON_ID_INVALID;
 153                 break;
 154         }
 155 }
 156
 157 void omap_die_id(unsigned int *die_id)
 158 {
 159         die_id[0] = readl((*ctrl)->control_std_fuse_die_id_0);
 160         die_id[1] = readl((*ctrl)->control_std_fuse_die_id_1);
 161         die_id[2] = readl((*ctrl)->control_std_fuse_die_id_2);
 162         die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
 163 }
 164
 165 #ifndef CONFIG_SYS_L2CACHE_OFF
 166 void v7_outer_cache_enable(void)
 167 {
 168         omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 1);
 169 }
 170
 171 void v7_outer_cache_disable(void)
 172 {
 173         omap_smc1(OMAP4_SERVICE_PL310_CONTROL_REG_SET, 0);
 174 }
 175 #endif /* !CONFIG_SYS_L2CACHE_OFF */
 176
 177 void vmmc_pbias_config(uint voltage)
 178 {
 179         u32 value = 0;
 180
 181         value = readl((*ctrl)->control_pbiaslite);
 182         value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
 183         writel(value, (*ctrl)->control_pbiaslite);
 184         value = readl((*ctrl)->control_pbiaslite);
 185         value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
 186         writel(value, (*ctrl)->control_pbiaslite);
 187 }