1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Lei Wen <leiwen@marvell.com>
9 * This file should be included in board config header file.
11 * It supports common definitions for Kirkwood platform
17 #if defined (CONFIG_KW88F6281)
18 #include <asm/arch/kw88f6281.h>
19 #elif defined (CONFIG_KW88F6192)
20 #include <asm/arch/kw88f6192.h>
22 #error "SOC Name not defined"
23 #endif /* CONFIG_KW88F6281 */
25 #include <asm/arch/soc.h>
26 #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
27 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
28 #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
31 * By default kwbimage.cfg from board specific folder is used
32 * If for some board, different configuration file need to be used,
33 * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
35 #ifndef CONFIG_SYS_KWD_CONFIG
36 #define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg
37 #endif /* CONFIG_SYS_KWD_CONFIG */
39 /* Kirkwood has 2k of Security SRAM, use it for SP */
40 #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
41 #define CONFIG_NR_DRAM_BANKS_MAX 2
43 #define CONFIG_I2C_MVTWSI_BASE0 KW_TWSI_BASE
44 #define MV_UART_CONSOLE_BASE KW_UART0_BASE
45 #define MV_SATA_BASE KW_SATA_BASE
46 #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
47 #define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
52 #ifdef CONFIG_CMD_NAND
53 #define CONFIG_NAND_KIRKWOOD
54 #define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
55 #define NAND_ALLOW_ERASE_ALL 1
59 * SPI Flash configuration
62 #define CONFIG_HARD_SPI 1
63 #ifndef CONFIG_ENV_SPI_BUS
64 # define CONFIG_ENV_SPI_BUS 0
66 #ifndef CONFIG_ENV_SPI_CS
67 # define CONFIG_ENV_SPI_CS 0
69 #ifndef CONFIG_ENV_SPI_MAX_HZ
70 # define CONFIG_ENV_SPI_MAX_HZ 50000000
75 * Ethernet Driver configuration
78 #define CONFIG_NETCONSOLE /* include NetConsole support */
79 #define CONFIG_MII /* expose smi ove miiphy interface */
80 #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
81 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
82 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
83 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
84 #endif /* CONFIG_CMD_NET */
90 #define CONFIG_EHCI_IS_TDI
91 #endif /* CONFIG_CMD_USB */
94 * IDE Support on SATA ports
98 #define CONFIG_IDE_PREINIT
99 #define CONFIG_MVSATA_IDE_USE_PORT1
100 /* Needs byte-swapping for ATA data register */
101 #define CONFIG_IDE_SWAP_IO
102 /* Data, registers and alternate blocks are at the same offset */
103 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
104 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
105 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
106 /* Each 8-bit ATA register is aligned to a 4-bytes address */
107 #define CONFIG_SYS_ATA_STRIDE 4
108 /* Controller supports 48-bits LBA addressing */
110 /* CONFIG_IDE requires some #defines for ATA registers */
111 #define CONFIG_SYS_IDE_MAXBUS 2
112 #define CONFIG_SYS_IDE_MAXDEVICE 2
113 /* ATA registers base is at SATA controller base */
114 #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
115 #endif /* CONFIG_IDE */
120 #ifdef CONFIG_CMD_I2C
121 #ifndef CONFIG_SYS_I2C_SOFT
122 #define CONFIG_SYS_I2C
123 #define CONFIG_SYS_I2C_MVTWSI
125 #define CONFIG_SYS_I2C_SLAVE 0x0
126 #define CONFIG_SYS_I2C_SPEED 100000
129 /* Use common timer */
130 #define CONFIG_SYS_TIMER_COUNTS_DOWN
131 #define CONFIG_SYS_TIMER_COUNTER (MVEBU_TIMER_BASE + 0x14)
132 #define CONFIG_SYS_TIMER_RATE CONFIG_SYS_TCLK
134 #endif /* _KW_CONFIG_H */