arch/arm/mach-imx/image-container.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <errno.h>
   8 #include <log.h>
   9 #include <malloc.h>
  10 #include <asm/io.h>
  11 #include <mmc.h>
  12 #include <spi_flash.h>
  13 #include <nand.h>
  14 #include <asm/mach-imx/image.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/mach-imx/boot_mode.h>
  17
  18 #define MMC_DEV         0
  19 #define QSPI_DEV        1
  20 #define NAND_DEV        2
  21 #define QSPI_NOR_DEV    3
  22 #define ROM_API_DEV     4
  23
  24 int get_container_size(ulong addr, u16 *header_length)
  25 {
  26         struct container_hdr *phdr;
  27         struct boot_img_t *img_entry;
  28         struct signature_block_hdr *sign_hdr;
  29         u8 i = 0;
  30         u32 max_offset = 0, img_end;
  31
  32         phdr = (struct container_hdr *)addr;
  33         if (phdr->tag != 0x87 && phdr->version != 0x0) {
  34                 debug("Wrong container header\n");
  35                 return -EFAULT;
  36         }
  37
  38         max_offset = phdr->length_lsb + (phdr->length_msb << 8);
  39         if (header_length)
  40                 *header_length = max_offset;
  41
  42         img_entry = (struct boot_img_t *)(addr + sizeof(struct container_hdr));
  43         for (i = 0; i < phdr->num_images; i++) {
  44                 img_end = img_entry->offset + img_entry->size;
  45                 if (img_end > max_offset)
  46                         max_offset = img_end;
  47
  48                 debug("img[%u], end = 0x%x\n", i, img_end);
  49
  50                 img_entry++;
  51         }
  52
  53         if (phdr->sig_blk_offset != 0) {
  54                 sign_hdr = (struct signature_block_hdr *)(addr + phdr->sig_blk_offset);
  55                 u16 len = sign_hdr->length_lsb + (sign_hdr->length_msb << 8);
  56
  57                 if (phdr->sig_blk_offset + len > max_offset)
  58                         max_offset = phdr->sig_blk_offset + len;
  59
  60                 debug("sigblk, end = 0x%x\n", phdr->sig_blk_offset + len);
  61         }
  62
  63         return max_offset;
  64 }
  65
  66 static int get_dev_container_size(void *dev, int dev_type, unsigned long offset, u16 *header_length)
  67 {
  68         u8 *buf = malloc(CONTAINER_HDR_ALIGNMENT);
  69         int ret = 0;
  70
  71         if (!buf) {
  72                 printf("Malloc buffer failed\n");
  73                 return -ENOMEM;
  74         }
  75
  76 #ifdef CONFIG_SPL_MMC
  77         if (dev_type == MMC_DEV) {
  78                 unsigned long count = 0;
  79                 struct mmc *mmc = (struct mmc *)dev;
  80
  81                 count = blk_dread(mmc_get_blk_desc(mmc),
  82                                   offset / mmc->read_bl_len,
  83                                   CONTAINER_HDR_ALIGNMENT / mmc->read_bl_len,
  84                                   buf);
  85                 if (count == 0) {
  86                         printf("Read container image from MMC/SD failed\n");
  87                         return -EIO;
  88                 }
  89         }
  90 #endif
  91
  92 #ifdef CONFIG_SPL_SPI_LOAD
  93         if (dev_type == QSPI_DEV) {
  94                 struct spi_flash *flash = (struct spi_flash *)dev;
  95
  96                 ret = spi_flash_read(flash, offset,
  97                                      CONTAINER_HDR_ALIGNMENT, buf);
  98                 if (ret != 0) {
  99                         printf("Read container image from QSPI failed\n");
 100                         return -EIO;
 101                 }
 102         }
 103 #endif
 104
 105 #ifdef CONFIG_SPL_NAND_SUPPORT
 106         if (dev_type == NAND_DEV) {
 107                 ret = nand_spl_load_image(offset, CONTAINER_HDR_ALIGNMENT,
 108                                           buf);
 109                 if (ret != 0) {
 110                         printf("Read container image from NAND failed\n");
 111                         return -EIO;
 112                 }
 113         }
 114 #endif
 115
 116 #ifdef CONFIG_SPL_NOR_SUPPORT
 117         if (dev_type == QSPI_NOR_DEV)
 118                 memcpy(buf, (const void *)offset, CONTAINER_HDR_ALIGNMENT);
 119 #endif
 120
 121 #ifdef CONFIG_SPL_BOOTROM_SUPPORT
 122         if (dev_type == ROM_API_DEV) {
 123                 ret = spl_romapi_raw_seekable_read(offset, CONTAINER_HDR_ALIGNMENT, buf);
 124                 if (!ret) {
 125                         printf("Read container image from ROM API failed\n");
 126                         return -EIO;
 127                 }
 128         }
 129 #endif
 130
 131         ret = get_container_size((ulong)buf, header_length);
 132
 133         free(buf);
 134
 135         return ret;
 136 }
 137
 138 static unsigned long get_boot_device_offset(void *dev, int dev_type)
 139 {
 140         unsigned long offset = 0;
 141
 142         if (dev_type == MMC_DEV) {
 143                 struct mmc *mmc = (struct mmc *)dev;
 144
 145                 if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) {
 146                         offset = CONTAINER_HDR_MMCSD_OFFSET;
 147                 } else {
 148                         u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config);
 149
 150                         if (part == 1 || part == 2) {
 151                                 if (is_imx8qxp() && is_soc_rev(CHIP_REV_B))
 152                                         offset = CONTAINER_HDR_MMCSD_OFFSET;
 153                                 else
 154                                         offset = CONTAINER_HDR_EMMC_OFFSET;
 155                         } else {
 156                                 offset = CONTAINER_HDR_MMCSD_OFFSET;
 157                         }
 158                 }
 159         } else if (dev_type == QSPI_DEV) {
 160                 offset = CONTAINER_HDR_QSPI_OFFSET;
 161         } else if (dev_type == NAND_DEV) {
 162                 offset = CONTAINER_HDR_NAND_OFFSET;
 163         } else if (dev_type == QSPI_NOR_DEV) {
 164                 offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000;
 165         } else if (dev_type == ROM_API_DEV) {
 166                 offset = (unsigned long)dev;
 167         }
 168
 169         return offset;
 170 }
 171
 172 static int get_imageset_end(void *dev, int dev_type)
 173 {
 174         unsigned long offset1 = 0, offset2 = 0;
 175         int value_container[2];
 176         u16 hdr_length;
 177
 178         offset1 = get_boot_device_offset(dev, dev_type);
 179         offset2 = CONTAINER_HDR_ALIGNMENT + offset1;
 180
 181         value_container[0] = get_dev_container_size(dev, dev_type, offset1, &hdr_length);
 182         if (value_container[0] < 0) {
 183                 printf("Parse seco container failed %d\n", value_container[0]);
 184                 return value_container[0];
 185         }
 186
 187         debug("seco container size 0x%x\n", value_container[0]);
 188
 189         value_container[1] = get_dev_container_size(dev, dev_type, offset2, &hdr_length);
 190         if (value_container[1] < 0) {
 191                 debug("Parse scu container failed %d, only seco container\n",
 192                       value_container[1]);
 193                 /* return seco container total size */
 194                 return value_container[0] + offset1;
 195         }
 196
 197         debug("scu container size 0x%x\n", value_container[1]);
 198
 199         return value_container[1] + offset2;
 200 }
 201
 202 #ifdef CONFIG_SPL_SPI_LOAD
 203 unsigned long spl_spi_get_uboot_offs(struct spi_flash *flash)
 204 {
 205         int end;
 206
 207         end = get_imageset_end(flash, QSPI_DEV);
 208         end = ROUND(end, SZ_1K);
 209
 210         printf("Load image from QSPI 0x%x\n", end);
 211
 212         return end;
 213 }
 214 #endif
 215
 216 #ifdef CONFIG_SPL_MMC
 217 unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc,
 218                                            unsigned long raw_sect)
 219 {
 220         int end;
 221
 222         end = get_imageset_end(mmc, MMC_DEV);
 223         end = ROUND(end, SZ_1K);
 224
 225         printf("Load image from MMC/SD 0x%x\n", end);
 226
 227         return end / mmc->read_bl_len;
 228 }
 229 #endif
 230
 231 #ifdef CONFIG_SPL_NAND_SUPPORT
 232 uint32_t spl_nand_get_uboot_raw_page(void)
 233 {
 234         int end;
 235
 236         end = get_imageset_end((void *)NULL, NAND_DEV);
 237         end = ROUND(end, SZ_16K);
 238
 239         printf("Load image from NAND 0x%x\n", end);
 240
 241         return end;
 242 }
 243 #endif
 244
 245 #ifdef CONFIG_SPL_NOR_SUPPORT
 246 unsigned long spl_nor_get_uboot_base(void)
 247 {
 248         int end;
 249
 250         /* Calculate the image set end,
 251          * if it is less than CONFIG_SYS_UBOOT_BASE(0x8281000),
 252          * we use CONFIG_SYS_UBOOT_BASE
 253          * Otherwise, use the calculated address
 254          */
 255         end = get_imageset_end((void *)NULL, QSPI_NOR_DEV);
 256         if (end <= CONFIG_SYS_UBOOT_BASE)
 257                 end = CONFIG_SYS_UBOOT_BASE;
 258         else
 259                 end = ROUND(end, SZ_1K);
 260
 261         printf("Load image from NOR 0x%x\n", end);
 262
 263         return end;
 264 }
 265 #endif
 266
 267 #ifdef CONFIG_SPL_BOOTROM_SUPPORT
 268 u32 __weak spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev)
 269 {
 270         return image_offset;
 271 }
 272
 273 ulong spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev)
 274 {
 275         ulong end;
 276
 277         image_offset = spl_arch_boot_image_offset(image_offset, rom_bt_dev);
 278
 279         end = get_imageset_end((void *)(ulong)image_offset, ROM_API_DEV);
 280         end = ROUND(end, SZ_1K);
 281
 282         printf("Load image from 0x%lx by ROM_API\n", end);
 283
 284         return end;
 285 }
 286 #endif