arch/arm/mach-exynos/exynos4_setup.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Machine Specific Values for EXYNOS4012 based board
   4  *
   5  * Copyright (C) 2011 Samsung Electronics
   6  */
   7
   8 #ifndef _ORIGEN_SETUP_H
   9 #define _ORIGEN_SETUP_H
  10
  11 #include <config.h>
  12 #include <asm/arch/cpu.h>
  13
  14 /* Bus Configuration Register Address */
  15 #define ASYNC_CONFIG            0x10010350
  16
  17 /* CLK_SRC_CPU */
  18 #define MUX_HPM_SEL_MOUTAPLL            0x0
  19 #define MUX_HPM_SEL_SCLKMPLL            0x1
  20 #define MUX_CORE_SEL_MOUTAPLL           0x0
  21 #define MUX_CORE_SEL_SCLKMPLL           0x1
  22 #define MUX_MPLL_SEL_FILPLL             0x0
  23 #define MUX_MPLL_SEL_MOUTMPLLFOUT       0x1
  24 #define MUX_APLL_SEL_FILPLL             0x0
  25 #define MUX_APLL_SEL_MOUTMPLLFOUT       0x1
  26 #define CLK_SRC_CPU_VAL                 ((MUX_HPM_SEL_MOUTAPLL << 20) \
  27                                         | (MUX_CORE_SEL_MOUTAPLL << 16) \
  28                                         | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
  29                                         | (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
  30
  31 /* CLK_DIV_CPU0 */
  32 #define APLL_RATIO              0x0
  33 #define PCLK_DBG_RATIO          0x1
  34 #define ATB_RATIO               0x3
  35 #define PERIPH_RATIO            0x3
  36 #define COREM1_RATIO            0x7
  37 #define COREM0_RATIO            0x3
  38 #define CORE_RATIO              0x0
  39 #define CLK_DIV_CPU0_VAL        ((APLL_RATIO << 24) \
  40                                 | (PCLK_DBG_RATIO << 20) \
  41                                 | (ATB_RATIO << 16) \
  42                                 | (PERIPH_RATIO << 12) \
  43                                 | (COREM1_RATIO << 8) \
  44                                 | (COREM0_RATIO << 4) \
  45                                 | (CORE_RATIO << 0))
  46
  47 /* CLK_DIV_CPU1 */
  48 #define HPM_RATIO               0x0
  49 #define COPY_RATIO              0x3
  50 #define CLK_DIV_CPU1_VAL        ((HPM_RATIO << 4) | (COPY_RATIO))
  51
  52 /* CLK_SRC_DMC */
  53 #define MUX_PWI_SEL_XXTI                0x0
  54 #define MUX_PWI_SEL_XUSBXTI             0x1
  55 #define MUX_PWI_SEL_SCLK_HDMI24M        0x2
  56 #define MUX_PWI_SEL_SCLK_USBPHY0        0x3
  57 #define MUX_PWI_SEL_SCLK_USBPHY1        0x4
  58 #define MUX_PWI_SEL_SCLK_HDMIPHY        0x5
  59 #define MUX_PWI_SEL_SCLKMPLL            0x6
  60 #define MUX_PWI_SEL_SCLKEPLL            0x7
  61 #define MUX_PWI_SEL_SCLKVPLL            0x8
  62 #define MUX_DPHY_SEL_SCLKMPLL           0x0
  63 #define MUX_DPHY_SEL_SCLKAPLL           0x1
  64 #define MUX_DMC_BUS_SEL_SCLKMPLL        0x0
  65 #define MUX_DMC_BUS_SEL_SCLKAPLL        0x1
  66 #define CLK_SRC_DMC_VAL                 ((MUX_PWI_SEL_XUSBXTI << 16) \
  67                                         | (MUX_DPHY_SEL_SCLKMPLL << 8) \
  68                                         | (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
  69
  70 /* CLK_DIV_DMC0 */
  71 #define CORE_TIMERS_RATIO       0x1
  72 #define COPY2_RATIO             0x3
  73 #define DMCP_RATIO              0x1
  74 #define DMCD_RATIO              0x1
  75 #define DMC_RATIO               0x1
  76 #define DPHY_RATIO              0x1
  77 #define ACP_PCLK_RATIO          0x1
  78 #define ACP_RATIO               0x3
  79 #define CLK_DIV_DMC0_VAL        ((CORE_TIMERS_RATIO << 28) \
  80                                 | (COPY2_RATIO << 24) \
  81                                 | (DMCP_RATIO << 20) \
  82                                 | (DMCD_RATIO << 16) \
  83                                 | (DMC_RATIO << 12) \
  84                                 | (DPHY_RATIO << 8) \
  85                                 | (ACP_PCLK_RATIO << 4) \
  86                                 | (ACP_RATIO << 0))
  87
  88 /* CLK_DIV_DMC1 */
  89 #define DPM_RATIO               0x1
  90 #define DVSEM_RATIO             0x1
  91 #define PWI_RATIO               0x1
  92 #define CLK_DIV_DMC1_VAL        ((DPM_RATIO << 24) \
  93                                 | (DVSEM_RATIO << 16) \
  94                                 | (PWI_RATIO << 8))
  95
  96 /* CLK_SRC_TOP0 */
  97 #define MUX_ONENAND_SEL_ACLK_133        0x0
  98 #define MUX_ONENAND_SEL_ACLK_160        0x1
  99 #define MUX_ACLK_133_SEL_SCLKMPLL       0x0
 100 #define MUX_ACLK_133_SEL_SCLKAPLL       0x1
 101 #define MUX_ACLK_160_SEL_SCLKMPLL       0x0
 102 #define MUX_ACLK_160_SEL_SCLKAPLL       0x1
 103 #define MUX_ACLK_100_SEL_SCLKMPLL       0x0
 104 #define MUX_ACLK_100_SEL_SCLKAPLL       0x1
 105 #define MUX_ACLK_200_SEL_SCLKMPLL       0x0
 106 #define MUX_ACLK_200_SEL_SCLKAPLL       0x1
 107 #define MUX_VPLL_SEL_FINPLL             0x0
 108 #define MUX_VPLL_SEL_FOUTVPLL           0x1
 109 #define MUX_EPLL_SEL_FINPLL             0x0
 110 #define MUX_EPLL_SEL_FOUTEPLL           0x1
 111 #define MUX_ONENAND_1_SEL_MOUTONENAND   0x0
 112 #define MUX_ONENAND_1_SEL_SCLKVPLL      0x1
 113 #define CLK_SRC_TOP0_VAL                ((MUX_ONENAND_SEL_ACLK_133 << 28) \
 114                                         | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
 115                                         | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
 116                                         | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
 117                                         | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
 118                                         | (MUX_VPLL_SEL_FINPLL << 8) \
 119                                         | (MUX_EPLL_SEL_FINPLL << 4)\
 120                                         | (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
 121
 122 /* CLK_SRC_TOP1 */
 123 #define VPLLSRC_SEL_FINPLL      0x0
 124 #define VPLLSRC_SEL_SCLKHDMI24M 0x1
 125 #define CLK_SRC_TOP1_VAL        (VPLLSRC_SEL_FINPLL)
 126
 127 /* CLK_DIV_TOP */
 128 #define ONENAND_RATIO           0x0
 129 #define ACLK_133_RATIO          0x5
 130 #define ACLK_160_RATIO          0x4
 131 #define ACLK_100_RATIO          0x7
 132 #define ACLK_200_RATIO          0x3
 133 #define CLK_DIV_TOP_VAL         ((ONENAND_RATIO << 16)  \
 134                                 | (ACLK_133_RATIO << 12)\
 135                                 | (ACLK_160_RATIO << 8) \
 136                                 | (ACLK_100_RATIO << 4) \
 137                                 | (ACLK_200_RATIO << 0))
 138
 139 /* CLK_SRC_LEFTBUS */
 140 #define MUX_GDL_SEL_SCLKMPLL    0x0
 141 #define MUX_GDL_SEL_SCLKAPLL    0x1
 142 #define CLK_SRC_LEFTBUS_VAL     (MUX_GDL_SEL_SCLKMPLL)
 143
 144 /* CLK_DIV_LEFTBUS */
 145 #define GPL_RATIO               0x1
 146 #define GDL_RATIO               0x3
 147 #define CLK_DIV_LEFTBUS_VAL     ((GPL_RATIO << 4) | (GDL_RATIO))
 148
 149 /* CLK_SRC_RIGHTBUS */
 150 #define MUX_GDR_SEL_SCLKMPLL    0x0
 151 #define MUX_GDR_SEL_SCLKAPLL    0x1
 152 #define CLK_SRC_RIGHTBUS_VAL    (MUX_GDR_SEL_SCLKMPLL)
 153
 154 /* CLK_DIV_RIGHTBUS */
 155 #define GPR_RATIO               0x1
 156 #define GDR_RATIO               0x3
 157 #define CLK_DIV_RIGHTBUS_VAL    ((GPR_RATIO << 4) | (GDR_RATIO))
 158
 159 /* CLK_SRS_FSYS: 6 = SCLKMPLL */
 160 #define SATA_SEL_SCLKMPLL       0
 161 #define SATA_SEL_SCLKAPLL       1
 162
 163 #define MMC_SEL_XXTI            0
 164 #define MMC_SEL_XUSBXTI         1
 165 #define MMC_SEL_SCLK_HDMI24M    2
 166 #define MMC_SEL_SCLK_USBPHY0    3
 167 #define MMC_SEL_SCLK_USBPHY1    4
 168 #define MMC_SEL_SCLK_HDMIPHY    5
 169 #define MMC_SEL_SCLKMPLL        6
 170 #define MMC_SEL_SCLKEPLL        7
 171 #define MMC_SEL_SCLKVPLL        8
 172
 173 #define MMCC0_SEL               MMC_SEL_SCLKMPLL
 174 #define MMCC1_SEL               MMC_SEL_SCLKMPLL
 175 #define MMCC2_SEL               MMC_SEL_SCLKMPLL
 176 #define MMCC3_SEL               MMC_SEL_SCLKMPLL
 177 #define MMCC4_SEL               MMC_SEL_SCLKMPLL
 178 #define CLK_SRC_FSYS_VAL        ((SATA_SEL_SCLKMPLL << 24) \
 179                                 | (MMCC4_SEL << 16) \
 180                                 | (MMCC3_SEL << 12) \
 181                                 | (MMCC2_SEL << 8) \
 182                                 | (MMCC1_SEL << 4) \
 183                                 | (MMCC0_SEL << 0))
 184
 185 /* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
 186 /* CLK_DIV_FSYS1 */
 187 #define MMC0_RATIO              0xF
 188 #define MMC0_PRE_RATIO          0x0
 189 #define MMC1_RATIO              0xF
 190 #define MMC1_PRE_RATIO          0x0
 191 #define CLK_DIV_FSYS1_VAL       ((MMC1_PRE_RATIO << 24) \
 192                                 | (MMC1_RATIO << 16) \
 193                                 | (MMC0_PRE_RATIO << 8) \
 194                                 | (MMC0_RATIO << 0))
 195
 196 /* CLK_DIV_FSYS2 */
 197 #define MMC2_RATIO              0xF
 198 #define MMC2_PRE_RATIO          0x0
 199 #define MMC3_RATIO              0xF
 200 #define MMC3_PRE_RATIO          0x0
 201 #define CLK_DIV_FSYS2_VAL       ((MMC3_PRE_RATIO << 24) \
 202                                 | (MMC3_RATIO << 16) \
 203                                 | (MMC2_PRE_RATIO << 8) \
 204                                 | (MMC2_RATIO << 0))
 205
 206 /* CLK_DIV_FSYS3 */
 207 #define MMC4_RATIO              0xF
 208 #define MMC4_PRE_RATIO          0x0
 209 #define CLK_DIV_FSYS3_VAL       ((MMC4_PRE_RATIO << 8) \
 210                                 | (MMC4_RATIO << 0))
 211
 212 /* CLK_SRC_PERIL0 */
 213 #define UART_SEL_XXTI           0
 214 #define UART_SEL_XUSBXTI        1
 215 #define UART_SEL_SCLK_HDMI24M   2
 216 #define UART_SEL_SCLK_USBPHY0   3
 217 #define UART_SEL_SCLK_USBPHY1   4
 218 #define UART_SEL_SCLK_HDMIPHY   5
 219 #define UART_SEL_SCLKMPLL       6
 220 #define UART_SEL_SCLKEPLL       7
 221 #define UART_SEL_SCLKVPLL       8
 222
 223 #define UART0_SEL               UART_SEL_SCLKMPLL
 224 #define UART1_SEL               UART_SEL_SCLKMPLL
 225 #define UART2_SEL               UART_SEL_SCLKMPLL
 226 #define UART3_SEL               UART_SEL_SCLKMPLL
 227 #define UART4_SEL               UART_SEL_SCLKMPLL
 228 #define CLK_SRC_PERIL0_VAL      ((UART4_SEL << 16) \
 229                                 | (UART3_SEL << 12) \
 230                                 | (UART2_SEL << 8) \
 231                                 | (UART1_SEL << 4) \
 232                                 | (UART0_SEL << 0))
 233
 234 /* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
 235 /* CLK_DIV_PERIL0 */
 236 #define UART0_RATIO             7
 237 #define UART1_RATIO             7
 238 #define UART2_RATIO             7
 239 #define UART3_RATIO             7
 240 #define UART4_RATIO             7
 241 #define CLK_DIV_PERIL0_VAL      ((UART4_RATIO << 16) \
 242                                 | (UART3_RATIO << 12) \
 243                                 | (UART2_RATIO << 8) \
 244                                 | (UART1_RATIO << 4) \
 245                                 | (UART0_RATIO << 0))
 246
 247 /* Clock Source CAM/FIMC */
 248 /* CLK_SRC_CAM */
 249 #define CAM0_SEL_XUSBXTI        1
 250 #define CAM1_SEL_XUSBXTI        1
 251 #define CSIS0_SEL_XUSBXTI       1
 252 #define CSIS1_SEL_XUSBXTI       1
 253
 254 #define FIMC_SEL_SCLKMPLL       6
 255 #define FIMC0_LCLK_SEL          FIMC_SEL_SCLKMPLL
 256 #define FIMC1_LCLK_SEL          FIMC_SEL_SCLKMPLL
 257 #define FIMC2_LCLK_SEL          FIMC_SEL_SCLKMPLL
 258 #define FIMC3_LCLK_SEL          FIMC_SEL_SCLKMPLL
 259
 260 #define CLK_SRC_CAM_VAL         ((CSIS1_SEL_XUSBXTI << 28) \
 261                                 | (CSIS0_SEL_XUSBXTI << 24) \
 262                                 | (CAM1_SEL_XUSBXTI << 20) \
 263                                 | (CAM0_SEL_XUSBXTI << 16) \
 264                                 | (FIMC3_LCLK_SEL << 12) \
 265                                 | (FIMC2_LCLK_SEL << 8) \
 266                                 | (FIMC1_LCLK_SEL << 4) \
 267                                 | (FIMC0_LCLK_SEL << 0))
 268
 269 /* SCLK CAM */
 270 /* CLK_DIV_CAM */
 271 #define FIMC0_LCLK_RATIO        4
 272 #define FIMC1_LCLK_RATIO        4
 273 #define FIMC2_LCLK_RATIO        4
 274 #define FIMC3_LCLK_RATIO        4
 275 #define CLK_DIV_CAM_VAL         ((FIMC3_LCLK_RATIO << 12) \
 276                                 | (FIMC2_LCLK_RATIO << 8) \
 277                                 | (FIMC1_LCLK_RATIO << 4) \
 278                                 | (FIMC0_LCLK_RATIO << 0))
 279
 280 /* SCLK MFC */
 281 /* CLK_SRC_MFC */
 282 #define MFC_SEL_MPLL            0
 283 #define MOUTMFC_0               0
 284 #define MFC_SEL                 MOUTMFC_0
 285 #define MFC_0_SEL               MFC_SEL_MPLL
 286 #define CLK_SRC_MFC_VAL         ((MFC_SEL << 8) | (MFC_0_SEL))
 287
 288
 289 /* CLK_DIV_MFC */
 290 #define MFC_RATIO               3
 291 #define CLK_DIV_MFC_VAL         (MFC_RATIO)
 292
 293 /* SCLK G3D */
 294 /* CLK_SRC_G3D */
 295 #define G3D_SEL_MPLL            0
 296 #define MOUTG3D_0               0
 297 #define G3D_SEL                 MOUTG3D_0
 298 #define G3D_0_SEL               G3D_SEL_MPLL
 299 #define CLK_SRC_G3D_VAL         ((G3D_SEL << 8) | (G3D_0_SEL))
 300
 301 /* CLK_DIV_G3D */
 302 #define G3D_RATIO               1
 303 #define CLK_DIV_G3D_VAL         (G3D_RATIO)
 304
 305 /* SCLK LCD0 */
 306 /* CLK_SRC_LCD0 */
 307 #define FIMD_SEL_SCLKMPLL       6
 308 #define MDNIE0_SEL_XUSBXTI      1
 309 #define MDNIE_PWM0_SEL_XUSBXTI  1
 310 #define MIPI0_SEL_XUSBXTI       1
 311 #define CLK_SRC_LCD0_VAL        ((MIPI0_SEL_XUSBXTI << 12) \
 312                                 | (MDNIE_PWM0_SEL_XUSBXTI << 8) \
 313                                 | (MDNIE0_SEL_XUSBXTI << 4) \
 314                                 | (FIMD_SEL_SCLKMPLL << 0))
 315
 316 /* CLK_DIV_LCD0 */
 317 #define FIMD0_RATIO             4
 318 #define CLK_DIV_LCD0_VAL        (FIMD0_RATIO)
 319
 320 /* Required period to generate a stable clock output */
 321 /* PLL_LOCK_TIME */
 322 #define PLL_LOCKTIME            0x1C20
 323
 324 /* PLL Values */
 325 #define DISABLE                 0
 326 #define ENABLE                  1
 327 #define SET_PLL(mdiv, pdiv, sdiv)       ((ENABLE << 31)\
 328                                         | (mdiv << 16) \
 329                                         | (pdiv << 8) \
 330                                         | (sdiv << 0))
 331
 332 /* APLL_CON0 */
 333 #define APLL_MDIV               0xFA
 334 #define APLL_PDIV               0x6
 335 #define APLL_SDIV               0x1
 336 #define APLL_CON0_VAL           SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
 337
 338 /* APLL_CON1 */
 339 #define APLL_AFC_ENB            0x1
 340 #define APLL_AFC                0xC
 341 #define APLL_CON1_VAL           ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
 342
 343 /* MPLL_CON0 */
 344 #define MPLL_MDIV               0xC8
 345 #define MPLL_PDIV               0x6
 346 #define MPLL_SDIV               0x1
 347 #define MPLL_CON0_VAL           SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
 348
 349 /* MPLL_CON1 */
 350 #define MPLL_AFC_ENB            0x0
 351 #define MPLL_AFC                0x1C
 352 #define MPLL_CON1_VAL           ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
 353
 354 /* EPLL_CON0 */
 355 #define EPLL_MDIV               0x30
 356 #define EPLL_PDIV               0x3
 357 #define EPLL_SDIV               0x2
 358 #define EPLL_CON0_VAL           SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
 359
 360 /* EPLL_CON1 */
 361 #define EPLL_K                  0x0
 362 #define EPLL_CON1_VAL           (EPLL_K >> 0)
 363
 364 /* VPLL_CON0 */
 365 #define VPLL_MDIV               0x35
 366 #define VPLL_PDIV               0x3
 367 #define VPLL_SDIV               0x2
 368 #define VPLL_CON0_VAL           SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
 369
 370 /* VPLL_CON1 */
 371 #define VPLL_SSCG_EN            DISABLE
 372 #define VPLL_SEL_PF_DN_SPREAD   0x0
 373 #define VPLL_MRR                0x11
 374 #define VPLL_MFR                0x0
 375 #define VPLL_K                  0x400
 376 #define VPLL_CON1_VAL           ((VPLL_SSCG_EN << 31)\
 377                                 | (VPLL_SEL_PF_DN_SPREAD << 29) \
 378                                 | (VPLL_MRR << 24) \
 379                                 | (VPLL_MFR << 16) \
 380                                 | (VPLL_K << 0))
 381
 382 /* DMC */
 383 #define DIRECT_CMD_NOP  0x07000000
 384 #define DIRECT_CMD_ZQ   0x0a000000
 385 #define DIRECT_CMD_CHIP1_SHIFT  (1 << 20)
 386 #define MEM_TIMINGS_MSR_COUNT   4
 387 #define CTRL_START      (1 << 0)
 388 #define CTRL_DLL_ON     (1 << 1)
 389 #define AREF_EN         (1 << 5)
 390 #define DRV_TYPE        (1 << 6)
 391
 392 struct mem_timings {
 393         unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
 394         unsigned timingref;
 395         unsigned timingrow;
 396         unsigned timingdata;
 397         unsigned timingpower;
 398         unsigned zqcontrol;
 399         unsigned control0;
 400         unsigned control1;
 401         unsigned control2;
 402         unsigned concontrol;
 403         unsigned prechconfig;
 404         unsigned memcontrol;
 405         unsigned memconfig0;
 406         unsigned memconfig1;
 407         unsigned dll_resync;
 408         unsigned dll_on;
 409 };
 410
 411 /* MIU */
 412 /* MIU Config Register Offsets*/
 413 #define APB_SFR_INTERLEAVE_CONF_OFFSET  0x400
 414 #define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
 415 #define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800
 416 #define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808
 417 #define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET   0x810
 418 #define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET        0x818
 419 #define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET  0x820
 420 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET        0x828
 421 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET  0x830
 422
 423 #ifdef CONFIG_TARGET_ORIGEN
 424 /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
 425 #define APB_SFR_INTERLEAVE_CONF_VAL     0x20001507
 426 #define APB_SFR_ARBRITATION_CONF_VAL    0x00000001
 427 #endif
 428
 429 #define INTERLEAVE_ADDR_MAP_START_ADDR  0x40000000
 430 #define INTERLEAVE_ADDR_MAP_END_ADDR    0xbfffffff
 431 #define INTERLEAVE_ADDR_MAP_EN          0x00000001
 432
 433 #ifdef CONFIG_MIU_1BIT_INTERLEAVED
 434 /* Interleave_bit0: 0xC*/
 435 #define APB_SFR_INTERLEAVE_CONF_VAL     0x0000000c
 436 #endif
 437 #ifdef CONFIG_MIU_2BIT_INTERLEAVED
 438 /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
 439 #define APB_SFR_INTERLEAVE_CONF_VAL     0x2000150c
 440 #endif
 441 #define SLAVE0_SINGLE_ADDR_MAP_START_ADDR       0x40000000
 442 #define SLAVE0_SINGLE_ADDR_MAP_END_ADDR         0x7fffffff
 443 #define SLAVE1_SINGLE_ADDR_MAP_START_ADDR       0x80000000
 444 #define SLAVE1_SINGLE_ADDR_MAP_END_ADDR         0xbfffffff
 445 /* Enable SME0 and SME1*/
 446 #define APB_SFR_SLV_ADDR_MAP_CONF_VAL           0x00000006
 447
 448 #define FORCE_DLL_RESYNC        3
 449 #define DLL_CONTROL_ON          1
 450
 451 #define DIRECT_CMD1     0x00020000
 452 #define DIRECT_CMD2     0x00030000
 453 #define DIRECT_CMD3     0x00010002
 454 #define DIRECT_CMD4     0x00000328
 455
 456 #define CTRL_ZQ_MODE_NOTERM     (0x1 << 0)
 457 #define CTRL_ZQ_START           (0x1 << 1)
 458 #define CTRL_ZQ_DIV             (0 << 4)
 459 #define CTRL_ZQ_MODE_DDS        (0x7 << 8)
 460 #define CTRL_ZQ_MODE_TERM       (0x2 << 11)
 461 #define CTRL_ZQ_FORCE_IMPN      (0x5 << 14)
 462 #define CTRL_ZQ_FORCE_IMPP      (0x6 << 17)
 463 #define CTRL_DCC                (0xE38 << 20)
 464 #define ZQ_CONTROL_VAL          (CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\
 465                                 | CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\
 466                                 | CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\
 467                                 | CTRL_ZQ_FORCE_IMPP | CTRL_DCC)
 468
 469 #define ASYNC                   (0 << 0)
 470 #define CLK_RATIO               (1 << 1)
 471 #define DIV_PIPE                (1 << 3)
 472 #define AWR_ON                  (1 << 4)
 473 #define AREF_DISABLE            (0 << 5)
 474 #define DRV_TYPE_DISABLE        (0 << 6)
 475 #define CHIP0_NOT_EMPTY         (0 << 8)
 476 #define CHIP1_NOT_EMPTY         (0 << 9)
 477 #define DQ_SWAP_DISABLE         (0 << 10)
 478 #define QOS_FAST_DISABLE        (0 << 11)
 479 #define RD_FETCH                (0x3 << 12)
 480 #define TIMEOUT_LEVEL0          (0xFFF << 16)
 481 #define CONCONTROL_VAL          (ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\
 482                                 | AREF_DISABLE | DRV_TYPE_DISABLE\
 483                                 | CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\
 484                                 | DQ_SWAP_DISABLE | QOS_FAST_DISABLE\
 485                                 | RD_FETCH | TIMEOUT_LEVEL0)
 486
 487 #define CLK_STOP_DISABLE        (0 << 1)
 488 #define DPWRDN_DISABLE          (0 << 2)
 489 #define DPWRDN_TYPE             (0 << 3)
 490 #define TP_DISABLE              (0 << 4)
 491 #define DSREF_DIABLE            (0 << 5)
 492 #define ADD_LAT_PALL            (1 << 6)
 493 #define MEM_TYPE_DDR3           (0x6 << 8)
 494 #define MEM_WIDTH_32            (0x2 << 12)
 495 #define NUM_CHIP_2              (1 << 16)
 496 #define BL_8                    (0x3 << 20)
 497 #define MEMCONTROL_VAL          (CLK_STOP_DISABLE | DPWRDN_DISABLE\
 498                                 | DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\
 499                                 | ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
 500                                 | NUM_CHIP_2 | BL_8)
 501
 502
 503 #define CHIP_BANK_8             (0x3 << 0)
 504 #define CHIP_ROW_14             (0x2 << 4)
 505 #define CHIP_COL_10             (0x3 << 8)
 506 #define CHIP_MAP_INTERLEAVED    (1 << 12)
 507 #define CHIP_MASK               (0xe0 << 16)
 508 #ifdef CONFIG_MIU_LINEAR
 509 #define CHIP0_BASE              (0x40 << 24)
 510 #define CHIP1_BASE              (0x60 << 24)
 511 #else
 512 #define CHIP0_BASE              (0x20 << 24)
 513 #define CHIP1_BASE              (0x40 << 24)
 514 #endif
 515 #define MEMCONFIG0_VAL          (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
 516                                 | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
 517 #define MEMCONFIG1_VAL          (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
 518                                 | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)
 519
 520 #define TP_CNT                  (0xff << 24)
 521 #define PRECHCONFIG             TP_CNT
 522
 523 #define CTRL_OFF                (0 << 0)
 524 #define CTRL_DLL_OFF            (0 << 1)
 525 #define CTRL_HALF               (0 << 2)
 526 #define CTRL_DFDQS              (1 << 3)
 527 #define DQS_DELAY               (0 << 4)
 528 #define CTRL_START_POINT        (0x10 << 8)
 529 #define CTRL_INC                (0x10 << 16)
 530 #define CTRL_FORCE              (0x71 << 24)
 531 #define CONTROL0_VAL            (CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\
 532                                 | CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\
 533                                 | CTRL_INC | CTRL_FORCE)
 534
 535 #define CTRL_SHIFTC             (0x6 << 0)
 536 #define CTRL_REF                (8 << 4)
 537 #define CTRL_SHGATE             (1 << 29)
 538 #define TERM_READ_EN            (1 << 30)
 539 #define TERM_WRITE_EN           (1 << 31)
 540 #define CONTROL1_VAL            (CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\
 541                                 | TERM_READ_EN | TERM_WRITE_EN)
 542
 543 #define CONTROL2_VAL            0x00000000
 544
 545 #ifdef CONFIG_TARGET_ORIGEN
 546 #define TIMINGREF_VAL           0x000000BB
 547 #define TIMINGROW_VAL           0x4046654f
 548 #define TIMINGDATA_VAL          0x46400506
 549 #define TIMINGPOWER_VAL         0x52000A3C
 550 #else
 551 #define TIMINGREF_VAL           0x000000BC
 552 #define TIMINGROW_VAL           0x45430506
 553 #define TIMINGDATA_VAL          0x56500506
 554 #define TIMINGPOWER_VAL         0x5444033d
 555 #endif
 556 #endif