arch/arm/mach-exynos/exynos4_setup.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Machine Specific Values for EXYNOS4012 based board
   4  *
   5  * Copyright (C) 2011 Samsung Electronics
   6  */
   7
   8 #ifndef _ORIGEN_SETUP_H
   9 #define _ORIGEN_SETUP_H
  10
  11 #include <config.h>
  12 #include <asm/arch/cpu.h>
  13
  14 #ifdef CONFIG_CLK_800_330_165
  15 #define DRAM_CLK_330
  16 #endif
  17 #ifdef CONFIG_CLK_1000_200_200
  18 #define DRAM_CLK_200
  19 #endif
  20 #ifdef CONFIG_CLK_1000_330_165
  21 #define DRAM_CLK_330
  22 #endif
  23 #ifdef CONFIG_CLK_1000_400_200
  24 #define DRAM_CLK_400
  25 #endif
  26
  27 /* Bus Configuration Register Address */
  28 #define ASYNC_CONFIG            0x10010350
  29
  30 /* CLK_SRC_CPU */
  31 #define MUX_HPM_SEL_MOUTAPLL            0x0
  32 #define MUX_HPM_SEL_SCLKMPLL            0x1
  33 #define MUX_CORE_SEL_MOUTAPLL           0x0
  34 #define MUX_CORE_SEL_SCLKMPLL           0x1
  35 #define MUX_MPLL_SEL_FILPLL             0x0
  36 #define MUX_MPLL_SEL_MOUTMPLLFOUT       0x1
  37 #define MUX_APLL_SEL_FILPLL             0x0
  38 #define MUX_APLL_SEL_MOUTMPLLFOUT       0x1
  39 #define CLK_SRC_CPU_VAL                 ((MUX_HPM_SEL_MOUTAPLL << 20) \
  40                                         | (MUX_CORE_SEL_MOUTAPLL << 16) \
  41                                         | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\
  42                                         | (MUX_APLL_SEL_MOUTMPLLFOUT << 0))
  43
  44 /* CLK_DIV_CPU0 */
  45 #define APLL_RATIO              0x0
  46 #define PCLK_DBG_RATIO          0x1
  47 #define ATB_RATIO               0x3
  48 #define PERIPH_RATIO            0x3
  49 #define COREM1_RATIO            0x7
  50 #define COREM0_RATIO            0x3
  51 #define CORE_RATIO              0x0
  52 #define CLK_DIV_CPU0_VAL        ((APLL_RATIO << 24) \
  53                                 | (PCLK_DBG_RATIO << 20) \
  54                                 | (ATB_RATIO << 16) \
  55                                 | (PERIPH_RATIO << 12) \
  56                                 | (COREM1_RATIO << 8) \
  57                                 | (COREM0_RATIO << 4) \
  58                                 | (CORE_RATIO << 0))
  59
  60 /* CLK_DIV_CPU1 */
  61 #define HPM_RATIO               0x0
  62 #define COPY_RATIO              0x3
  63 #define CLK_DIV_CPU1_VAL        ((HPM_RATIO << 4) | (COPY_RATIO))
  64
  65 /* CLK_SRC_DMC */
  66 #define MUX_PWI_SEL_XXTI                0x0
  67 #define MUX_PWI_SEL_XUSBXTI             0x1
  68 #define MUX_PWI_SEL_SCLK_HDMI24M        0x2
  69 #define MUX_PWI_SEL_SCLK_USBPHY0        0x3
  70 #define MUX_PWI_SEL_SCLK_USBPHY1        0x4
  71 #define MUX_PWI_SEL_SCLK_HDMIPHY        0x5
  72 #define MUX_PWI_SEL_SCLKMPLL            0x6
  73 #define MUX_PWI_SEL_SCLKEPLL            0x7
  74 #define MUX_PWI_SEL_SCLKVPLL            0x8
  75 #define MUX_DPHY_SEL_SCLKMPLL           0x0
  76 #define MUX_DPHY_SEL_SCLKAPLL           0x1
  77 #define MUX_DMC_BUS_SEL_SCLKMPLL        0x0
  78 #define MUX_DMC_BUS_SEL_SCLKAPLL        0x1
  79 #define CLK_SRC_DMC_VAL                 ((MUX_PWI_SEL_XUSBXTI << 16) \
  80                                         | (MUX_DPHY_SEL_SCLKMPLL << 8) \
  81                                         | (MUX_DMC_BUS_SEL_SCLKMPLL << 4))
  82
  83 /* CLK_DIV_DMC0 */
  84 #define CORE_TIMERS_RATIO       0x1
  85 #define COPY2_RATIO             0x3
  86 #define DMCP_RATIO              0x1
  87 #define DMCD_RATIO              0x1
  88 #define DMC_RATIO               0x1
  89 #define DPHY_RATIO              0x1
  90 #define ACP_PCLK_RATIO          0x1
  91 #define ACP_RATIO               0x3
  92 #define CLK_DIV_DMC0_VAL        ((CORE_TIMERS_RATIO << 28) \
  93                                 | (COPY2_RATIO << 24) \
  94                                 | (DMCP_RATIO << 20) \
  95                                 | (DMCD_RATIO << 16) \
  96                                 | (DMC_RATIO << 12) \
  97                                 | (DPHY_RATIO << 8) \
  98                                 | (ACP_PCLK_RATIO << 4) \
  99                                 | (ACP_RATIO << 0))
 100
 101 /* CLK_DIV_DMC1 */
 102 #define DPM_RATIO               0x1
 103 #define DVSEM_RATIO             0x1
 104 #define PWI_RATIO               0x1
 105 #define CLK_DIV_DMC1_VAL        ((DPM_RATIO << 24) \
 106                                 | (DVSEM_RATIO << 16) \
 107                                 | (PWI_RATIO << 8))
 108
 109 /* CLK_SRC_TOP0 */
 110 #define MUX_ONENAND_SEL_ACLK_133        0x0
 111 #define MUX_ONENAND_SEL_ACLK_160        0x1
 112 #define MUX_ACLK_133_SEL_SCLKMPLL       0x0
 113 #define MUX_ACLK_133_SEL_SCLKAPLL       0x1
 114 #define MUX_ACLK_160_SEL_SCLKMPLL       0x0
 115 #define MUX_ACLK_160_SEL_SCLKAPLL       0x1
 116 #define MUX_ACLK_100_SEL_SCLKMPLL       0x0
 117 #define MUX_ACLK_100_SEL_SCLKAPLL       0x1
 118 #define MUX_ACLK_200_SEL_SCLKMPLL       0x0
 119 #define MUX_ACLK_200_SEL_SCLKAPLL       0x1
 120 #define MUX_VPLL_SEL_FINPLL             0x0
 121 #define MUX_VPLL_SEL_FOUTVPLL           0x1
 122 #define MUX_EPLL_SEL_FINPLL             0x0
 123 #define MUX_EPLL_SEL_FOUTEPLL           0x1
 124 #define MUX_ONENAND_1_SEL_MOUTONENAND   0x0
 125 #define MUX_ONENAND_1_SEL_SCLKVPLL      0x1
 126 #define CLK_SRC_TOP0_VAL                ((MUX_ONENAND_SEL_ACLK_133 << 28) \
 127                                         | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \
 128                                         | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \
 129                                         | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \
 130                                         | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \
 131                                         | (MUX_VPLL_SEL_FINPLL << 8) \
 132                                         | (MUX_EPLL_SEL_FINPLL << 4)\
 133                                         | (MUX_ONENAND_1_SEL_MOUTONENAND << 0))
 134
 135 /* CLK_SRC_TOP1 */
 136 #define VPLLSRC_SEL_FINPLL      0x0
 137 #define VPLLSRC_SEL_SCLKHDMI24M 0x1
 138 #define CLK_SRC_TOP1_VAL        (VPLLSRC_SEL_FINPLL)
 139
 140 /* CLK_DIV_TOP */
 141 #define ONENAND_RATIO           0x0
 142 #define ACLK_133_RATIO          0x5
 143 #define ACLK_160_RATIO          0x4
 144 #define ACLK_100_RATIO          0x7
 145 #define ACLK_200_RATIO          0x3
 146 #define CLK_DIV_TOP_VAL         ((ONENAND_RATIO << 16)  \
 147                                 | (ACLK_133_RATIO << 12)\
 148                                 | (ACLK_160_RATIO << 8) \
 149                                 | (ACLK_100_RATIO << 4) \
 150                                 | (ACLK_200_RATIO << 0))
 151
 152 /* CLK_SRC_LEFTBUS */
 153 #define MUX_GDL_SEL_SCLKMPLL    0x0
 154 #define MUX_GDL_SEL_SCLKAPLL    0x1
 155 #define CLK_SRC_LEFTBUS_VAL     (MUX_GDL_SEL_SCLKMPLL)
 156
 157 /* CLK_DIV_LEFTBUS */
 158 #define GPL_RATIO               0x1
 159 #define GDL_RATIO               0x3
 160 #define CLK_DIV_LEFTBUS_VAL     ((GPL_RATIO << 4) | (GDL_RATIO))
 161
 162 /* CLK_SRC_RIGHTBUS */
 163 #define MUX_GDR_SEL_SCLKMPLL    0x0
 164 #define MUX_GDR_SEL_SCLKAPLL    0x1
 165 #define CLK_SRC_RIGHTBUS_VAL    (MUX_GDR_SEL_SCLKMPLL)
 166
 167 /* CLK_DIV_RIGHTBUS */
 168 #define GPR_RATIO               0x1
 169 #define GDR_RATIO               0x3
 170 #define CLK_DIV_RIGHTBUS_VAL    ((GPR_RATIO << 4) | (GDR_RATIO))
 171
 172 /* CLK_SRS_FSYS: 6 = SCLKMPLL */
 173 #define SATA_SEL_SCLKMPLL       0
 174 #define SATA_SEL_SCLKAPLL       1
 175
 176 #define MMC_SEL_XXTI            0
 177 #define MMC_SEL_XUSBXTI         1
 178 #define MMC_SEL_SCLK_HDMI24M    2
 179 #define MMC_SEL_SCLK_USBPHY0    3
 180 #define MMC_SEL_SCLK_USBPHY1    4
 181 #define MMC_SEL_SCLK_HDMIPHY    5
 182 #define MMC_SEL_SCLKMPLL        6
 183 #define MMC_SEL_SCLKEPLL        7
 184 #define MMC_SEL_SCLKVPLL        8
 185
 186 #define MMCC0_SEL               MMC_SEL_SCLKMPLL
 187 #define MMCC1_SEL               MMC_SEL_SCLKMPLL
 188 #define MMCC2_SEL               MMC_SEL_SCLKMPLL
 189 #define MMCC3_SEL               MMC_SEL_SCLKMPLL
 190 #define MMCC4_SEL               MMC_SEL_SCLKMPLL
 191 #define CLK_SRC_FSYS_VAL        ((SATA_SEL_SCLKMPLL << 24) \
 192                                 | (MMCC4_SEL << 16) \
 193                                 | (MMCC3_SEL << 12) \
 194                                 | (MMCC2_SEL << 8) \
 195                                 | (MMCC1_SEL << 4) \
 196                                 | (MMCC0_SEL << 0))
 197
 198 /* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */
 199 /* CLK_DIV_FSYS1 */
 200 #define MMC0_RATIO              0xF
 201 #define MMC0_PRE_RATIO          0x0
 202 #define MMC1_RATIO              0xF
 203 #define MMC1_PRE_RATIO          0x0
 204 #define CLK_DIV_FSYS1_VAL       ((MMC1_PRE_RATIO << 24) \
 205                                 | (MMC1_RATIO << 16) \
 206                                 | (MMC0_PRE_RATIO << 8) \
 207                                 | (MMC0_RATIO << 0))
 208
 209 /* CLK_DIV_FSYS2 */
 210 #define MMC2_RATIO              0xF
 211 #define MMC2_PRE_RATIO          0x0
 212 #define MMC3_RATIO              0xF
 213 #define MMC3_PRE_RATIO          0x0
 214 #define CLK_DIV_FSYS2_VAL       ((MMC3_PRE_RATIO << 24) \
 215                                 | (MMC3_RATIO << 16) \
 216                                 | (MMC2_PRE_RATIO << 8) \
 217                                 | (MMC2_RATIO << 0))
 218
 219 /* CLK_DIV_FSYS3 */
 220 #define MMC4_RATIO              0xF
 221 #define MMC4_PRE_RATIO          0x0
 222 #define CLK_DIV_FSYS3_VAL       ((MMC4_PRE_RATIO << 8) \
 223                                 | (MMC4_RATIO << 0))
 224
 225 /* CLK_SRC_PERIL0 */
 226 #define UART_SEL_XXTI           0
 227 #define UART_SEL_XUSBXTI        1
 228 #define UART_SEL_SCLK_HDMI24M   2
 229 #define UART_SEL_SCLK_USBPHY0   3
 230 #define UART_SEL_SCLK_USBPHY1   4
 231 #define UART_SEL_SCLK_HDMIPHY   5
 232 #define UART_SEL_SCLKMPLL       6
 233 #define UART_SEL_SCLKEPLL       7
 234 #define UART_SEL_SCLKVPLL       8
 235
 236 #define UART0_SEL               UART_SEL_SCLKMPLL
 237 #define UART1_SEL               UART_SEL_SCLKMPLL
 238 #define UART2_SEL               UART_SEL_SCLKMPLL
 239 #define UART3_SEL               UART_SEL_SCLKMPLL
 240 #define UART4_SEL               UART_SEL_SCLKMPLL
 241 #define CLK_SRC_PERIL0_VAL      ((UART4_SEL << 16) \
 242                                 | (UART3_SEL << 12) \
 243                                 | (UART2_SEL << 8) \
 244                                 | (UART1_SEL << 4) \
 245                                 | (UART0_SEL << 0))
 246
 247 /* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */
 248 /* CLK_DIV_PERIL0 */
 249 #define UART0_RATIO             7
 250 #define UART1_RATIO             7
 251 #define UART2_RATIO             7
 252 #define UART3_RATIO             7
 253 #define UART4_RATIO             7
 254 #define CLK_DIV_PERIL0_VAL      ((UART4_RATIO << 16) \
 255                                 | (UART3_RATIO << 12) \
 256                                 | (UART2_RATIO << 8) \
 257                                 | (UART1_RATIO << 4) \
 258                                 | (UART0_RATIO << 0))
 259
 260 /* Clock Source CAM/FIMC */
 261 /* CLK_SRC_CAM */
 262 #define CAM0_SEL_XUSBXTI        1
 263 #define CAM1_SEL_XUSBXTI        1
 264 #define CSIS0_SEL_XUSBXTI       1
 265 #define CSIS1_SEL_XUSBXTI       1
 266
 267 #define FIMC_SEL_SCLKMPLL       6
 268 #define FIMC0_LCLK_SEL          FIMC_SEL_SCLKMPLL
 269 #define FIMC1_LCLK_SEL          FIMC_SEL_SCLKMPLL
 270 #define FIMC2_LCLK_SEL          FIMC_SEL_SCLKMPLL
 271 #define FIMC3_LCLK_SEL          FIMC_SEL_SCLKMPLL
 272
 273 #define CLK_SRC_CAM_VAL         ((CSIS1_SEL_XUSBXTI << 28) \
 274                                 | (CSIS0_SEL_XUSBXTI << 24) \
 275                                 | (CAM1_SEL_XUSBXTI << 20) \
 276                                 | (CAM0_SEL_XUSBXTI << 16) \
 277                                 | (FIMC3_LCLK_SEL << 12) \
 278                                 | (FIMC2_LCLK_SEL << 8) \
 279                                 | (FIMC1_LCLK_SEL << 4) \
 280                                 | (FIMC0_LCLK_SEL << 0))
 281
 282 /* SCLK CAM */
 283 /* CLK_DIV_CAM */
 284 #define FIMC0_LCLK_RATIO        4
 285 #define FIMC1_LCLK_RATIO        4
 286 #define FIMC2_LCLK_RATIO        4
 287 #define FIMC3_LCLK_RATIO        4
 288 #define CLK_DIV_CAM_VAL         ((FIMC3_LCLK_RATIO << 12) \
 289                                 | (FIMC2_LCLK_RATIO << 8) \
 290                                 | (FIMC1_LCLK_RATIO << 4) \
 291                                 | (FIMC0_LCLK_RATIO << 0))
 292
 293 /* SCLK MFC */
 294 /* CLK_SRC_MFC */
 295 #define MFC_SEL_MPLL            0
 296 #define MOUTMFC_0               0
 297 #define MFC_SEL                 MOUTMFC_0
 298 #define MFC_0_SEL               MFC_SEL_MPLL
 299 #define CLK_SRC_MFC_VAL         ((MFC_SEL << 8) | (MFC_0_SEL))
 300
 301
 302 /* CLK_DIV_MFC */
 303 #define MFC_RATIO               3
 304 #define CLK_DIV_MFC_VAL         (MFC_RATIO)
 305
 306 /* SCLK G3D */
 307 /* CLK_SRC_G3D */
 308 #define G3D_SEL_MPLL            0
 309 #define MOUTG3D_0               0
 310 #define G3D_SEL                 MOUTG3D_0
 311 #define G3D_0_SEL               G3D_SEL_MPLL
 312 #define CLK_SRC_G3D_VAL         ((G3D_SEL << 8) | (G3D_0_SEL))
 313
 314 /* CLK_DIV_G3D */
 315 #define G3D_RATIO               1
 316 #define CLK_DIV_G3D_VAL         (G3D_RATIO)
 317
 318 /* SCLK LCD0 */
 319 /* CLK_SRC_LCD0 */
 320 #define FIMD_SEL_SCLKMPLL       6
 321 #define MDNIE0_SEL_XUSBXTI      1
 322 #define MDNIE_PWM0_SEL_XUSBXTI  1
 323 #define MIPI0_SEL_XUSBXTI       1
 324 #define CLK_SRC_LCD0_VAL        ((MIPI0_SEL_XUSBXTI << 12) \
 325                                 | (MDNIE_PWM0_SEL_XUSBXTI << 8) \
 326                                 | (MDNIE0_SEL_XUSBXTI << 4) \
 327                                 | (FIMD_SEL_SCLKMPLL << 0))
 328
 329 /* CLK_DIV_LCD0 */
 330 #define FIMD0_RATIO             4
 331 #define CLK_DIV_LCD0_VAL        (FIMD0_RATIO)
 332
 333 /* Required period to generate a stable clock output */
 334 /* PLL_LOCK_TIME */
 335 #define PLL_LOCKTIME            0x1C20
 336
 337 /* PLL Values */
 338 #define DISABLE                 0
 339 #define ENABLE                  1
 340 #define SET_PLL(mdiv, pdiv, sdiv)       ((ENABLE << 31)\
 341                                         | (mdiv << 16) \
 342                                         | (pdiv << 8) \
 343                                         | (sdiv << 0))
 344
 345 /* APLL_CON0 */
 346 #define APLL_MDIV               0xFA
 347 #define APLL_PDIV               0x6
 348 #define APLL_SDIV               0x1
 349 #define APLL_CON0_VAL           SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV)
 350
 351 /* APLL_CON1 */
 352 #define APLL_AFC_ENB            0x1
 353 #define APLL_AFC                0xC
 354 #define APLL_CON1_VAL           ((APLL_AFC_ENB << 31) | (APLL_AFC << 0))
 355
 356 /* MPLL_CON0 */
 357 #define MPLL_MDIV               0xC8
 358 #define MPLL_PDIV               0x6
 359 #define MPLL_SDIV               0x1
 360 #define MPLL_CON0_VAL           SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
 361
 362 /* MPLL_CON1 */
 363 #define MPLL_AFC_ENB            0x0
 364 #define MPLL_AFC                0x1C
 365 #define MPLL_CON1_VAL           ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0))
 366
 367 /* EPLL_CON0 */
 368 #define EPLL_MDIV               0x30
 369 #define EPLL_PDIV               0x3
 370 #define EPLL_SDIV               0x2
 371 #define EPLL_CON0_VAL           SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
 372
 373 /* EPLL_CON1 */
 374 #define EPLL_K                  0x0
 375 #define EPLL_CON1_VAL           (EPLL_K >> 0)
 376
 377 /* VPLL_CON0 */
 378 #define VPLL_MDIV               0x35
 379 #define VPLL_PDIV               0x3
 380 #define VPLL_SDIV               0x2
 381 #define VPLL_CON0_VAL           SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
 382
 383 /* VPLL_CON1 */
 384 #define VPLL_SSCG_EN            DISABLE
 385 #define VPLL_SEL_PF_DN_SPREAD   0x0
 386 #define VPLL_MRR                0x11
 387 #define VPLL_MFR                0x0
 388 #define VPLL_K                  0x400
 389 #define VPLL_CON1_VAL           ((VPLL_SSCG_EN << 31)\
 390                                 | (VPLL_SEL_PF_DN_SPREAD << 29) \
 391                                 | (VPLL_MRR << 24) \
 392                                 | (VPLL_MFR << 16) \
 393                                 | (VPLL_K << 0))
 394
 395 /* DMC */
 396 #define DIRECT_CMD_NOP  0x07000000
 397 #define DIRECT_CMD_ZQ   0x0a000000
 398 #define DIRECT_CMD_CHIP1_SHIFT  (1 << 20)
 399 #define MEM_TIMINGS_MSR_COUNT   4
 400 #define CTRL_START      (1 << 0)
 401 #define CTRL_DLL_ON     (1 << 1)
 402 #define AREF_EN         (1 << 5)
 403 #define DRV_TYPE        (1 << 6)
 404
 405 struct mem_timings {
 406         unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
 407         unsigned timingref;
 408         unsigned timingrow;
 409         unsigned timingdata;
 410         unsigned timingpower;
 411         unsigned zqcontrol;
 412         unsigned control0;
 413         unsigned control1;
 414         unsigned control2;
 415         unsigned concontrol;
 416         unsigned prechconfig;
 417         unsigned memcontrol;
 418         unsigned memconfig0;
 419         unsigned memconfig1;
 420         unsigned dll_resync;
 421         unsigned dll_on;
 422 };
 423
 424 /* MIU */
 425 /* MIU Config Register Offsets*/
 426 #define APB_SFR_INTERLEAVE_CONF_OFFSET  0x400
 427 #define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
 428 #define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800
 429 #define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808
 430 #define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET   0x810
 431 #define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET        0x818
 432 #define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET  0x820
 433 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET        0x828
 434 #define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET  0x830
 435
 436 #ifdef CONFIG_ORIGEN
 437 /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
 438 #define APB_SFR_INTERLEAVE_CONF_VAL     0x20001507
 439 #define APB_SFR_ARBRITATION_CONF_VAL    0x00000001
 440 #endif
 441
 442 #define INTERLEAVE_ADDR_MAP_START_ADDR  0x40000000
 443 #define INTERLEAVE_ADDR_MAP_END_ADDR    0xbfffffff
 444 #define INTERLEAVE_ADDR_MAP_EN          0x00000001
 445
 446 #ifdef CONFIG_MIU_1BIT_INTERLEAVED
 447 /* Interleave_bit0: 0xC*/
 448 #define APB_SFR_INTERLEAVE_CONF_VAL     0x0000000c
 449 #endif
 450 #ifdef CONFIG_MIU_2BIT_INTERLEAVED
 451 /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
 452 #define APB_SFR_INTERLEAVE_CONF_VAL     0x2000150c
 453 #endif
 454 #define SLAVE0_SINGLE_ADDR_MAP_START_ADDR       0x40000000
 455 #define SLAVE0_SINGLE_ADDR_MAP_END_ADDR         0x7fffffff
 456 #define SLAVE1_SINGLE_ADDR_MAP_START_ADDR       0x80000000
 457 #define SLAVE1_SINGLE_ADDR_MAP_END_ADDR         0xbfffffff
 458 /* Enable SME0 and SME1*/
 459 #define APB_SFR_SLV_ADDR_MAP_CONF_VAL           0x00000006
 460
 461 #define FORCE_DLL_RESYNC        3
 462 #define DLL_CONTROL_ON          1
 463
 464 #define DIRECT_CMD1     0x00020000
 465 #define DIRECT_CMD2     0x00030000
 466 #define DIRECT_CMD3     0x00010002
 467 #define DIRECT_CMD4     0x00000328
 468
 469 #define CTRL_ZQ_MODE_NOTERM     (0x1 << 0)
 470 #define CTRL_ZQ_START           (0x1 << 1)
 471 #define CTRL_ZQ_DIV             (0 << 4)
 472 #define CTRL_ZQ_MODE_DDS        (0x7 << 8)
 473 #define CTRL_ZQ_MODE_TERM       (0x2 << 11)
 474 #define CTRL_ZQ_FORCE_IMPN      (0x5 << 14)
 475 #define CTRL_ZQ_FORCE_IMPP      (0x6 << 17)
 476 #define CTRL_DCC                (0xE38 << 20)
 477 #define ZQ_CONTROL_VAL          (CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\
 478                                 | CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\
 479                                 | CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\
 480                                 | CTRL_ZQ_FORCE_IMPP | CTRL_DCC)
 481
 482 #define ASYNC                   (0 << 0)
 483 #define CLK_RATIO               (1 << 1)
 484 #define DIV_PIPE                (1 << 3)
 485 #define AWR_ON                  (1 << 4)
 486 #define AREF_DISABLE            (0 << 5)
 487 #define DRV_TYPE_DISABLE        (0 << 6)
 488 #define CHIP0_NOT_EMPTY         (0 << 8)
 489 #define CHIP1_NOT_EMPTY         (0 << 9)
 490 #define DQ_SWAP_DISABLE         (0 << 10)
 491 #define QOS_FAST_DISABLE        (0 << 11)
 492 #define RD_FETCH                (0x3 << 12)
 493 #define TIMEOUT_LEVEL0          (0xFFF << 16)
 494 #define CONCONTROL_VAL          (ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\
 495                                 | AREF_DISABLE | DRV_TYPE_DISABLE\
 496                                 | CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\
 497                                 | DQ_SWAP_DISABLE | QOS_FAST_DISABLE\
 498                                 | RD_FETCH | TIMEOUT_LEVEL0)
 499
 500 #define CLK_STOP_DISABLE        (0 << 1)
 501 #define DPWRDN_DISABLE          (0 << 2)
 502 #define DPWRDN_TYPE             (0 << 3)
 503 #define TP_DISABLE              (0 << 4)
 504 #define DSREF_DIABLE            (0 << 5)
 505 #define ADD_LAT_PALL            (1 << 6)
 506 #define MEM_TYPE_DDR3           (0x6 << 8)
 507 #define MEM_WIDTH_32            (0x2 << 12)
 508 #define NUM_CHIP_2              (1 << 16)
 509 #define BL_8                    (0x3 << 20)
 510 #define MEMCONTROL_VAL          (CLK_STOP_DISABLE | DPWRDN_DISABLE\
 511                                 | DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\
 512                                 | ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
 513                                 | NUM_CHIP_2 | BL_8)
 514
 515
 516 #define CHIP_BANK_8             (0x3 << 0)
 517 #define CHIP_ROW_14             (0x2 << 4)
 518 #define CHIP_COL_10             (0x3 << 8)
 519 #define CHIP_MAP_INTERLEAVED    (1 << 12)
 520 #define CHIP_MASK               (0xe0 << 16)
 521 #ifdef CONFIG_MIU_LINEAR
 522 #define CHIP0_BASE              (0x40 << 24)
 523 #define CHIP1_BASE              (0x60 << 24)
 524 #else
 525 #define CHIP0_BASE              (0x20 << 24)
 526 #define CHIP1_BASE              (0x40 << 24)
 527 #endif
 528 #define MEMCONFIG0_VAL          (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
 529                                 | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
 530 #define MEMCONFIG1_VAL          (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\
 531                                 | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)
 532
 533 #define TP_CNT                  (0xff << 24)
 534 #define PRECHCONFIG             TP_CNT
 535
 536 #define CTRL_OFF                (0 << 0)
 537 #define CTRL_DLL_OFF            (0 << 1)
 538 #define CTRL_HALF               (0 << 2)
 539 #define CTRL_DFDQS              (1 << 3)
 540 #define DQS_DELAY               (0 << 4)
 541 #define CTRL_START_POINT        (0x10 << 8)
 542 #define CTRL_INC                (0x10 << 16)
 543 #define CTRL_FORCE              (0x71 << 24)
 544 #define CONTROL0_VAL            (CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\
 545                                 | CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\
 546                                 | CTRL_INC | CTRL_FORCE)
 547
 548 #define CTRL_SHIFTC             (0x6 << 0)
 549 #define CTRL_REF                (8 << 4)
 550 #define CTRL_SHGATE             (1 << 29)
 551 #define TERM_READ_EN            (1 << 30)
 552 #define TERM_WRITE_EN           (1 << 31)
 553 #define CONTROL1_VAL            (CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\
 554                                 | TERM_READ_EN | TERM_WRITE_EN)
 555
 556 #define CONTROL2_VAL            0x00000000
 557
 558 #ifdef CONFIG_ORIGEN
 559 #define TIMINGREF_VAL           0x000000BB
 560 #define TIMINGROW_VAL           0x4046654f
 561 #define TIMINGDATA_VAL          0x46400506
 562 #define TIMINGPOWER_VAL         0x52000A3C
 563 #else
 564 #define TIMINGREF_VAL           0x000000BC
 565 #ifdef DRAM_CLK_330
 566 #define TIMINGROW_VAL           0x3545548d
 567 #define TIMINGDATA_VAL          0x45430506
 568 #define TIMINGPOWER_VAL         0x4439033c
 569 #endif
 570 #ifdef DRAM_CLK_400
 571 #define TIMINGROW_VAL           0x45430506
 572 #define TIMINGDATA_VAL          0x56500506
 573 #define TIMINGPOWER_VAL         0x5444033d
 574 #endif
 575 #endif
 576 #endif