2 * (C) Copyright 2008-2011
3 * Graeme Russ, <graeme.russ@gmail.com>
6 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
9 * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13 * Marius Groeger <mgroeger@sysgo.de>
15 * Copyright 2015 ATS Advanced Telematics Systems GmbH
16 * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
18 * SPDX-License-Identifier: GPL-2.0+
25 * ARMv7M does not support ARM instruction mode. However, the
26 * interworking BLX and BX instructions do encode the ARM/Thumb
27 * field in bit 0. This means that when executing any Branch
28 * and eXchange instruction we must set bit 0 to one to guarantee
29 * that we keep the processor in Thumb instruction mode. From The
30 * ARMv7-M Instruction Set A4.1.1:
31 * "ARMv7-M only supports the Thumb instruction execution state,
32 * therefore the value of address bit [0] must be 1 in interworking
33 * instructions, otherwise a fault occurs."
35 unsigned long do_go_exec(ulong (*entry)(int, char * const []),
36 int argc, char * const argv[])
38 ulong addr = (ulong)entry | 1;
41 return entry(argc, argv);