4 * Copyright (C) 2006-2014 Texas Instruments.
6 * Based on Linux DaVinci NAND driver by TI.
9 #ifndef _DAVINCI_NAND_H_
10 #define _DAVINCI_NAND_H_
12 #include <asm/arch/hardware.h>
14 #define NAND_READ_START 0x00
15 #define NAND_READ_END 0x30
16 #define NAND_STATUS 0x70
21 #ifdef CONFIG_SYS_NAND_MASK_CLE
23 #define MASK_CLE CONFIG_SYS_NAND_MASK_CLE
25 #ifdef CONFIG_SYS_NAND_MASK_ALE
27 #define MASK_ALE CONFIG_SYS_NAND_MASK_ALE
30 struct davinci_emif_regs {
50 uint32_t ddrphyid_rev;
65 uint32_t nand4biteccload;
66 uint32_t nand4bitecc[4];
73 #define davinci_emif_regs \
74 ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE)
76 #define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2))
77 #define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4)
78 #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4)
79 #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2)))
80 #define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12)
81 #define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13)
82 #define DAVINCI_NANDFCR_CS2NAND (1 << 0)
84 /* Chip Select setup */
85 #define DAVINCI_ABCR_STROBE_SELECT (1 << 31)
86 #define DAVINCI_ABCR_EXT_WAIT (1 << 30)
87 #define DAVINCI_ABCR_WSETUP(n) (n << 26)
88 #define DAVINCI_ABCR_WSTROBE(n) (n << 20)
89 #define DAVINCI_ABCR_WHOLD(n) (n << 17)
90 #define DAVINCI_ABCR_RSETUP(n) (n << 13)
91 #define DAVINCI_ABCR_RSTROBE(n) (n << 7)
92 #define DAVINCI_ABCR_RHOLD(n) (n << 4)
93 #define DAVINCI_ABCR_TA(n) (n << 2)
94 #define DAVINCI_ABCR_ASIZE_16BIT 1
95 #define DAVINCI_ABCR_ASIZE_8BIT 0