arch/arm/include/asm/arch-sunxi/cpucfg.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Sunxi A31 CPUCFG register definition.
   4  *
   5  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com
   6  */
   7
   8 #ifndef _SUNXI_CPUCFG_H
   9 #define _SUNXI_CPUCFG_H
  10
  11 #include <linux/compiler.h>
  12 #include <linux/types.h>
  13
  14 #ifndef __ASSEMBLY__
  15
  16 struct __packed sunxi_cpucfg_cpu {
  17         u32 rst;                /* base + 0x0 */
  18         u32 ctrl;               /* base + 0x4 */
  19         u32 status;             /* base + 0x8 */
  20         u8 res[0x34];           /* base + 0xc */
  21 };
  22
  23 struct __packed sunxi_cpucfg_reg {
  24         u8 res0[0x40];          /* 0x000 */
  25         struct sunxi_cpucfg_cpu cpu[4];         /* 0x040 */
  26         u8 res1[0x44];          /* 0x140 */
  27         u32 gen_ctrl;           /* 0x184 */
  28         u32 l2_status;          /* 0x188 */
  29         u8 res2[0x4];           /* 0x18c */
  30         u32 event_in;           /* 0x190 */
  31         u8 res3[0xc];           /* 0x194 */
  32         u32 super_standy_flag;  /* 0x1a0 */
  33         u32 priv0;              /* 0x1a4 */
  34         u32 priv1;              /* 0x1a8 */
  35         u8 res4[0x4];           /* 0x1ac */
  36         u32 cpu1_pwr_clamp;     /* 0x1b0 sun7i only */
  37         u32 cpu1_pwroff;        /* 0x1b4 sun7i only */
  38         u8 res5[0x2c];          /* 0x1b8 */
  39         u32 dbg_ctrl1;          /* 0x1e4 */
  40         u8 res6[0x18];          /* 0x1e8 */
  41         u32 idle_cnt0_low;      /* 0x200 */
  42         u32 idle_cnt0_high;     /* 0x204 */
  43         u32 idle_cnt0_ctrl;     /* 0x208 */
  44         u8 res8[0x4];           /* 0x20c */
  45         u32 idle_cnt1_low;      /* 0x210 */
  46         u32 idle_cnt1_high;     /* 0x214 */
  47         u32 idle_cnt1_ctrl;     /* 0x218 */
  48         u8 res9[0x4];           /* 0x21c */
  49         u32 idle_cnt2_low;      /* 0x220 */
  50         u32 idle_cnt2_high;     /* 0x224 */
  51         u32 idle_cnt2_ctrl;     /* 0x228 */
  52         u8 res10[0x4];          /* 0x22c */
  53         u32 idle_cnt3_low;      /* 0x230 */
  54         u32 idle_cnt3_high;     /* 0x234 */
  55         u32 idle_cnt3_ctrl;     /* 0x238 */
  56         u8 res11[0x4];          /* 0x23c */
  57         u32 idle_cnt4_low;      /* 0x240 */
  58         u32 idle_cnt4_high;     /* 0x244 */
  59         u32 idle_cnt4_ctrl;     /* 0x248 */
  60         u8 res12[0x34];         /* 0x24c */
  61         u32 cnt64_ctrl;         /* 0x280 */
  62         u32 cnt64_low;          /* 0x284 */
  63         u32 cnt64_high;         /* 0x288 */
  64 };
  65
  66 #endif /* __ASSEMBLY__ */
  67 #endif /* _SUNXI_CPUCFG_H */