1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2015, Freescale Semiconductor, Inc.
6 #ifndef __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
7 #define __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__
9 #define MC_RGM_DES (MC_RGM_BASE_ADDR)
10 #define MC_RGM_FES (MC_RGM_BASE_ADDR + 0x300)
11 #define MC_RGM_FERD (MC_RGM_BASE_ADDR + 0x310)
12 #define MC_RGM_FBRE (MC_RGM_BASE_ADDR + 0x330)
13 #define MC_RGM_FESS (MC_RGM_BASE_ADDR + 0x340)
14 #define MC_RGM_DDR_HE (MC_RGM_BASE_ADDR + 0x350)
15 #define MC_RGM_DDR_HS (MC_RGM_BASE_ADDR + 0x354)
16 #define MC_RGM_FRHE (MC_RGM_BASE_ADDR + 0x358)
17 #define MC_RGM_FREC (MC_RGM_BASE_ADDR + 0x600)
18 #define MC_RGM_FRET (MC_RGM_BASE_ADDR + 0x607)
19 #define MC_RGM_DRET (MC_RGM_BASE_ADDR + 0x60B)
21 /* function reset sources mask */
24 #define F_FCCU_SOFT 0x40
25 #define F_FCCU_HARD 0x20
26 #define F_SOFT_FUNC 0x8
30 #endif /* __ARCH_ARM_MACH_S32V234_MCRGM_REGS_H__ */