arch/arm/include/asm/arch-rockchip/cru_rv1108.h

   1 /*
   2  * (C) Copyright 2016 Rockchip Electronics Co., Ltd
   3  * Author: Andy Yan <andy.yan@rock-chips.com>
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #ifndef _ASM_ARCH_CRU_RV1108_H
   7 #define _ASM_ARCH_CRU_RV1108_H
   8
   9 #include <common.h>
  10
  11 #define OSC_HZ          (24 * 1000 * 1000)
  12
  13 #define APLL_HZ         (600 * 1000000)
  14 #define GPLL_HZ         (594 * 1000000)
  15
  16 struct rv1108_clk_priv {
  17         struct rv1108_cru *cru;
  18         ulong rate;
  19 };
  20
  21 struct rv1108_cru {
  22         struct rv1108_pll {
  23                 unsigned int con0;
  24                 unsigned int con1;
  25                 unsigned int con2;
  26                 unsigned int con3;
  27                 unsigned int con4;
  28                 unsigned int con5;
  29                 unsigned int reserved[2];
  30         } pll[3];
  31         unsigned int clksel_con[46];
  32         unsigned int reserved1[2];
  33         unsigned int clkgate_con[20];
  34         unsigned int reserved2[4];
  35         unsigned int softrst_con[13];
  36         unsigned int reserved3[3];
  37         unsigned int glb_srst_fst_val;
  38         unsigned int glb_srst_snd_val;
  39         unsigned int glb_cnt_th;
  40         unsigned int misc_con;
  41         unsigned int glb_rst_con;
  42         unsigned int glb_rst_st;
  43         unsigned int sdmmc_con[2];
  44         unsigned int sdio_con[2];
  45         unsigned int emmc_con[2];
  46 };
  47 check_member(rv1108_cru, emmc_con[1], 0x01ec);
  48
  49 struct pll_div {
  50         u32 refdiv;
  51         u32 fbdiv;
  52         u32 postdiv1;
  53         u32 postdiv2;
  54         u32 frac;
  55 };
  56
  57 enum {
  58         /* PLL CON0 */
  59         FBDIV_MASK              = 0xfff,
  60         FBDIV_SHIFT             = 0,
  61
  62         /* PLL CON1 */
  63         POSTDIV2_SHIFT          = 12,
  64         POSTDIV2_MASK           = 7 << POSTDIV2_SHIFT,
  65         POSTDIV1_SHIFT          = 8,
  66         POSTDIV1_MASK           = 7 << POSTDIV1_SHIFT,
  67         REFDIV_MASK             = 0x3f,
  68         REFDIV_SHIFT            = 0,
  69
  70         /* PLL CON2 */
  71         LOCK_STA_SHIFT          = 31,
  72         LOCK_STA_MASK           = 1 << LOCK_STA_SHIFT,
  73         FRACDIV_MASK            = 0xffffff,
  74         FRACDIV_SHIFT           = 0,
  75
  76         /* PLL CON3 */
  77         WORK_MODE_SHIFT         = 8,
  78         WORK_MODE_MASK          = 1 << WORK_MODE_SHIFT,
  79         WORK_MODE_SLOW          = 0,
  80         WORK_MODE_NORMAL        = 1,
  81         DSMPD_SHIFT             = 3,
  82         DSMPD_MASK              = 1 << DSMPD_SHIFT,
  83
  84         /* CLKSEL0_CON */
  85         CORE_PLL_SEL_SHIFT      = 8,
  86         CORE_PLL_SEL_MASK       = 3 << CORE_PLL_SEL_SHIFT,
  87         CORE_PLL_SEL_APLL       = 0,
  88         CORE_PLL_SEL_GPLL       = 1,
  89         CORE_PLL_SEL_DPLL       = 2,
  90         CORE_CLK_DIV_SHIFT      = 0,
  91         CORE_CLK_DIV_MASK       = 0x1f << CORE_CLK_DIV_SHIFT,
  92
  93         /* CLKSEL_CON22 */
  94         CLK_SARADC_DIV_CON_SHIFT= 0,
  95         CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
  96         CLK_SARADC_DIV_CON_WIDTH= 10,
  97
  98         /* CLKSEL24_CON */
  99         MAC_PLL_SEL_SHIFT       = 12,
 100         MAC_PLL_SEL_MASK        = 1 << MAC_PLL_SEL_SHIFT,
 101         MAC_PLL_SEL_APLL        = 0,
 102         MAC_PLL_SEL_GPLL        = 1,
 103         RMII_EXTCLK_SEL_SHIFT   = 8,
 104         RMII_EXTCLK_SEL_MASK    = 1 << RMII_EXTCLK_SEL_SHIFT,
 105         MAC_CLK_DIV_MASK        = 0x1f,
 106         MAC_CLK_DIV_SHIFT       = 0,
 107
 108         /* CLKSEL27_CON */
 109         SFC_PLL_SEL_SHIFT       = 7,
 110         SFC_PLL_SEL_MASK        = 1 << SFC_PLL_SEL_SHIFT,
 111         SFC_PLL_SEL_DPLL        = 0,
 112         SFC_PLL_SEL_GPLL        = 1,
 113         SFC_CLK_DIV_SHIFT       = 0,
 114         SFC_CLK_DIV_MASK        = 0x3f << SFC_CLK_DIV_SHIFT,
 115 };
 116 #endif