arch/arm/include/asm/arch-imx8m/imx-regs.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2017 NXP
   4  */
   5
   6 #ifndef __ASM_ARCH_IMX8M_REGS_H__
   7 #define __ASM_ARCH_IMX8M_REGS_H__
   8
   9 #define ARCH_MXC
  10
  11 #include <asm/mach-imx/regs-lcdif.h>
  12
  13 #define ROM_VERSION_A0          IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
  14 #define ROM_VERSION_B0          IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
  15
  16 #define M4_BOOTROM_BASE_ADDR   0x007E0000
  17
  18 #define GPIO1_BASE_ADDR         0X30200000
  19 #define GPIO2_BASE_ADDR         0x30210000
  20 #define GPIO3_BASE_ADDR         0x30220000
  21 #define GPIO4_BASE_ADDR         0x30230000
  22 #define GPIO5_BASE_ADDR         0x30240000
  23 #define WDOG1_BASE_ADDR         0x30280000
  24 #define WDOG2_BASE_ADDR         0x30290000
  25 #define WDOG3_BASE_ADDR         0x302A0000
  26 #define IOMUXC_BASE_ADDR        0x30330000
  27 #define IOMUXC_GPR_BASE_ADDR    0x30340000
  28 #define OCOTP_BASE_ADDR         0x30350000
  29 #define ANATOP_BASE_ADDR        0x30360000
  30 #define SNVS_BASE_ADDR          0x30370000
  31 #define CCM_BASE_ADDR           0x30380000
  32 #define SRC_BASE_ADDR           0x30390000
  33 #define GPC_BASE_ADDR           0x303A0000
  34
  35 #define SYSCNT_RD_BASE_ADDR     0x306A0000
  36 #define SYSCNT_CMP_BASE_ADDR    0x306B0000
  37 #define SYSCNT_CTRL_BASE_ADDR   0x306C0000
  38
  39 #define UART1_BASE_ADDR         0x30860000
  40 #define UART3_BASE_ADDR         0x30880000
  41 #define UART2_BASE_ADDR         0x30890000
  42 #define I2C1_BASE_ADDR          0x30A20000
  43 #define I2C2_BASE_ADDR          0x30A30000
  44 #define I2C3_BASE_ADDR          0x30A40000
  45 #define I2C4_BASE_ADDR          0x30A50000
  46 #define UART4_BASE_ADDR         0x30A60000
  47 #define USDHC1_BASE_ADDR        0x30B40000
  48 #define USDHC2_BASE_ADDR        0x30B50000
  49 #define QSPI0_AMBA_BASE     0x08000000
  50 #ifdef CONFIG_IMX8MM
  51 #define USDHC3_BASE_ADDR        0x30B60000
  52 #endif
  53 #define UART_BASE_ADDR(n)       (                       \
  54         !!sizeof(struct {                               \
  55                 static_assert((n) >= 1 && (n) <= 4);    \
  56                 int pad;                                \
  57                 }) * (                                  \
  58         (n) == 1 ? UART1_BASE_ADDR :                    \
  59         (n) == 2 ? UART2_BASE_ADDR :                    \
  60         (n) == 3 ? UART3_BASE_ADDR :                    \
  61         UART4_BASE_ADDR)                                \
  62         )
  63
  64 #define TZASC_BASE_ADDR         0x32F80000
  65
  66 #define MXS_LCDIF_BASE          IS_ENABLED(CONFIG_IMX8MQ) ? \
  67                                         0x30320000 : 0x32e00000
  68
  69 #define SRC_IPS_BASE_ADDR       0x30390000
  70 #define SRC_DDRC_RCR_ADDR       0x30391000
  71 #define SRC_DDRC2_RCR_ADDR      0x30391004
  72
  73 #define APBH_DMA_ARB_BASE_ADDR  0x33000000
  74 #define APBH_DMA_ARB_END_ADDR   0x33007FFF
  75 #define MXS_APBH_BASE           APBH_DMA_ARB_BASE_ADDR
  76
  77 #define MXS_GPMI_BASE           (APBH_DMA_ARB_BASE_ADDR + 0x02000)
  78 #define MXS_BCH_BASE            (APBH_DMA_ARB_BASE_ADDR + 0x04000)
  79
  80 #define DDRC_DDR_SS_GPR0        0x3d000000
  81 #define DDRC_IPS_BASE_ADDR(X)   (0x3d400000 + ((X) * 0x2000000))
  82 #define DDR_CSD1_BASE_ADDR      0x40000000
  83
  84 #define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
  85 #define FEC_QUIRK_ENET_MAC
  86
  87 #define CAAM_ARB_BASE_ADDR              (0x00100000)
  88 #define CAAM_ARB_END_ADDR               (0x00107FFF)
  89 #define CAAM_IPS_BASE_ADDR              (0x30900000)
  90 #define CFG_SYS_FSL_SEC_OFFSET       (0)
  91 #define CFG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR + \
  92                                          CFG_SYS_FSL_SEC_OFFSET)
  93 #define CFG_SYS_FSL_JR0_OFFSET       (0x1000)
  94 #define CFG_SYS_FSL_JR0_ADDR         (CFG_SYS_FSL_SEC_ADDR + \
  95                                          CFG_SYS_FSL_JR0_OFFSET)
  96 #if !defined(__ASSEMBLY__)
  97 #include <asm/types.h>
  98 #include <linux/bitops.h>
  99 #include <stdbool.h>
 100
 101 #define GPR_TZASC_EN                                    BIT(0)
 102 #define GPR_TZASC_ID_SWAP_BYPASS                BIT(1)
 103 #define GPR_TZASC_EN_LOCK                               BIT(16)
 104 #define GPR_TZASC_ID_SWAP_BYPASS_LOCK   BIT(17)
 105
 106 #define SRC_SCR_M4_ENABLE_OFFSET        3
 107 #define SRC_SCR_M4_ENABLE_MASK          BIT(3)
 108 #define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0
 109 #define SRC_SCR_M4C_NON_SCLR_RST_MASK   BIT(0)
 110 #define SRC_DDR1_ENABLE_MASK            0x8F000000UL
 111 #define SRC_DDR2_ENABLE_MASK            0x8F000000UL
 112 #define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3)
 113 #define SRC_DDR1_RCR_PHY_RESET_MASK     BIT(2)
 114 #define SRC_DDR1_RCR_CORE_RESET_N_MASK  BIT(1)
 115 #define SRC_DDR1_RCR_PRESET_N_MASK      BIT(0)
 116
 117 #define SNVS_LPSR                       0x4c
 118 #define SNVS_LPLVDR                     0x64
 119 #define SNVS_LPPGDR_INIT                0x41736166
 120
 121 struct iomuxc_gpr_base_regs {
 122         u32 gpr[47];
 123 };
 124
 125 struct ocotp_regs {
 126         u32     ctrl;
 127         u32     ctrl_set;
 128         u32     ctrl_clr;
 129         u32     ctrl_tog;
 130         u32     timing;
 131         u32     rsvd0[3];
 132         u32     data;
 133         u32     rsvd1[3];
 134         u32     read_ctrl;
 135         u32     rsvd2[3];
 136         u32     read_fuse_data;
 137         u32     rsvd3[3];
 138         u32     sw_sticky;
 139         u32     rsvd4[3];
 140         u32     scs;
 141         u32     scs_set;
 142         u32     scs_clr;
 143         u32     scs_tog;
 144         u32     crc_addr;
 145         u32     rsvd5[3];
 146         u32     crc_value;
 147         u32     rsvd6[3];
 148         u32     version;
 149         u32     rsvd7[0xdb];
 150
 151         /* fuse banks */
 152         struct fuse_bank {
 153                 u32     fuse_regs[0x10];
 154         } bank[0];
 155 };
 156
 157 #ifdef CONFIG_IMX8MP
 158 struct fuse_bank0_regs {
 159         u32 lock;
 160         u32 rsvd0[7];
 161         u32 uid_low;
 162         u32 rsvd1[3];
 163         u32 uid_high;
 164         u32 rsvd2[3];
 165 };
 166 #else
 167 struct fuse_bank0_regs {
 168         u32 lock;
 169         u32 rsvd0[3];
 170         u32 uid_low;
 171         u32 rsvd1[3];
 172         u32 uid_high;
 173         u32 rsvd2[7];
 174 };
 175 #endif
 176
 177 struct fuse_bank1_regs {
 178         u32 tester3;
 179         u32 rsvd0[3];
 180         u32 tester4;
 181         u32 rsvd1[3];
 182         u32 tester5;
 183         u32 rsvd2[3];
 184         u32 cfg0;
 185         u32 rsvd3[3];
 186 };
 187
 188 struct fuse_bank3_regs {
 189         u32 mem_trim0;
 190         u32 rsvd0[3];
 191         u32 mem_trim1;
 192         u32 rsvd1[3];
 193         u32 mem_trim2;
 194         u32 rsvd2[3];
 195         u32 ana0;
 196         u32 rsvd3[3];
 197 };
 198
 199 struct fuse_bank9_regs {
 200         u32 mac_addr0;
 201         u32 rsvd0[3];
 202         u32 mac_addr1;
 203         u32 rsvd1[11];
 204 };
 205
 206 struct fuse_bank38_regs {
 207         u32 ana_trim1; /* trim0 is at 0xD70, bank 37*/
 208         u32 rsvd0[3];
 209         u32 ana_trim2;
 210         u32 rsvd1[3];
 211         u32 ana_trim3;
 212         u32 rsvd2[3];
 213         u32 ana_trim4;
 214         u32 rsvd3[3];
 215 };
 216
 217 struct fuse_bank39_regs {
 218         u32 ana_trim5;
 219         u32 rsvd[15];
 220 };
 221
 222 #ifdef CONFIG_IMX8MQ
 223 struct anamix_pll {
 224         u32 audio_pll1_cfg0;
 225         u32 audio_pll1_cfg1;
 226         u32 audio_pll2_cfg0;
 227         u32 audio_pll2_cfg1;
 228         u32 video_pll_cfg0;
 229         u32 video_pll_cfg1;
 230         u32 gpu_pll_cfg0;
 231         u32 gpu_pll_cfg1;
 232         u32 vpu_pll_cfg0;
 233         u32 vpu_pll_cfg1;
 234         u32 arm_pll_cfg0;
 235         u32 arm_pll_cfg1;
 236         u32 sys_pll1_cfg0;
 237         u32 sys_pll1_cfg1;
 238         u32 sys_pll1_cfg2;
 239         u32 sys_pll2_cfg0;
 240         u32 sys_pll2_cfg1;
 241         u32 sys_pll2_cfg2;
 242         u32 sys_pll3_cfg0;
 243         u32 sys_pll3_cfg1;
 244         u32 sys_pll3_cfg2;
 245         u32 video_pll2_cfg0;
 246         u32 video_pll2_cfg1;
 247         u32 video_pll2_cfg2;
 248         u32 dram_pll_cfg0;
 249         u32 dram_pll_cfg1;
 250         u32 dram_pll_cfg2;
 251         u32 digprog;
 252         u32 osc_misc_cfg;
 253         u32 pllout_monitor_cfg;
 254         u32 frac_pllout_div_cfg;
 255         u32 sscg_pllout_div_cfg;
 256 };
 257 #else
 258 struct anamix_pll {
 259         u32 audio_pll1_gnrl_ctl;
 260         u32 audio_pll1_fdiv_ctl0;
 261         u32 audio_pll1_fdiv_ctl1;
 262         u32 audio_pll1_sscg_ctl;
 263         u32 audio_pll1_mnit_ctl;
 264         u32 audio_pll2_gnrl_ctl;
 265         u32 audio_pll2_fdiv_ctl0;
 266         u32 audio_pll2_fdiv_ctl1;
 267         u32 audio_pll2_sscg_ctl;
 268         u32 audio_pll2_mnit_ctl;
 269         u32 video_pll1_gnrl_ctl;
 270         u32 video_pll1_fdiv_ctl0;
 271         u32 video_pll1_fdiv_ctl1;
 272         u32 video_pll1_sscg_ctl;
 273         u32 video_pll1_mnit_ctl;
 274         u32 reserved[5];
 275         u32 dram_pll_gnrl_ctl;
 276         u32 dram_pll_fdiv_ctl0;
 277         u32 dram_pll_fdiv_ctl1;
 278         u32 dram_pll_sscg_ctl;
 279         u32 dram_pll_mnit_ctl;
 280         u32 gpu_pll_gnrl_ctl;
 281         u32 gpu_pll_div_ctl;
 282         u32 gpu_pll_locked_ctl1;
 283         u32 gpu_pll_mnit_ctl;
 284         u32 vpu_pll_gnrl_ctl;
 285         u32 vpu_pll_div_ctl;
 286         u32 vpu_pll_locked_ctl1;
 287         u32 vpu_pll_mnit_ctl;
 288         u32 arm_pll_gnrl_ctl;
 289         u32 arm_pll_div_ctl;
 290         u32 arm_pll_locked_ctl1;
 291         u32 arm_pll_mnit_ctl;
 292         u32 sys_pll1_gnrl_ctl;
 293         u32 sys_pll1_div_ctl;
 294         u32 sys_pll1_locked_ctl1;
 295         u32 reserved2[24];
 296         u32 sys_pll1_mnit_ctl;
 297         u32 sys_pll2_gnrl_ctl;
 298         u32 sys_pll2_div_ctl;
 299         u32 sys_pll2_locked_ctl1;
 300         u32 sys_pll2_mnit_ctl;
 301         u32 sys_pll3_gnrl_ctl;
 302         u32 sys_pll3_div_ctl;
 303         u32 sys_pll3_locked_ctl1;
 304         u32 sys_pll3_mnit_ctl;
 305         u32 anamix_misc_ctl;
 306         u32 anamix_clk_mnit_ctl;
 307         u32 reserved3[437];
 308         u32 digprog;
 309 };
 310 #endif
 311
 312 /* System Reset Controller (SRC) */
 313 struct src {
 314         u32 scr;
 315         u32 a53rcr;
 316         u32 a53rcr1;
 317         u32 m4rcr;
 318         u32 reserved1[4];
 319         u32 usbophy1_rcr;
 320         u32 usbophy2_rcr;
 321         u32 mipiphy_rcr;
 322         u32 pciephy_rcr;
 323         u32 hdmi_rcr;
 324         u32 disp_rcr;
 325         u32 reserved2[2];
 326         u32 gpu_rcr;
 327         u32 vpu_rcr;
 328         u32 pcie2_rcr;
 329         u32 mipiphy1_rcr;
 330         u32 mipiphy2_rcr;
 331         u32 reserved3;
 332         u32 sbmr1;
 333         u32 srsr;
 334         u32 reserved4[2];
 335         u32 sisr;
 336         u32 simr;
 337         u32 sbmr2;
 338         u32 gpr1;
 339         u32 gpr2;
 340         u32 gpr3;
 341         u32 gpr4;
 342         u32 gpr5;
 343         u32 gpr6;
 344         u32 gpr7;
 345         u32 gpr8;
 346         u32 gpr9;
 347         u32 gpr10;
 348         u32 reserved5[985];
 349         u32 ddr1_rcr;
 350         u32 ddr2_rcr;
 351 };
 352
 353 #define PWMCR_PRESCALER(x)      (((x - 1) & 0xFFF) << 4)
 354 #define PWMCR_DOZEEN            (1 << 24)
 355 #define PWMCR_WAITEN            (1 << 23)
 356 #define PWMCR_DBGEN             (1 << 22)
 357 #define PWMCR_CLKSRC_IPG_HIGH   (2 << 16)
 358 #define PWMCR_CLKSRC_IPG        (1 << 16)
 359 #define PWMCR_EN                (1 << 0)
 360
 361 struct pwm_regs {
 362         u32     cr;
 363         u32     sr;
 364         u32     ir;
 365         u32     sar;
 366         u32     pr;
 367         u32     cnr;
 368 };
 369
 370 #define WDOG_WDT_MASK   BIT(3)
 371 #define WDOG_WDZST_MASK BIT(0)
 372 struct wdog_regs {
 373         u16     wcr;    /* Control */
 374         u16     wsr;    /* Service */
 375         u16     wrsr;   /* Reset Status */
 376         u16     wicr;   /* Interrupt Control */
 377         u16     wmcr;   /* Miscellaneous Control */
 378 };
 379
 380 struct bootrom_sw_info {
 381         u8 reserved_1;
 382         u8 boot_dev_instance;
 383         u8 boot_dev_type;
 384         u8 reserved_2;
 385         u32 core_freq;
 386         u32 axi_freq;
 387         u32 ddr_freq;
 388         u32 tick_freq;
 389         u32 reserved_3[3];
 390 };
 391
 392 #define ROM_SW_INFO_ADDR_B0     (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\
 393                                  0x000009e8)
 394 #define ROM_SW_INFO_ADDR_A0     0x000009e8
 395
 396 #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
 397                 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
 398                 (struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
 399
 400 struct gpc_reg {
 401         u32 lpcr_bsc;
 402         u32 lpcr_ad;
 403         u32 lpcr_cpu1;
 404         u32 lpcr_cpu2;
 405         u32 lpcr_cpu3;
 406         u32 slpcr;
 407         u32 mst_cpu_mapping;
 408         u32 mmdc_cpu_mapping;
 409         u32 mlpcr;
 410         u32 pgc_ack_sel;
 411         u32 pgc_ack_sel_m4;
 412         u32 gpc_misc;
 413         u32 imr1_core0;
 414         u32 imr2_core0;
 415         u32 imr3_core0;
 416         u32 imr4_core0;
 417         u32 imr1_core1;
 418         u32 imr2_core1;
 419         u32 imr3_core1;
 420         u32 imr4_core1;
 421         u32 imr1_cpu1;
 422         u32 imr2_cpu1;
 423         u32 imr3_cpu1;
 424         u32 imr4_cpu1;
 425         u32 imr1_cpu3;
 426         u32 imr2_cpu3;
 427         u32 imr3_cpu3;
 428         u32 imr4_cpu3;
 429         u32 isr1_cpu0;
 430         u32 isr2_cpu0;
 431         u32 isr3_cpu0;
 432         u32 isr4_cpu0;
 433         u32 isr1_cpu1;
 434         u32 isr2_cpu1;
 435         u32 isr3_cpu1;
 436         u32 isr4_cpu1;
 437         u32 isr1_cpu2;
 438         u32 isr2_cpu2;
 439         u32 isr3_cpu2;
 440         u32 isr4_cpu2;
 441         u32 isr1_cpu3;
 442         u32 isr2_cpu3;
 443         u32 isr3_cpu3;
 444         u32 isr4_cpu3;
 445         u32 slt0_cfg;
 446         u32 slt1_cfg;
 447         u32 slt2_cfg;
 448         u32 slt3_cfg;
 449         u32 slt4_cfg;
 450         u32 slt5_cfg;
 451         u32 slt6_cfg;
 452         u32 slt7_cfg;
 453         u32 slt8_cfg;
 454         u32 slt9_cfg;
 455         u32 slt10_cfg;
 456         u32 slt11_cfg;
 457         u32 slt12_cfg;
 458         u32 slt13_cfg;
 459         u32 slt14_cfg;
 460         u32 pgc_cpu_0_1_mapping;
 461         u32 cpu_pgc_up_trg;
 462         u32 mix_pgc_up_trg;
 463         u32 pu_pgc_up_trg;
 464         u32 cpu_pgc_dn_trg;
 465         u32 mix_pgc_dn_trg;
 466         u32 pu_pgc_dn_trg;
 467         u32 lpcr_bsc2;
 468         u32 pgc_cpu_2_3_mapping;
 469         u32 lps_cpu0;
 470         u32 lps_cpu1;
 471         u32 lps_cpu2;
 472         u32 lps_cpu3;
 473         u32 gpc_gpr;
 474         u32 gtor;
 475         u32 debug_addr1;
 476         u32 debug_addr2;
 477         u32 cpu_pgc_up_status1;
 478         u32 mix_pgc_up_status0;
 479         u32 mix_pgc_up_status1;
 480         u32 mix_pgc_up_status2;
 481         u32 m4_mix_pgc_up_status0;
 482         u32 m4_mix_pgc_up_status1;
 483         u32 m4_mix_pgc_up_status2;
 484         u32 pu_pgc_up_status0;
 485         u32 pu_pgc_up_status1;
 486         u32 pu_pgc_up_status2;
 487         u32 m4_pu_pgc_up_status0;
 488         u32 m4_pu_pgc_up_status1;
 489         u32 m4_pu_pgc_up_status2;
 490         u32 a53_lp_io_0;
 491         u32 a53_lp_io_1;
 492         u32 a53_lp_io_2;
 493         u32 cpu_pgc_dn_status1;
 494         u32 mix_pgc_dn_status0;
 495         u32 mix_pgc_dn_status1;
 496         u32 mix_pgc_dn_status2;
 497         u32 m4_mix_pgc_dn_status0;
 498         u32 m4_mix_pgc_dn_status1;
 499         u32 m4_mix_pgc_dn_status2;
 500         u32 pu_pgc_dn_status0;
 501         u32 pu_pgc_dn_status1;
 502         u32 pu_pgc_dn_status2;
 503         u32 m4_pu_pgc_dn_status0;
 504         u32 m4_pu_pgc_dn_status1;
 505         u32 m4_pu_pgc_dn_status2;
 506         u32 res[3];
 507         u32 mix_pdn_flg;
 508         u32 pu_pdn_flg;
 509         u32 m4_mix_pdn_flg;
 510         u32 m4_pu_pdn_flg;
 511         u32 imr1_core2;
 512         u32 imr2_core2;
 513         u32 imr3_core2;
 514         u32 imr4_core2;
 515         u32 imr1_core3;
 516         u32 imr2_core3;
 517         u32 imr3_core3;
 518         u32 imr4_core3;
 519         u32 pgc_ack_sel_pu;
 520         u32 pgc_ack_sel_m4_pu;
 521         u32 slt15_cfg;
 522         u32 slt16_cfg;
 523         u32 slt17_cfg;
 524         u32 slt18_cfg;
 525         u32 slt19_cfg;
 526         u32 gpc_pu_pwrhsk;
 527         u32 slt0_cfg_pu;
 528         u32 slt1_cfg_pu;
 529         u32 slt2_cfg_pu;
 530         u32 slt3_cfg_pu;
 531         u32 slt4_cfg_pu;
 532         u32 slt5_cfg_pu;
 533         u32 slt6_cfg_pu;
 534         u32 slt7_cfg_pu;
 535         u32 slt8_cfg_pu;
 536         u32 slt9_cfg_pu;
 537         u32 slt10_cfg_pu;
 538         u32 slt11_cfg_pu;
 539         u32 slt12_cfg_pu;
 540         u32 slt13_cfg_pu;
 541         u32 slt14_cfg_pu;
 542         u32 slt15_cfg_pu;
 543         u32 slt16_cfg_pu;
 544         u32 slt17_cfg_pu;
 545         u32 slt18_cfg_pu;
 546         u32 slt19_cfg_pu;
 547 };
 548
 549 struct pgc_reg {
 550         u32 pgcr;
 551         u32 pgpupscr;
 552         u32 pgpdnscr;
 553         u32 pgsr;
 554         u32 pgauxsw;
 555         u32 pgdr;
 556 };
 557 #endif
 558 #endif