1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2016-2018, 2020 NXP
4 * Copyright 2015, Freescale Semiconductor
7 #ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
8 #define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
10 #include <linux/kconfig.h>
11 #include <fsl_ddrc_version.h>
14 #include <linux/bitops.h>
17 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
20 * Reserve secure memory
21 * To be aligned with MMU block size
23 #define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
24 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
26 #ifdef CONFIG_ARCH_LS2080A
27 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
28 #define SRDS_MAX_LANES 8
29 #define CONFIG_SYS_PAGE_SIZE 0x10000
30 #ifndef L1_CACHE_BYTES
31 #define L1_CACHE_SHIFT 6
32 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
35 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
36 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
37 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
40 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
41 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
43 #define CONFIG_SYS_FSL_CCSR_GUR_LE
44 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
45 #define CONFIG_SYS_FSL_ESDHC_LE
46 #define CONFIG_SYS_FSL_IFC_LE
47 #define CONFIG_SYS_FSL_PEX_LUT_LE
49 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
51 /* Generic Interrupt Controller Definitions */
52 #define GICD_BASE 0x06000000
53 #define GICR_BASE 0x06100000
56 #define SMMU_BASE 0x05000000 /* GR0 Base */
59 #define CONFIG_SYS_FSL_SFP_VER_3_4
60 #define CONFIG_SYS_FSL_SFP_LE
61 #define CONFIG_SYS_FSL_SRK_LE
63 /* Security Monitor */
64 #define CONFIG_SYS_FSL_SEC_MON_LE
67 #define CONFIG_ESBC_HDR_LS
70 #define CONFIG_SYS_FSL_CCSR_GUR_LE
72 /* Cache Coherent Interconnect */
73 #define CCI_MN_BASE 0x04000000
74 #define CCI_MN_RNF_NODEID_LIST 0x180
75 #define CCI_MN_DVM_DOMAIN_CTL 0x200
76 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
78 #define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
79 #define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
80 #define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
81 #define CCN_HN_F_SAM_NODEID_MASK 0x7f
82 #define CCN_HN_F_SAM_NODEID_DDR0 0x4
83 #define CCN_HN_F_SAM_NODEID_DDR1 0xe
85 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
86 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
87 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
88 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
89 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
90 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
92 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
93 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
94 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
96 #define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
98 /* TZ Protection Controller Definitions */
99 #define TZPC_BASE 0x02200000
100 #define TZPCR0SIZE_BASE (TZPC_BASE)
101 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
102 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
103 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
104 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
105 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
106 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
107 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
108 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
109 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
111 #define DCSR_CGACRE5 0x700070914ULL
112 #define EPU_EPCMPR5 0x700060914ULL
113 #define EPU_EPCCR5 0x700060814ULL
114 #define EPU_EPSMCR5 0x700060228ULL
115 #define EPU_EPECR5 0x700060314ULL
116 #define EPU_EPCTR5 0x700060a14ULL
117 #define EPU_EPGCR 0x700060000ULL
119 #define CONFIG_SYS_FSL_ERRATUM_A008751
121 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
123 #elif defined(CONFIG_ARCH_LS1088A)
124 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
125 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
127 #define CONFIG_SYS_PAGE_SIZE 0x10000
129 #define SRDS_MAX_LANES 4
130 #define SRDS_BITS_PER_LANE 4
132 /* TZ Protection Controller Definitions */
133 #define TZPC_BASE 0x02200000
134 #define TZPCR0SIZE_BASE (TZPC_BASE)
135 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
136 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
137 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
138 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
139 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
140 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
141 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
142 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
143 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
145 /* Generic Interrupt Controller Definitions */
146 #define GICD_BASE 0x06000000
147 #define GICR_BASE 0x06100000
149 /* SMMU Defintions */
150 #define SMMU_BASE 0x05000000 /* GR0 Base */
153 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
154 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
156 #define CONFIG_SYS_FSL_CCSR_GUR_LE
157 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
158 #define CONFIG_SYS_FSL_ESDHC_LE
159 #define CONFIG_SYS_FSL_IFC_LE
160 #define CONFIG_SYS_FSL_PEX_LUT_LE
162 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
165 #define CONFIG_SYS_FSL_SFP_VER_3_4
166 #define CONFIG_SYS_FSL_SFP_LE
167 #define CONFIG_SYS_FSL_SRK_LE
169 /* Security Monitor */
170 #define CONFIG_SYS_FSL_SEC_MON_LE
173 #define CONFIG_ESBC_HDR_LS
176 #define CONFIG_SYS_FSL_CCSR_GUR_LE
177 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
178 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
179 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
180 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
182 /* LX2160A/LX2162A Soc Support */
183 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
184 #define TZPC_BASE 0x02200000
185 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
186 #if !CONFIG_IS_ENABLED(DM_I2C)
187 #define CONFIG_SYS_I2C_EARLY_INIT
189 #define SRDS_MAX_LANES 8
190 #ifndef L1_CACHE_BYTES
191 #define L1_CACHE_SHIFT 6
192 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
194 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
195 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
196 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
198 #define CONFIG_SYS_PAGE_SIZE 0x10000
200 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
201 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
202 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
205 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
206 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
208 #define CONFIG_SYS_FSL_CCSR_GUR_LE
209 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
210 #define CONFIG_SYS_FSL_ESDHC_LE
211 #define CONFIG_SYS_FSL_PEX_LUT_LE
213 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
215 /* Generic Interrupt Controller Definitions */
216 #define GICD_BASE 0x06000000
217 #define GICR_BASE 0x06200000
219 /* SMMU Definitions */
220 #define SMMU_BASE 0x05000000 /* GR0 Base */
223 #define CONFIG_SYS_FSL_SFP_VER_3_4
224 #define CONFIG_SYS_FSL_SFP_LE
225 #define CONFIG_SYS_FSL_SRK_LE
227 /* Security Monitor */
228 #define CONFIG_SYS_FSL_SEC_MON_LE
231 #define CONFIG_ESBC_HDR_LS
234 #define CONFIG_SYS_FSL_CCSR_GUR_LE
236 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
238 #elif defined(CONFIG_ARCH_LS1028A)
239 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
240 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
242 #define CONFIG_FSL_TZPC_BP147
243 #define CONFIG_FSL_TZASC_400
245 /* TZ Protection Controller Definitions */
246 #define TZPC_BASE 0x02200000
247 #define TZPCR0SIZE_BASE (TZPC_BASE)
248 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
249 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
250 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
251 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
252 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
253 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
254 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
255 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
256 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
258 #define SRDS_MAX_LANES 4
259 #define SRDS_BITS_PER_LANE 4
261 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
262 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
263 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
265 /* Generic Interrupt Controller Definitions */
266 #define GICD_BASE 0x06000000
267 #define GICR_BASE 0x06040000
269 /* SMMU Definitions */
270 #define SMMU_BASE 0x05000000 /* GR0 Base */
273 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
274 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
276 #define CONFIG_SYS_FSL_CCSR_GUR_LE
277 #define CONFIG_SYS_FSL_CCSR_SCFG_LE
278 #define CONFIG_SYS_FSL_ESDHC_LE
279 #define CONFIG_SYS_FSL_PEX_LUT_LE
281 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
284 #define CONFIG_SYS_FSL_SFP_VER_3_4
285 #define CONFIG_SYS_FSL_SFP_LE
286 #define CONFIG_SYS_FSL_SRK_LE
289 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
291 /* Security Monitor */
292 #define CONFIG_SYS_FSL_SEC_MON_LE
295 #define CONFIG_ESBC_HDR_LS
298 #define CONFIG_SYS_FSL_CCSR_GUR_LE
300 #elif defined(CONFIG_FSL_LSCH2)
301 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
302 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
303 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
305 #define DCSR_DCFG_SBEESR2 0x20140534
306 #define DCSR_DCFG_MBEESR2 0x20140544
308 #define CONFIG_SYS_FSL_CCSR_SCFG_BE
309 #define CONFIG_SYS_FSL_ESDHC_BE
310 #define CONFIG_SYS_FSL_WDOG_BE
311 #define CONFIG_SYS_FSL_DSPI_BE
312 #define CONFIG_SYS_FSL_CCSR_GUR_BE
313 #define CONFIG_SYS_FSL_PEX_LUT_BE
316 #ifdef CONFIG_ARCH_LS1043A
317 #define CONFIG_SYS_FMAN_V3
318 #define CONFIG_SYS_FSL_QMAN_V3
319 #define CONFIG_SYS_NUM_FMAN 1
320 #define CONFIG_SYS_NUM_FM1_DTSEC 7
321 #define CONFIG_SYS_NUM_FM1_10GEC 1
322 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
323 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
325 #define QE_MURAM_SIZE 0x6000UL
326 #define MAX_QE_RISC 1
327 #define QE_NUM_OF_SNUM 28
329 #define CONFIG_SYS_FSL_IFC_BE
330 #define CONFIG_SYS_FSL_SFP_VER_3_2
331 #define CONFIG_SYS_FSL_SEC_MON_BE
332 #define CONFIG_SYS_FSL_SFP_BE
333 #define CONFIG_SYS_FSL_SRK_LE
334 #define CONFIG_KEY_REVOCATION
336 /* SMMU Defintions */
337 #define SMMU_BASE 0x09000000
339 /* Generic Interrupt Controller Definitions */
340 #define GICD_BASE 0x01401000
341 #define GICC_BASE 0x01402000
342 #define GICH_BASE 0x01404000
343 #define GICV_BASE 0x01406000
344 #define GICD_SIZE 0x1000
345 #define GICC_SIZE 0x2000
346 #define GICH_SIZE 0x2000
347 #define GICV_SIZE 0x2000
348 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
349 #define GICD_BASE_64K 0x01410000
350 #define GICC_BASE_64K 0x01420000
351 #define GICH_BASE_64K 0x01440000
352 #define GICV_BASE_64K 0x01460000
353 #define GICD_SIZE_64K 0x10000
354 #define GICC_SIZE_64K 0x20000
355 #define GICH_SIZE_64K 0x20000
356 #define GICV_SIZE_64K 0x20000
359 #define DCFG_CCSR_SVR 0x1ee00a4
362 #define GIC_ADDR_BIT 31
363 #define SCFG_GIC400_ALIGN 0x1570188
365 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
367 #elif defined(CONFIG_ARCH_LS1012A)
368 #define GICD_BASE 0x01401000
369 #define GICC_BASE 0x01402000
370 #define CONFIG_SYS_FSL_SFP_VER_3_2
371 #define CONFIG_SYS_FSL_SEC_MON_BE
372 #define CONFIG_SYS_FSL_SFP_BE
373 #define CONFIG_SYS_FSL_SRK_LE
374 #define CONFIG_KEY_REVOCATION
375 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
376 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
377 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
379 #elif defined(CONFIG_ARCH_LS1046A)
380 #define CONFIG_SYS_FMAN_V3
381 #define CONFIG_SYS_FSL_QMAN_V3
382 #define CONFIG_SYS_NUM_FMAN 1
383 #define CONFIG_SYS_NUM_FM1_DTSEC 8
384 #define CONFIG_SYS_NUM_FM1_10GEC 2
385 #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
386 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
388 #define CONFIG_SYS_FSL_IFC_BE
389 #define CONFIG_SYS_FSL_SFP_VER_3_2
390 #define CONFIG_SYS_FSL_SEC_MON_BE
391 #define CONFIG_SYS_FSL_SFP_BE
392 #define CONFIG_SYS_FSL_SRK_LE
393 #define CONFIG_KEY_REVOCATION
395 /* SMMU Defintions */
396 #define SMMU_BASE 0x09000000
398 /* Generic Interrupt Controller Definitions */
399 #define GICD_BASE 0x01410000
400 #define GICC_BASE 0x01420000
402 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
404 #error SoC not defined
408 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */