arch/arm/dts/zynq-syzygy-hub.dts

   1 /*
   2  * SYZYGY Hub DTS
   3  *
   4  *  Copyright (C) 2011 - 2015 Xilinx
   5  *  Copyright (C) 2017 Opal Kelly Inc.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 /dts-v1/;
  10 /include/ "zynq-7000.dtsi"
  11
  12 / {
  13         model = "SYZYGY Hub";
  14         compatible = "opalkelly,syzygy-hub", "xlnx,zynq-7000";
  15
  16         aliases {
  17                 ethernet0 = &gem0;
  18                 serial0 = &uart0;
  19                 mmc0 = &sdhci0;
  20         };
  21
  22         memory@0 {
  23                 device_type = "memory";
  24                 reg = <0x0 0x40000000>;
  25         };
  26
  27         chosen {
  28                 bootargs = "";
  29                 stdout-path = "serial0:115200n8";
  30         };
  31
  32         usb_phy0: phy0 {
  33                 #phy-cells = <0>;
  34                 compatible = "usb-nop-xceiv";
  35                 reset-gpios = <&gpio0 47 1>;
  36         };
  37 };
  38
  39 &clkc {
  40         ps-clk-frequency = <50000000>;
  41 };
  42
  43 &gem0 {
  44         status = "okay";
  45         phy-mode = "rgmii-id";
  46         phy-handle = <&ethernet_phy>;
  47
  48         ethernet_phy: ethernet-phy@0 {
  49                 reg = <0>;
  50                 device_type = "ethernet-phy";
  51         };
  52 };
  53
  54 &i2c1 {
  55         status = "okay";
  56 };
  57
  58 &sdhci0 {
  59         u-boot,dm-pre-reloc;
  60         status = "okay";
  61 };
  62
  63 &uart0 {
  64         u-boot,dm-pre-reloc;
  65         status = "okay";
  66 };
  67
  68 &usb0 {
  69         status = "okay";
  70         dr_mode = "otg";
  71         usb-phy = <&usb_phy0>;
  72 };