arch/arm/dts/rk3288.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/interrupt-controller/irq.h>
   5 #include <dt-bindings/interrupt-controller/arm-gic.h>
   6 #include <dt-bindings/pinctrl/rockchip.h>
   7 #include <dt-bindings/clock/rk3288-cru.h>
   8 #include <dt-bindings/power-domain/rk3288.h>
   9 #include <dt-bindings/thermal/thermal.h>
  10 #include <dt-bindings/video/rk3288.h>
  11 #include "skeleton.dtsi"
  12
  13 / {
  14         compatible = "rockchip,rk3288";
  15
  16         interrupt-parent = <&gic>;
  17         aliases {
  18                 gpio0 = &gpio0;
  19                 gpio1 = &gpio1;
  20                 gpio2 = &gpio2;
  21                 gpio3 = &gpio3;
  22                 gpio4 = &gpio4;
  23                 gpio5 = &gpio5;
  24                 gpio6 = &gpio6;
  25                 gpio7 = &gpio7;
  26                 gpio8 = &gpio8;
  27                 i2c0 = &i2c0;
  28                 i2c1 = &i2c1;
  29                 i2c2 = &i2c2;
  30                 i2c3 = &i2c3;
  31                 i2c4 = &i2c4;
  32                 i2c5 = &i2c5;
  33                 mmc0 = &emmc;
  34                 mmc1 = &sdmmc;
  35                 mmc2 = &sdio0;
  36                 mmc3 = &sdio1;
  37                 mshc0 = &emmc;
  38                 mshc1 = &sdmmc;
  39                 mshc2 = &sdio0;
  40                 mshc3 = &sdio1;
  41                 serial0 = &uart0;
  42                 serial1 = &uart1;
  43                 serial2 = &uart2;
  44                 serial3 = &uart3;
  45                 serial4 = &uart4;
  46                 spi0 = &spi0;
  47                 spi1 = &spi1;
  48                 spi2 = &spi2;
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54                 enable-method = "rockchip,rk3066-smp";
  55                 rockchip,pmu = <&pmu>;
  56
  57                 cpu0: cpu@500 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a12";
  60                         reg = <0x500>;
  61                         operating-points = <
  62                                 /* KHz    uV */
  63                                 1800000 1400000
  64                                 1704000 1350000
  65                                 1608000 1300000
  66                                 1512000 1250000
  67                                 1416000 1200000
  68                                 1200000 1100000
  69                                 1008000 1050000
  70                                  816000 1000000
  71                                  696000  950000
  72                                  600000  900000
  73                                  408000  900000
  74                                  216000  900000
  75                                  126000  900000
  76                         >;
  77                         #cooling-cells = <2>; /* min followed by max */
  78                         clock-latency = <40000>;
  79                         clocks = <&cru ARMCLK>;
  80                         resets = <&cru SRST_CORE0>;
  81                 };
  82                 cpu@501 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a12";
  85                         reg = <0x501>;
  86                         resets = <&cru SRST_CORE1>;
  87                 };
  88                 cpu@502 {
  89                         device_type = "cpu";
  90                         compatible = "arm,cortex-a12";
  91                         reg = <0x502>;
  92                         resets = <&cru SRST_CORE2>;
  93                 };
  94                 cpu@503 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a12";
  97                         reg = <0x503>;
  98                         resets = <&cru SRST_CORE3>;
  99                 };
 100         };
 101
 102         amba {
 103                 compatible = "arm,amba-bus";
 104                 #address-cells = <1>;
 105                 #size-cells = <1>;
 106                 ranges;
 107
 108                 dmac_peri: dma-controller@ff250000 {
 109                         compatible = "arm,pl330", "arm,primecell";
 110                         broken-no-flushp;
 111                         reg = <0xff250000 0x4000>;
 112                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 113                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 114                         #dma-cells = <1>;
 115                         clocks = <&cru ACLK_DMAC2>;
 116                         clock-names = "apb_pclk";
 117                 };
 118
 119                 dmac_bus_ns: dma-controller@ff600000 {
 120                         compatible = "arm,pl330", "arm,primecell";
 121                         broken-no-flushp;
 122                         reg = <0xff600000 0x4000>;
 123                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 124                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 125                         #dma-cells = <1>;
 126                         clocks = <&cru ACLK_DMAC1>;
 127                         clock-names = "apb_pclk";
 128                         status = "disabled";
 129                 };
 130
 131                 dmac_bus_s: dma-controller@ffb20000 {
 132                         compatible = "arm,pl330", "arm,primecell";
 133                         broken-no-flushp;
 134                         reg = <0xffb20000 0x4000>;
 135                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 136                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 137                         #dma-cells = <1>;
 138                         clocks = <&cru ACLK_DMAC1>;
 139                         clock-names = "apb_pclk";
 140                 };
 141         };
 142
 143         xin24m: oscillator {
 144                 compatible = "fixed-clock";
 145                 clock-frequency = <24000000>;
 146                 clock-output-names = "xin24m";
 147                 #clock-cells = <0>;
 148         };
 149
 150         timer {
 151                 arm,use-physical-timer;
 152                 compatible = "arm,armv7-timer";
 153                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 154                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 155                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 156                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 157                 clock-frequency = <24000000>;
 158                 always-on;
 159         };
 160
 161         display-subsystem {
 162                 compatible = "rockchip,display-subsystem";
 163                 ports = <&vopl_out>, <&vopb_out>;
 164         };
 165
 166         sdmmc: dwmmc@ff0c0000 {
 167                 compatible = "rockchip,rk3288-dw-mshc";
 168                 max-frequency = <150000000>;
 169                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 170                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 171                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 172                 fifo-depth = <0x100>;
 173                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 174                 reg = <0xff0c0000 0x4000>;
 175                 status = "disabled";
 176         };
 177
 178         sdio0: dwmmc@ff0d0000 {
 179                 compatible = "rockchip,rk3288-dw-mshc";
 180                 max-frequency = <150000000>;
 181                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 182                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 183                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 184                 fifo-depth = <0x100>;
 185                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 186                 reg = <0xff0d0000 0x4000>;
 187                 status = "disabled";
 188         };
 189
 190         sdio1: dwmmc@ff0e0000 {
 191                 compatible = "rockchip,rk3288-dw-mshc";
 192                 max-frequency = <150000000>;
 193                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 194                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 195                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 196                 fifo-depth = <0x100>;
 197                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 198                 reg = <0xff0e0000 0x4000>;
 199                 status = "disabled";
 200         };
 201
 202         emmc: dwmmc@ff0f0000 {
 203                 compatible = "rockchip,rk3288-dw-mshc";
 204                 max-frequency = <150000000>;
 205                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 206                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 207                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 208                 fifo-depth = <0x100>;
 209                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 210                 reg = <0xff0f0000 0x4000>;
 211                 status = "disabled";
 212         };
 213
 214         saradc: saradc@ff100000 {
 215                 compatible = "rockchip,saradc";
 216                 reg = <0xff100000 0x100>;
 217                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 218                 #io-channel-cells = <1>;
 219                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 220                 clock-names = "saradc", "apb_pclk";
 221                 status = "disabled";
 222         };
 223
 224         spi0: spi@ff110000 {
 225                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 226                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 227                 clock-names = "spiclk", "apb_pclk";
 228                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 229                 dma-names = "tx", "rx";
 230                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 231                 pinctrl-names = "default";
 232                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 233                 reg = <0xff110000 0x1000>;
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236                 status = "disabled";
 237         };
 238
 239         spi1: spi@ff120000 {
 240                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 241                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 242                 clock-names = "spiclk", "apb_pclk";
 243                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 244                 dma-names = "tx", "rx";
 245                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 246                 pinctrl-names = "default";
 247                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 248                 reg = <0xff120000 0x1000>;
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251                 status = "disabled";
 252         };
 253
 254         spi2: spi@ff130000 {
 255                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 256                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 257                 clock-names = "spiclk", "apb_pclk";
 258                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 259                 dma-names = "tx", "rx";
 260                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 261                 pinctrl-names = "default";
 262                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 263                 reg = <0xff130000 0x1000>;
 264                 #address-cells = <1>;
 265                 #size-cells = <0>;
 266                 status = "disabled";
 267         };
 268
 269         i2c1: i2c@ff140000 {
 270                 compatible = "rockchip,rk3288-i2c";
 271                 reg = <0xff140000 0x1000>;
 272                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 273                 #address-cells = <1>;
 274                 #size-cells = <0>;
 275                 clock-names = "i2c";
 276                 clocks = <&cru PCLK_I2C1>;
 277                 pinctrl-names = "default";
 278                 pinctrl-0 = <&i2c1_xfer>;
 279                 status = "disabled";
 280         };
 281
 282         i2c3: i2c@ff150000 {
 283                 compatible = "rockchip,rk3288-i2c";
 284                 reg = <0xff150000 0x1000>;
 285                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 286                 #address-cells = <1>;
 287                 #size-cells = <0>;
 288                 clock-names = "i2c";
 289                 clocks = <&cru PCLK_I2C3>;
 290                 pinctrl-names = "default";
 291                 pinctrl-0 = <&i2c3_xfer>;
 292                 status = "disabled";
 293         };
 294
 295         i2c4: i2c@ff160000 {
 296                 compatible = "rockchip,rk3288-i2c";
 297                 reg = <0xff160000 0x1000>;
 298                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301                 clock-names = "i2c";
 302                 clocks = <&cru PCLK_I2C4>;
 303                 pinctrl-names = "default";
 304                 pinctrl-0 = <&i2c4_xfer>;
 305                 status = "disabled";
 306         };
 307
 308         i2c5: i2c@ff170000 {
 309                 compatible = "rockchip,rk3288-i2c";
 310                 reg = <0xff170000 0x1000>;
 311                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 312                 #address-cells = <1>;
 313                 #size-cells = <0>;
 314                 clock-names = "i2c";
 315                 clocks = <&cru PCLK_I2C5>;
 316                 pinctrl-names = "default";
 317                 pinctrl-0 = <&i2c5_xfer>;
 318                 status = "disabled";
 319         };
 320         uart0: serial@ff180000 {
 321                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 322                 reg = <0xff180000 0x100>;
 323                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 324                 reg-shift = <2>;
 325                 reg-io-width = <4>;
 326                 clock-frequency = <24000000>;
 327                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 328                 clock-names = "baudclk", "apb_pclk";
 329                 pinctrl-names = "default";
 330                 pinctrl-0 = <&uart0_xfer>;
 331                 status = "disabled";
 332         };
 333
 334         uart1: serial@ff190000 {
 335                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 336                 reg = <0xff190000 0x100>;
 337                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 338                 reg-shift = <2>;
 339                 reg-io-width = <4>;
 340                 clock-frequency = <24000000>;
 341                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 342                 clock-names = "baudclk", "apb_pclk";
 343                 pinctrl-names = "default";
 344                 pinctrl-0 = <&uart1_xfer>;
 345                 status = "disabled";
 346         };
 347
 348         uart2: serial@ff690000 {
 349                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 350                 reg = <0xff690000 0x100>;
 351                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 352                 reg-shift = <2>;
 353                 reg-io-width = <4>;
 354                 clock-frequency = <24000000>;
 355                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 356                 clock-names = "baudclk", "apb_pclk";
 357                 pinctrl-names = "default";
 358                 pinctrl-0 = <&uart2_xfer>;
 359                 status = "disabled";
 360         };
 361         uart3: serial@ff1b0000 {
 362                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 363                 reg = <0xff1b0000 0x100>;
 364                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 365                 reg-shift = <2>;
 366                 reg-io-width = <4>;
 367                 clock-frequency = <24000000>;
 368                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 369                 clock-names = "baudclk", "apb_pclk";
 370                 pinctrl-names = "default";
 371                 pinctrl-0 = <&uart3_xfer>;
 372                 status = "disabled";
 373         };
 374
 375         uart4: serial@ff1c0000 {
 376                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 377                 reg = <0xff1c0000 0x100>;
 378                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 379                 reg-shift = <2>;
 380                 reg-io-width = <4>;
 381                 clock-frequency = <24000000>;
 382                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 383                 clock-names = "baudclk", "apb_pclk";
 384                 pinctrl-names = "default";
 385                 pinctrl-0 = <&uart4_xfer>;
 386                 status = "disabled";
 387         };
 388         thermal: thermal-zones {
 389                 #include "rk3288-thermal.dtsi"
 390         };
 391
 392         tsadc: tsadc@ff280000 {
 393                 compatible = "rockchip,rk3288-tsadc";
 394                 reg = <0xff280000 0x100>;
 395                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 396                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 397                 clock-names = "tsadc", "apb_pclk";
 398                 resets = <&cru SRST_TSADC>;
 399                 reset-names = "tsadc-apb";
 400                 pinctrl-names = "otp_out";
 401                 pinctrl-0 = <&otp_out>;
 402                 #thermal-sensor-cells = <1>;
 403                 hw-shut-temp = <125000>;
 404                 status = "disabled";
 405         };
 406
 407         gmac: ethernet@ff290000 {
 408                 compatible = "rockchip,rk3288-gmac";
 409                 reg = <0xff290000 0x10000>;
 410                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 411                 interrupt-names = "macirq";
 412                 rockchip,grf = <&grf>;
 413                 clocks = <&cru SCLK_MAC>,
 414                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 415                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 416                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 417                 clock-names = "stmmaceth",
 418                         "mac_clk_rx", "mac_clk_tx",
 419                         "clk_mac_ref", "clk_mac_refout",
 420                         "aclk_mac", "pclk_mac";
 421         };
 422
 423         usb_host0_ehci: usb@ff500000 {
 424                 compatible = "generic-ehci";
 425                 reg = <0xff500000 0x100>;
 426                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 427                 clocks = <&cru HCLK_USBHOST0>;
 428                 clock-names = "usbhost";
 429                 phys = <&usbphy1>;
 430                 phy-names = "usb";
 431                 status = "disabled";
 432         };
 433
 434         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 435
 436         usb_host1: usb@ff540000 {
 437                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 438                                 "snps,dwc2";
 439                 reg = <0xff540000 0x40000>;
 440                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 441                 clocks = <&cru HCLK_USBHOST1>;
 442                 clock-names = "otg";
 443                 phys = <&usbphy2>;
 444                 phy-names = "usb2-phy";
 445                 status = "disabled";
 446         };
 447
 448         usb_otg: usb@ff580000 {
 449                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 450                                 "snps,dwc2";
 451                 reg = <0xff580000 0x40000>;
 452                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 453                 clocks = <&cru HCLK_OTG0>;
 454                 clock-names = "otg";
 455                 dr_mode = "otg";
 456                 phys = <&usbphy0>;
 457                 phy-names = "usb2-phy";
 458                 status = "disabled";
 459         };
 460
 461         usb_hsic: usb@ff5c0000 {
 462                 compatible = "generic-ehci";
 463                 reg = <0xff5c0000 0x100>;
 464                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 465                 clocks = <&cru HCLK_HSIC>;
 466                 clock-names = "usbhost";
 467                 status = "disabled";
 468         };
 469
 470         dmc: dmc@ff610000 {
 471                 compatible = "rockchip,rk3288-dmc", "syscon";
 472                 rockchip,cru = <&cru>;
 473                 rockchip,grf = <&grf>;
 474                 rockchip,pmu = <&pmu>;
 475                 rockchip,sgrf = <&sgrf>;
 476                 rockchip,noc = <&noc>;
 477                 reg = <0xff610000 0x3fc
 478                        0xff620000 0x294
 479                        0xff630000 0x3fc
 480                        0xff640000 0x294>;
 481                 rockchip,sram = <&ddr_sram>;
 482                 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
 483                          <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
 484                          <&cru ARMCLK>;
 485                 clock-names = "pclk_ddrupctl0", "pclk_publ0",
 486                               "pclk_ddrupctl1", "pclk_publ1",
 487                               "arm_clk";
 488         };
 489
 490         i2c0: i2c@ff650000 {
 491                 compatible = "rockchip,rk3288-i2c";
 492                 reg = <0xff650000 0x1000>;
 493                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 494                 #address-cells = <1>;
 495                 #size-cells = <0>;
 496                 clock-names = "i2c";
 497                 clocks = <&cru PCLK_I2C0>;
 498                 pinctrl-names = "default";
 499                 pinctrl-0 = <&i2c0_xfer>;
 500                 status = "disabled";
 501         };
 502
 503         i2c2: i2c@ff660000 {
 504                 compatible = "rockchip,rk3288-i2c";
 505                 reg = <0xff660000 0x1000>;
 506                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 507                 #address-cells = <1>;
 508                 #size-cells = <0>;
 509                 clock-names = "i2c";
 510                 clocks = <&cru PCLK_I2C2>;
 511                 pinctrl-names = "default";
 512                 pinctrl-0 = <&i2c2_xfer>;
 513                 status = "disabled";
 514         };
 515
 516         pwm0: pwm@ff680000 {
 517                 compatible = "rockchip,rk3288-pwm";
 518                 reg = <0xff680000 0x10>;
 519                 #pwm-cells = <3>;
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&pwm0_pin>;
 522                 clocks = <&cru PCLK_PWM>;
 523                 clock-names = "pwm";
 524                 rockchip,grf = <&grf>;
 525                 status = "disabled";
 526         };
 527
 528         pwm1: pwm@ff680010 {
 529                 compatible = "rockchip,rk3288-pwm";
 530                 reg = <0xff680010 0x10>;
 531                 #pwm-cells = <3>;
 532                 pinctrl-names = "default";
 533                 pinctrl-0 = <&pwm1_pin>;
 534                 clocks = <&cru PCLK_PWM>;
 535                 clock-names = "pwm";
 536                 rockchip,grf = <&grf>;
 537                 status = "disabled";
 538         };
 539
 540         pwm2: pwm@ff680020 {
 541                 compatible = "rockchip,rk3288-pwm";
 542                 reg = <0xff680020 0x10>;
 543                 #pwm-cells = <3>;
 544                 pinctrl-names = "default";
 545                 pinctrl-0 = <&pwm2_pin>;
 546                 clocks = <&cru PCLK_PWM>;
 547                 clock-names = "pwm";
 548                 rockchip,grf = <&grf>;
 549                 status = "disabled";
 550         };
 551
 552         pwm3: pwm@ff680030 {
 553                 compatible = "rockchip,rk3288-pwm";
 554                 reg = <0xff680030 0x10>;
 555                 #pwm-cells = <2>;
 556                 pinctrl-names = "default";
 557                 pinctrl-0 = <&pwm3_pin>;
 558                 clocks = <&cru PCLK_PWM>;
 559                 clock-names = "pwm";
 560                 rockchip,grf = <&grf>;
 561                 status = "disabled";
 562         };
 563
 564         bus_intmem@ff700000 {
 565                 compatible = "mmio-sram";
 566                 reg = <0xff700000 0x18000>;
 567                 #address-cells = <1>;
 568                 #size-cells = <1>;
 569                 ranges = <0 0xff700000 0x18000>;
 570                 smp-sram@0 {
 571                         compatible = "rockchip,rk3066-smp-sram";
 572                         reg = <0x00 0x10>;
 573                 };
 574                 ddr_sram: ddr-sram@1000 {
 575                         compatible = "rockchip,rk3288-ddr-sram";
 576                         reg = <0x1000 0x4000>;
 577                 };
 578         };
 579
 580         sram@ff720000 {
 581                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 582                 reg = <0xff720000 0x1000>;
 583         };
 584
 585         pmu: power-management@ff730000 {
 586                 compatible = "rockchip,rk3288-pmu", "syscon";
 587                 reg = <0xff730000 0x100>;
 588         };
 589
 590         sgrf: syscon@ff740000 {
 591                 compatible = "rockchip,rk3288-sgrf", "syscon";
 592                 reg = <0xff740000 0x1000>;
 593         };
 594
 595         cru: clock-controller@ff760000 {
 596                 compatible = "rockchip,rk3288-cru";
 597                 reg = <0xff760000 0x1000>;
 598                 rockchip,grf = <&grf>;
 599                 #clock-cells = <1>;
 600                 #reset-cells = <1>;
 601                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 602                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 603                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 604                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 605                                   <&cru PCLK_PERI>;
 606                 assigned-clock-rates = <594000000>, <400000000>,
 607                                        <500000000>, <300000000>,
 608                                        <150000000>, <75000000>,
 609                                        <300000000>, <150000000>,
 610                                        <75000000>;
 611         };
 612
 613         grf: syscon@ff770000 {
 614                 compatible = "rockchip,rk3288-grf", "syscon";
 615                 reg = <0xff770000 0x1000>;
 616         };
 617
 618         wdt: watchdog@ff800000 {
 619                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 620                 reg = <0xff800000 0x100>;
 621                 clocks = <&cru PCLK_WDT>;
 622                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 623                 status = "disabled";
 624         };
 625
 626         spdif: sound@ff88b0000 {
 627                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 628                 reg = <0xff8b0000 0x10000>;
 629                 #sound-dai-cells = <0>;
 630                 clock-names = "hclk", "mclk";
 631                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 632                 dmas = <&dmac_bus_s 3>;
 633                 dma-names = "tx";
 634                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 635                 pinctrl-names = "default";
 636                 pinctrl-0 = <&spdif_tx>;
 637                 rockchip,grf = <&grf>;
 638                 status = "disabled";
 639         };
 640
 641         i2s: i2s@ff890000 {
 642                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 643                 reg = <0xff890000 0x10000>;
 644                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 645                 #address-cells = <1>;
 646                 #size-cells = <0>;
 647                 #sound-dai-cells = <1>;
 648                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 649                 dma-names = "tx", "rx";
 650                 clock-names = "i2s_hclk", "i2s_clk";
 651                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 652                 pinctrl-names = "default";
 653                 pinctrl-0 = <&i2s0_bus>;
 654                 status = "disabled";
 655         };
 656
 657         vopb: vop@ff930000 {
 658                 compatible = "rockchip,rk3288-vop";
 659                 reg = <0xff930000 0x19c>;
 660                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 661                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 662                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 663                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 664                 reset-names = "axi", "ahb", "dclk";
 665                 iommus = <&vopb_mmu>;
 666                 power-domains = <&power RK3288_PD_VIO>;
 667                 status = "disabled";
 668                 vopb_out: port {
 669                         #address-cells = <1>;
 670                         #size-cells = <0>;
 671                         vopb_out_edp: endpoint@0 {
 672                                 reg = <0>;
 673                                 remote-endpoint = <&edp_in_vopb>;
 674                         };
 675                         vopb_out_hdmi: endpoint@1 {
 676                                 reg = <1>;
 677                                 remote-endpoint = <&hdmi_in_vopb>;
 678                         };
 679                         vopb_out_lvds: endpoint@2 {
 680                                 reg = <2>;
 681                                 remote-endpoint = <&lvds_in_vopb>;
 682                         };
 683                         vopb_out_mipi: endpoint@3 {
 684                                 reg = <3>;
 685                                 remote-endpoint = <&mipi_in_vopb>;
 686                         };
 687
 688                 };
 689         };
 690
 691         vopb_mmu: iommu@ff930300 {
 692                 compatible = "rockchip,iommu";
 693                 reg = <0xff930300 0x100>;
 694                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 695                 interrupt-names = "vopb_mmu";
 696                 power-domains = <&power RK3288_PD_VIO>;
 697                 #iommu-cells = <0>;
 698                 status = "disabled";
 699         };
 700
 701         vopl: vop@ff940000 {
 702                 compatible = "rockchip,rk3288-vop";
 703                 reg = <0xff940000 0x19c>;
 704                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 705                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 706                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 707                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 708                 reset-names = "axi", "ahb", "dclk";
 709                 iommus = <&vopl_mmu>;
 710                 power-domains = <&power RK3288_PD_VIO>;
 711                 status = "disabled";
 712                 vopl_out: port {
 713                         #address-cells = <1>;
 714                         #size-cells = <0>;
 715                         vopl_out_edp: endpoint@0 {
 716                                 reg = <0>;
 717                                 remote-endpoint = <&edp_in_vopl>;
 718                         };
 719                         vopl_out_hdmi: endpoint@1 {
 720                                 reg = <1>;
 721                                 remote-endpoint = <&hdmi_in_vopl>;
 722                         };
 723                         vopl_out_lvds: endpoint@2 {
 724                                 reg = <2>;
 725                                 remote-endpoint = <&lvds_in_vopl>;
 726                         };
 727                         vopl_out_mipi: endpoint@3 {
 728                                 reg = <3>;
 729                                 remote-endpoint = <&mipi_in_vopl>;
 730                         };
 731
 732                 };
 733         };
 734
 735         vopl_mmu: iommu@ff940300 {
 736                 compatible = "rockchip,iommu";
 737                 reg = <0xff940300 0x100>;
 738                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 739                 interrupt-names = "vopl_mmu";
 740                 power-domains = <&power RK3288_PD_VIO>;
 741                 #iommu-cells = <0>;
 742                 status = "disabled";
 743         };
 744
 745         edp: edp@ff970000 {
 746                 compatible = "rockchip,rk3288-edp";
 747                 reg = <0xff970000 0x4000>;
 748                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 749                 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
 750                 rockchip,grf = <&grf>;
 751                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 752                 resets = <&cru 111>;
 753                 reset-names = "edp";
 754                 power-domains = <&power RK3288_PD_VIO>;
 755                 status = "disabled";
 756                 ports {
 757                         edp_in: port {
 758                                 #address-cells = <1>;
 759                                 #size-cells = <0>;
 760                                 edp_in_vopb: endpoint@0 {
 761                                         reg = <0>;
 762                                         remote-endpoint = <&vopb_out_edp>;
 763                                 };
 764                                 edp_in_vopl: endpoint@1 {
 765                                         reg = <1>;
 766                                         remote-endpoint = <&vopl_out_edp>;
 767                                 };
 768                         };
 769                 };
 770         };
 771
 772         hdmi: hdmi@ff980000 {
 773                 compatible = "rockchip,rk3288-dw-hdmi";
 774                 reg = <0xff980000 0x20000>;
 775                 reg-io-width = <4>;
 776                 ddc-i2c-bus = <&i2c5>;
 777                 rockchip,grf = <&grf>;
 778                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 779                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 780                 clock-names = "iahb", "isfr";
 781                 status = "disabled";
 782                 ports {
 783                         hdmi_in: port {
 784                                 #address-cells = <1>;
 785                                 #size-cells = <0>;
 786                                 hdmi_in_vopb: endpoint@0 {
 787                                         reg = <0>;
 788                                         remote-endpoint = <&vopb_out_hdmi>;
 789                                 };
 790                                 hdmi_in_vopl: endpoint@1 {
 791                                         reg = <1>;
 792                                         remote-endpoint = <&vopl_out_hdmi>;
 793                                 };
 794                         };
 795                 };
 796         };
 797
 798         lvds: lvds@ff96c000 {
 799                 compatible = "rockchip,rk3288-lvds";
 800                 reg = <0xff96c000 0x4000>;
 801                 clocks = <&cru PCLK_LVDS_PHY>;
 802                 clock-names = "pclk_lvds";
 803                 pinctrl-names = "default";
 804                 pinctrl-0 = <&lcdc0_ctl>;
 805                 rockchip,grf = <&grf>;
 806                 status = "disabled";
 807                 ports {
 808                         #address-cells = <1>;
 809                         #size-cells = <0>;
 810                         lvds_in: port@0 {
 811                                 reg = <0>;
 812                                 #address-cells = <1>;
 813                                 #size-cells = <0>;
 814                                 lvds_in_vopb: endpoint@0 {
 815                                         reg = <0>;
 816                                         remote-endpoint = <&vopb_out_lvds>;
 817                                 };
 818                                 lvds_in_vopl: endpoint@1 {
 819                                         reg = <1>;
 820                                         remote-endpoint = <&vopl_out_lvds>;
 821                                 };
 822                         };
 823                 };
 824         };
 825
 826         mipi_dsi0: mipi@ff960000 {
 827                 compatible = "rockchip,rk3288_mipi_dsi";
 828                 reg = <0xff960000 0x4000>;
 829                 clocks = <&cru PCLK_MIPI_DSI0>;
 830                 clock-names = "pclk_mipi";
 831                 /*pinctrl-names = "default";
 832                 pinctrl-0 = <&lcdc0_ctl>;*/
 833                 rockchip,grf = <&grf>;
 834                 #address-cells = <1>;
 835                 #size-cells = <0>;
 836                 status = "disabled";
 837                 ports {
 838                         reg = <1>;
 839                         mipi_in: port {
 840                                 #address-cells = <1>;
 841                                 #size-cells = <0>;
 842                                 mipi_in_vopb: endpoint@0 {
 843                                         reg = <0>;
 844                                         remote-endpoint = <&vopb_out_mipi>;
 845                                 };
 846                                 mipi_in_vopl: endpoint@1 {
 847                                         reg = <1>;
 848                                         remote-endpoint = <&vopl_out_mipi>;
 849                                 };
 850                         };
 851                 };
 852         };
 853
 854         hdmi_audio: hdmi_audio {
 855                 compatible = "rockchip,rk3288-hdmi-audio";
 856                 i2s-controller = <&i2s>;
 857                 status = "disable";
 858         };
 859
 860         vpu: video-codec@ff9a0000 {
 861                 compatible = "rockchip,rk3288-vpu";
 862                 reg = <0xff9a0000 0x800>;
 863                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 864                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 865                 interrupt-names = "vepu", "vdpu";
 866                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 867                 clock-names = "aclk_vcodec", "hclk_vcodec";
 868                 power-domains = <&power RK3288_PD_VIDEO>;
 869                 iommus = <&vpu_mmu>;
 870         };
 871
 872         vpu_mmu: iommu@ff9a0800 {
 873                 compatible = "rockchip,iommu";
 874                 reg = <0xff9a0800 0x100>;
 875                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 876                 interrupt-names = "vpu_mmu";
 877                 power-domains = <&power RK3288_PD_VIDEO>;
 878                 #iommu-cells = <0>;
 879         };
 880
 881         gpu: gpu@ffa30000 {
 882                 compatible = "arm,malit764",
 883                              "arm,malit76x",
 884                              "arm,malit7xx",
 885                              "arm,mali-midgard";
 886                 reg = <0xffa30000 0x10000>;
 887                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 888                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 889                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 890                 interrupt-names = "JOB", "MMU", "GPU";
 891                 clocks = <&cru ACLK_GPU>;
 892                 clock-names = "aclk_gpu";
 893                 operating-points = <
 894                         /* KHz uV */
 895                         100000 950000
 896                         200000 950000
 897                         300000 1000000
 898                         400000 1100000
 899                         /* 500000 1200000 - See crosbug.com/p/33857 */
 900                         600000 1250000
 901                 >;
 902                 power-domains = <&power RK3288_PD_GPU>;
 903                 status = "disabled";
 904         };
 905
 906         noc: syscon@ffac0000 {
 907                 compatible = "rockchip,rk3288-noc", "syscon";
 908                 reg = <0xffac0000 0x2000>;
 909         };
 910
 911         efuse: efuse@ffb40000 {
 912                 compatible = "rockchip,rk3288-efuse";
 913                 reg = <0xffb40000 0x10000>;
 914                 status = "disabled";
 915         };
 916
 917         gic: interrupt-controller@ffc01000 {
 918                 compatible = "arm,gic-400";
 919                 interrupt-controller;
 920                 #interrupt-cells = <3>;
 921                 #address-cells = <0>;
 922
 923                 reg = <0xffc01000 0x1000>,
 924                       <0xffc02000 0x1000>,
 925                       <0xffc04000 0x2000>,
 926                       <0xffc06000 0x2000>;
 927                 interrupts = <GIC_PPI 9 0xf04>;
 928         };
 929
 930         cpuidle: cpuidle {
 931                 compatible = "rockchip,rk3288-cpuidle";
 932         };
 933
 934         usbphy: phy {
 935                 compatible = "rockchip,rk3288-usb-phy";
 936                 rockchip,grf = <&grf>;
 937                 #address-cells = <1>;
 938                 #size-cells = <0>;
 939                 status = "disabled";
 940
 941                 usbphy0: usb-phy0 {
 942                         #phy-cells = <0>;
 943                         reg = <0x320>;
 944                         clocks = <&cru SCLK_OTGPHY0>;
 945                         clock-names = "phyclk";
 946                 };
 947
 948                 usbphy1: usb-phy1 {
 949                         #phy-cells = <0>;
 950                         reg = <0x334>;
 951                         clocks = <&cru SCLK_OTGPHY1>;
 952                         clock-names = "phyclk";
 953                 };
 954
 955                 usbphy2: usb-phy2 {
 956                         #phy-cells = <0>;
 957                         reg = <0x348>;
 958                         clocks = <&cru SCLK_OTGPHY2>;
 959                         clock-names = "phyclk";
 960                 };
 961         };
 962
 963         pinctrl: pinctrl {
 964                 compatible = "rockchip,rk3288-pinctrl";
 965                 rockchip,grf = <&grf>;
 966                 rockchip,pmu = <&pmu>;
 967                 #address-cells = <1>;
 968                 #size-cells = <1>;
 969                 ranges;
 970
 971                 gpio0: gpio0@ff750000 {
 972                         compatible = "rockchip,gpio-bank";
 973                         reg =   <0xff750000 0x100>;
 974                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 975                         clocks = <&cru PCLK_GPIO0>;
 976
 977                         gpio-controller;
 978                         #gpio-cells = <2>;
 979
 980                         interrupt-controller;
 981                         #interrupt-cells = <2>;
 982                 };
 983
 984                 gpio1: gpio1@ff780000 {
 985                         compatible = "rockchip,gpio-bank";
 986                         reg = <0xff780000 0x100>;
 987                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 988                         clocks = <&cru PCLK_GPIO1>;
 989
 990                         gpio-controller;
 991                         #gpio-cells = <2>;
 992
 993                         interrupt-controller;
 994                         #interrupt-cells = <2>;
 995                 };
 996
 997                 gpio2: gpio2@ff790000 {
 998                         compatible = "rockchip,gpio-bank";
 999                         reg = <0xff790000 0x100>;
1000                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1001                         clocks = <&cru PCLK_GPIO2>;
1002
1003                         gpio-controller;
1004                         #gpio-cells = <2>;
1005
1006                         interrupt-controller;
1007                         #interrupt-cells = <2>;
1008                 };
1009
1010                 gpio3: gpio3@ff7a0000 {
1011                         compatible = "rockchip,gpio-bank";
1012                         reg = <0xff7a0000 0x100>;
1013                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1014                         clocks = <&cru PCLK_GPIO3>;
1015
1016                         gpio-controller;
1017                         #gpio-cells = <2>;
1018
1019                         interrupt-controller;
1020                         #interrupt-cells = <2>;
1021                 };
1022
1023                 gpio4: gpio4@ff7b0000 {
1024                         compatible = "rockchip,gpio-bank";
1025                         reg = <0xff7b0000 0x100>;
1026                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1027                         clocks = <&cru PCLK_GPIO4>;
1028
1029                         gpio-controller;
1030                         #gpio-cells = <2>;
1031
1032                         interrupt-controller;
1033                         #interrupt-cells = <2>;
1034                 };
1035
1036                 gpio5: gpio5@ff7c0000 {
1037                         compatible = "rockchip,gpio-bank";
1038                         reg = <0xff7c0000 0x100>;
1039                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1040                         clocks = <&cru PCLK_GPIO5>;
1041
1042                         gpio-controller;
1043                         #gpio-cells = <2>;
1044
1045                         interrupt-controller;
1046                         #interrupt-cells = <2>;
1047                 };
1048
1049                 gpio6: gpio6@ff7d0000 {
1050                         compatible = "rockchip,gpio-bank";
1051                         reg = <0xff7d0000 0x100>;
1052                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1053                         clocks = <&cru PCLK_GPIO6>;
1054
1055                         gpio-controller;
1056                         #gpio-cells = <2>;
1057
1058                         interrupt-controller;
1059                         #interrupt-cells = <2>;
1060                 };
1061
1062                 gpio7: gpio7@ff7e0000 {
1063                         compatible = "rockchip,gpio-bank";
1064                         reg = <0xff7e0000 0x100>;
1065                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1066                         clocks = <&cru PCLK_GPIO7>;
1067
1068                         gpio-controller;
1069                         #gpio-cells = <2>;
1070
1071                         interrupt-controller;
1072                         #interrupt-cells = <2>;
1073                 };
1074
1075                 gpio8: gpio8@ff7f0000 {
1076                         compatible = "rockchip,gpio-bank";
1077                         reg = <0xff7f0000 0x100>;
1078                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1079                         clocks = <&cru PCLK_GPIO8>;
1080
1081                         gpio-controller;
1082                         #gpio-cells = <2>;
1083
1084                         interrupt-controller;
1085                         #interrupt-cells = <2>;
1086                 };
1087
1088                 pcfg_pull_up: pcfg-pull-up {
1089                         bias-pull-up;
1090                 };
1091
1092                 pcfg_pull_down: pcfg-pull-down {
1093                         bias-pull-down;
1094                 };
1095
1096                 pcfg_pull_none: pcfg-pull-none {
1097                         bias-disable;
1098                 };
1099
1100                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1101                         bias-disable;
1102                         drive-strength = <12>;
1103                 };
1104
1105                 sleep {
1106                         global_pwroff: global-pwroff {
1107                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1108                         };
1109
1110                         ddrio_pwroff: ddrio-pwroff {
1111                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1112                         };
1113
1114                         ddr0_retention: ddr0-retention {
1115                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1116                         };
1117
1118                         ddr1_retention: ddr1-retention {
1119                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1120                         };
1121                 };
1122
1123                 i2c0 {
1124                         i2c0_xfer: i2c0-xfer {
1125                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1126                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1127                         };
1128                 };
1129
1130                 i2c1 {
1131                         i2c1_xfer: i2c1-xfer {
1132                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1133                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1134                         };
1135                 };
1136
1137                 i2c2 {
1138                         i2c2_xfer: i2c2-xfer {
1139                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1140                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1141                         };
1142                 };
1143
1144                 i2c3 {
1145                         i2c3_xfer: i2c3-xfer {
1146                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1147                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1148                         };
1149                 };
1150
1151                 i2c4 {
1152                         i2c4_xfer: i2c4-xfer {
1153                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1154                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1155                         };
1156                 };
1157
1158                 i2c5 {
1159                         i2c5_xfer: i2c5-xfer {
1160                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1161                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1162                         };
1163                 };
1164
1165                 i2s0 {
1166                         i2s0_bus: i2s0-bus {
1167                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1168                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1169                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1170                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1171                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1172                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1173                         };
1174                 };
1175
1176                 lcdc0 {
1177                         lcdc0_ctl: lcdc0-ctl {
1178                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1179                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1180                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1181                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1182                         };
1183                 };
1184
1185                 sdmmc {
1186                         sdmmc_clk: sdmmc-clk {
1187                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1188                         };
1189
1190                         sdmmc_cmd: sdmmc-cmd {
1191                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1192                         };
1193
1194                         sdmmc_cd: sdmcc-cd {
1195                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1196                         };
1197
1198                         sdmmc_bus1: sdmmc-bus1 {
1199                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1200                         };
1201
1202                         sdmmc_bus4: sdmmc-bus4 {
1203                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1204                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1205                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1206                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1207                         };
1208                 };
1209
1210                 sdio0 {
1211                         sdio0_bus1: sdio0-bus1 {
1212                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1213                         };
1214
1215                         sdio0_bus4: sdio0-bus4 {
1216                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1217                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1218                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1219                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1220                         };
1221
1222                         sdio0_cmd: sdio0-cmd {
1223                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1224                         };
1225
1226                         sdio0_clk: sdio0-clk {
1227                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1228                         };
1229
1230                         sdio0_cd: sdio0-cd {
1231                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1232                         };
1233
1234                         sdio0_wp: sdio0-wp {
1235                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1236                         };
1237
1238                         sdio0_pwr: sdio0-pwr {
1239                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1240                         };
1241
1242                         sdio0_bkpwr: sdio0-bkpwr {
1243                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1244                         };
1245
1246                         sdio0_int: sdio0-int {
1247                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1248                         };
1249                 };
1250
1251                 sdio1 {
1252                         sdio1_bus1: sdio1-bus1 {
1253                                 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>;
1254                         };
1255
1256                         sdio1_bus4: sdio1-bus4 {
1257                                 rockchip,pins = <3 24 RK_FUNC_4 &pcfg_pull_up>,
1258                                                 <3 25 RK_FUNC_4 &pcfg_pull_up>,
1259                                                 <3 26 RK_FUNC_4 &pcfg_pull_up>,
1260                                                 <3 27 RK_FUNC_4 &pcfg_pull_up>;
1261                         };
1262
1263                         sdio1_cd: sdio1-cd {
1264                                 rockchip,pins = <3 28 RK_FUNC_4 &pcfg_pull_up>;
1265                         };
1266
1267                         sdio1_wp: sdio1-wp {
1268                                 rockchip,pins = <3 29 RK_FUNC_4 &pcfg_pull_up>;
1269                         };
1270
1271                         sdio1_bkpwr: sdio1-bkpwr {
1272                                 rockchip,pins = <3 30 RK_FUNC_4 &pcfg_pull_up>;
1273                         };
1274
1275                         sdio1_int: sdio1-int {
1276                                 rockchip,pins = <3 31 RK_FUNC_4 &pcfg_pull_up>;
1277                         };
1278
1279                         sdio1_cmd: sdio1-cmd {
1280                                 rockchip,pins = <4 6 RK_FUNC_4 &pcfg_pull_up>;
1281                         };
1282
1283                         sdio1_clk: sdio1-clk {
1284                                 rockchip,pins = <4 7 RK_FUNC_4 &pcfg_pull_none>;
1285                         };
1286
1287                         sdio1_pwr: sdio1-pwr {
1288                                 rockchip,pins = <4 9 RK_FUNC_4 &pcfg_pull_up>;
1289                         };
1290                 };
1291
1292                 emmc {
1293                         emmc_clk: emmc-clk {
1294                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1295                         };
1296
1297                         emmc_cmd: emmc-cmd {
1298                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1299                         };
1300
1301                         emmc_pwr: emmc-pwr {
1302                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1303                         };
1304
1305                         emmc_bus1: emmc-bus1 {
1306                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1307                         };
1308
1309                         emmc_bus4: emmc-bus4 {
1310                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1311                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1312                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1313                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1314                         };
1315
1316                         emmc_bus8: emmc-bus8 {
1317                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1318                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1319                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1320                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1321                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1322                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1323                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1324                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1325                         };
1326                 };
1327
1328                 spi0 {
1329                         spi0_clk: spi0-clk {
1330                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1331                         };
1332                         spi0_cs0: spi0-cs0 {
1333                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1334                         };
1335                         spi0_tx: spi0-tx {
1336                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1337                         };
1338                         spi0_rx: spi0-rx {
1339                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1340                         };
1341                         spi0_cs1: spi0-cs1 {
1342                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1343                         };
1344                 };
1345                 spi1 {
1346                         spi1_clk: spi1-clk {
1347                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1348                         };
1349                         spi1_cs0: spi1-cs0 {
1350                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1351                         };
1352                         spi1_rx: spi1-rx {
1353                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1354                         };
1355                         spi1_tx: spi1-tx {
1356                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1357                         };
1358                 };
1359
1360                 spi2 {
1361                         spi2_cs1: spi2-cs1 {
1362                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1363                         };
1364                         spi2_clk: spi2-clk {
1365                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1366                         };
1367                         spi2_cs0: spi2-cs0 {
1368                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1369                         };
1370                         spi2_rx: spi2-rx {
1371                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1372                         };
1373                         spi2_tx: spi2-tx {
1374                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1375                         };
1376                 };
1377
1378                 uart0 {
1379                         uart0_xfer: uart0-xfer {
1380                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1381                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1382                         };
1383
1384                         uart0_cts: uart0-cts {
1385                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1386                         };
1387
1388                         uart0_rts: uart0-rts {
1389                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1390                         };
1391                 };
1392
1393                 uart1 {
1394                         uart1_xfer: uart1-xfer {
1395                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1396                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1397                         };
1398
1399                         uart1_cts: uart1-cts {
1400                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1401                         };
1402
1403                         uart1_rts: uart1-rts {
1404                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1405                         };
1406                 };
1407
1408                 uart2 {
1409                         uart2_xfer: uart2-xfer {
1410                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1411                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1412                         };
1413                         /* no rts / cts for uart2 */
1414                 };
1415
1416                 uart3 {
1417                         uart3_xfer: uart3-xfer {
1418                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1419                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1420                         };
1421
1422                         uart3_cts: uart3-cts {
1423                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1424                         };
1425
1426                         uart3_rts: uart3-rts {
1427                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1428                         };
1429                 };
1430
1431                 uart4 {
1432                         uart4_xfer: uart4-xfer {
1433                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1434                                                 <5 13 3 &pcfg_pull_none>;
1435                         };
1436
1437                         uart4_cts: uart4-cts {
1438                                 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1439                         };
1440
1441                         uart4_rts: uart4-rts {
1442                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1443                         };
1444                 };
1445
1446                 tsadc {
1447                         otp_out: otp-out {
1448                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1449                         };
1450                 };
1451
1452                 pwm0 {
1453                         pwm0_pin: pwm0-pin {
1454                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1455                         };
1456                 };
1457
1458                 pwm1 {
1459                         pwm1_pin: pwm1-pin {
1460                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1461                         };
1462                 };
1463
1464                 pwm2 {
1465                         pwm2_pin: pwm2-pin {
1466                                 rockchip,pins = <7 22 RK_FUNC_3 &pcfg_pull_none>;
1467                         };
1468                 };
1469
1470                 pwm3 {
1471                         pwm3_pin: pwm3-pin {
1472                                 rockchip,pins = <7 23 RK_FUNC_3 &pcfg_pull_none>;
1473                         };
1474                 };
1475
1476                 gmac {
1477                         rgmii_pins: rgmii-pins {
1478                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1479                                                 <3 31 3 &pcfg_pull_none>,
1480                                                 <3 26 3 &pcfg_pull_none>,
1481                                                 <3 27 3 &pcfg_pull_none>,
1482                                                 <3 28 3 &pcfg_pull_none_12ma>,
1483                                                 <3 29 3 &pcfg_pull_none_12ma>,
1484                                                 <3 24 3 &pcfg_pull_none_12ma>,
1485                                                 <3 25 3 &pcfg_pull_none_12ma>,
1486                                                 <4 0 3 &pcfg_pull_none>,
1487                                                 <4 5 3 &pcfg_pull_none>,
1488                                                 <4 6 3 &pcfg_pull_none>,
1489                                                 <4 9 3 &pcfg_pull_none_12ma>,
1490                                                 <4 4 3 &pcfg_pull_none_12ma>,
1491                                                 <4 1 3 &pcfg_pull_none>,
1492                                                 <4 3 3 &pcfg_pull_none>;
1493                         };
1494
1495                         rmii_pins: rmii-pins {
1496                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1497                                                 <3 31 3 &pcfg_pull_none>,
1498                                                 <3 28 3 &pcfg_pull_none>,
1499                                                 <3 29 3 &pcfg_pull_none>,
1500                                                 <4 0 3 &pcfg_pull_none>,
1501                                                 <4 5 3 &pcfg_pull_none>,
1502                                                 <4 4 3 &pcfg_pull_none>,
1503                                                 <4 1 3 &pcfg_pull_none>,
1504                                                 <4 2 3 &pcfg_pull_none>,
1505                                                 <4 3 3 &pcfg_pull_none>;
1506                         };
1507                 };
1508
1509                 spdif {
1510                         spdif_tx: spdif-tx {
1511                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1512                         };
1513                 };
1514         };
1515
1516         power: power-controller {
1517                 compatible = "rockchip,rk3288-power-controller";
1518                 #power-domain-cells = <1>;
1519                 rockchip,pmu = <&pmu>;
1520                 #address-cells = <1>;
1521                 #size-cells = <0>;
1522
1523                 pd_gpu {
1524                         reg = <RK3288_PD_GPU>;
1525                         clocks = <&cru ACLK_GPU>;
1526                 };
1527
1528                 pd_hevc {
1529                         reg = <RK3288_PD_HEVC>;
1530                         clocks = <&cru ACLK_HEVC>,
1531                                  <&cru SCLK_HEVC_CABAC>,
1532                                  <&cru SCLK_HEVC_CORE>,
1533                                  <&cru HCLK_HEVC>;
1534                 };
1535
1536                 pd_vio {
1537                         reg = <RK3288_PD_VIO>;
1538                         clocks = <&cru ACLK_IEP>,
1539                                  <&cru ACLK_ISP>,
1540                                  <&cru ACLK_RGA>,
1541                                  <&cru ACLK_VIP>,
1542                                  <&cru ACLK_VOP0>,
1543                                  <&cru ACLK_VOP1>,
1544                                  <&cru DCLK_VOP0>,
1545                                  <&cru DCLK_VOP1>,
1546                                  <&cru HCLK_IEP>,
1547                                  <&cru HCLK_ISP>,
1548                                  <&cru HCLK_RGA>,
1549                                  <&cru HCLK_VIP>,
1550                                  <&cru HCLK_VOP0>,
1551                                  <&cru HCLK_VOP1>,
1552                                  <&cru PCLK_EDP_CTRL>,
1553                                  <&cru PCLK_HDMI_CTRL>,
1554                                  <&cru PCLK_LVDS_PHY>,
1555                                  <&cru PCLK_MIPI_CSI>,
1556                                  <&cru PCLK_MIPI_DSI0>,
1557                                  <&cru PCLK_MIPI_DSI1>,
1558                                  <&cru SCLK_EDP_24M>,
1559                                  <&cru SCLK_EDP>,
1560                                  <&cru SCLK_HDMI_CEC>,
1561                                  <&cru SCLK_HDMI_HDCP>,
1562                                  <&cru SCLK_ISP_JPE>,
1563                                  <&cru SCLK_ISP>,
1564                                  <&cru SCLK_RGA>;
1565                 };
1566
1567                 pd_video {
1568                         reg = <RK3288_PD_VIDEO>;
1569                         clocks = <&cru ACLK_VCODEC>,
1570                                  <&cru HCLK_VCODEC>;
1571                 };
1572         };
1573 };