arch/arm/dts/mt7622.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019 MediaTek Inc.
   4  * Author: Sam Shih <sam.shih@mediatek.com>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/clock/mt7622-clk.h>
  10 #include <dt-bindings/power/mt7629-power.h>
  11 #include <dt-bindings/reset/mt7629-reset.h>
  12 #include <dt-bindings/gpio/gpio.h>
  13 #include <dt-bindings/phy/phy.h>
  14
  15 / {
  16         compatible = "mediatek,mt7622";
  17         interrupt-parent = <&sysirq>;
  18         #address-cells = <1>;
  19         #size-cells = <1>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu0: cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a53";
  28                         reg = <0x0>;
  29                         clock-frequency = <1300000000>;
  30                 };
  31
  32                 cpu1: cpu@1 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a53";
  35                         reg = <0x1>;
  36                         clock-frequency = <1300000000>;
  37                 };
  38         };
  39
  40         snfi: snfi@1100d000 {
  41                 compatible = "mediatek,mtk-snfi-spi";
  42                 reg = <0x1100d000 0x2000>;
  43                 clocks = <&pericfg CLK_PERI_NFI_PD>,
  44                          <&pericfg CLK_PERI_SNFI_PD>;
  45                 clock-names = "nfi_clk", "pad_clk";
  46                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
  47                                   <&topckgen CLK_TOP_NFI_INFRA_SEL>;
  48
  49                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
  50                                          <&topckgen CLK_TOP_UNIVPLL2_D8>;
  51                 status = "disabled";
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54         };
  55
  56         timer {
  57                 compatible = "arm,armv8-timer";
  58                 interrupt-parent = <&gic>;
  59                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  60                               IRQ_TYPE_LEVEL_HIGH)>,
  61                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  62                               IRQ_TYPE_LEVEL_HIGH)>,
  63                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
  64                               IRQ_TYPE_LEVEL_HIGH)>,
  65                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  66                               IRQ_TYPE_LEVEL_HIGH)>;
  67                 arm,cpu-registers-not-fw-configured;
  68         };
  69
  70         timer0: timer@10004000 {
  71                 compatible = "mediatek,timer";
  72                 reg = <0x10004000 0x80>;
  73                 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
  74                 clocks = <&system_clk>;
  75                 clock-names = "system-clk";
  76         };
  77
  78         system_clk: dummy13m {
  79                 compatible = "fixed-clock";
  80                 clock-frequency = <13000000>;
  81                 #clock-cells = <0>;
  82         };
  83
  84         infracfg: infracfg@10000000 {
  85                 compatible = "mediatek,mt7622-infracfg",
  86                              "syscon";
  87                 reg = <0x10000000 0x1000>;
  88                 #clock-cells = <1>;
  89                 #reset-cells = <1>;
  90         };
  91
  92         pericfg: pericfg@10002000 {
  93                 compatible = "mediatek,mt7622-pericfg", "syscon";
  94                 reg = <0x10002000 0x1000>;
  95                 #clock-cells = <1>;
  96         };
  97
  98         scpsys: scpsys@10006000 {
  99                 compatible = "mediatek,mt7622-scpsys",
 100                              "syscon";
 101                 #power-domain-cells = <1>;
 102                 reg = <0x10006000 0x1000>;
 103                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
 104                              <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
 105                              <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
 106                              <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
 107                 infracfg = <&infracfg>;
 108                 clocks = <&topckgen CLK_TOP_HIF_SEL>;
 109                 clock-names = "hif_sel";
 110         };
 111
 112         sysirq: interrupt-controller@10200620 {
 113                 compatible = "mediatek,sysirq";
 114                 reg = <0x10200620 0x20>;
 115                 interrupt-controller;
 116                 #interrupt-cells = <3>;
 117                 interrupt-parent = <&gic>;
 118         };
 119
 120         apmixedsys: apmixedsys@10209000 {
 121                 compatible = "mediatek,mt7622-apmixedsys";
 122                 reg = <0x10209000 0x1000>;
 123                 #clock-cells = <1>;
 124         };
 125
 126         topckgen: topckgen@10210000 {
 127                 compatible = "mediatek,mt7622-topckgen";
 128                 reg = <0x10210000 0x1000>;
 129                 #clock-cells = <1>;
 130         };
 131
 132         pinctrl: pinctrl@10211000 {
 133                 compatible = "mediatek,mt7622-pinctrl";
 134                 reg = <0x10211000 0x1000>;
 135                 gpio: gpio-controller {
 136                         gpio-controller;
 137                         #gpio-cells = <2>;
 138                 };
 139         };
 140
 141         watchdog: watchdog@10212000 {
 142                 compatible = "mediatek,wdt";
 143                 reg = <0x10212000 0x800>;
 144         };
 145
 146         wdt-reboot {
 147                 compatible = "wdt-reboot";
 148                 wdt = <&watchdog>;
 149         };
 150
 151         gic: interrupt-controller@10300000 {
 152                 compatible = "arm,gic-400";
 153                 interrupt-controller;
 154                 #interrupt-cells = <3>;
 155                 interrupt-parent = <&gic>;
 156                 reg = <0x10310000 0x1000>,
 157                       <0x10320000 0x1000>,
 158                       <0x10340000 0x2000>,
 159                       <0x10360000 0x2000>;
 160         };
 161
 162         uart0: serial@11002000 {
 163                 compatible = "mediatek,hsuart";
 164                 reg = <0x11002000 0x400>;
 165                 reg-shift = <2>;
 166                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
 167                 clocks = <&topckgen CLK_TOP_UART_SEL>,
 168                          <&pericfg CLK_PERI_UART0_PD>;
 169                 clock-names = "baud", "bus";
 170                 status = "disabled";
 171                 assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 172                 assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
 173         };
 174
 175         mmc0: mmc@11230000 {
 176                 compatible = "mediatek,mt7622-mmc";
 177                 reg = <0x11230000 0x1000>;
 178                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
 179                 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
 180                          <&topckgen CLK_TOP_MSDC50_0_SEL>;
 181                 clock-names = "source", "hclk";
 182                 status = "disabled";
 183         };
 184
 185         mmc1: mmc@11240000 {
 186                 compatible = "mediatek,mt7622-mmc";
 187                 reg = <0x11240000 0x1000>;
 188                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
 189                 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
 190                          <&topckgen CLK_TOP_AXI_SEL>;
 191                 clock-names = "source", "hclk";
 192                 status = "disabled";
 193         };
 194
 195         ssusbsys: ssusbsys@1a000000 {
 196                 compatible = "mediatek,mt7622-ssusbsys",
 197                              "syscon";
 198                 reg = <0x1a000000 0x1000>;
 199                 #clock-cells = <1>;
 200                 #reset-cells = <1>;
 201         };
 202
 203         pciesys: pciesys@1a100800 {
 204                 compatible = "mediatek,mt7622-pciesys", "syscon";
 205                 reg = <0x1a100800 0x1000>;
 206                 #clock-cells = <1>;
 207                 #reset-cells = <1>;
 208         };
 209
 210         pcie: pcie@1a140000 {
 211                 compatible = "mediatek,mt7622-pcie";
 212                 device_type = "pci";
 213                 reg = <0x1a140000 0x1000>,
 214                       <0x1a143000 0x1000>,
 215                       <0x1a145000 0x1000>;
 216                 reg-names = "subsys", "port0", "port1";
 217                 #address-cells = <3>;
 218                 #size-cells = <2>;
 219                 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
 220                              <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
 221                 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
 222                          <&pciesys CLK_PCIE_P1_MAC_EN>,
 223                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 224                          <&pciesys CLK_PCIE_P0_AHB_EN>,
 225                          <&pciesys CLK_PCIE_P0_AUX_EN>,
 226                          <&pciesys CLK_PCIE_P1_AUX_EN>,
 227                          <&pciesys CLK_PCIE_P0_AXI_EN>,
 228                          <&pciesys CLK_PCIE_P1_AXI_EN>,
 229                          <&pciesys CLK_PCIE_P0_OBFF_EN>,
 230                          <&pciesys CLK_PCIE_P1_OBFF_EN>,
 231                          <&pciesys CLK_PCIE_P0_PIPE_EN>,
 232                          <&pciesys CLK_PCIE_P1_PIPE_EN>;
 233                 clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
 234                               "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
 235                               "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
 236                 power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF0>;
 237                 bus-range = <0x00 0xff>;
 238                 ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
 239                 status = "disabled";
 240
 241                 pcie0: pcie@0,0 {
 242                         reg = <0x0000 0 0 0 0>;
 243                         #address-cells = <3>;
 244                         #size-cells = <2>;
 245                         #interrupt-cells = <1>;
 246                         ranges;
 247                         status = "disabled";
 248
 249                         interrupt-map-mask = <0 0 0 7>;
 250                         interrupt-map = <0 0 0 1 &pcie_intc0 0>,
 251                                         <0 0 0 2 &pcie_intc0 1>,
 252                                         <0 0 0 3 &pcie_intc0 2>,
 253                                         <0 0 0 4 &pcie_intc0 3>;
 254                         pcie_intc0: interrupt-controller {
 255                                 interrupt-controller;
 256                                 #address-cells = <0>;
 257                                 #interrupt-cells = <1>;
 258                         };
 259                 };
 260
 261                 pcie1: pcie@1,0 {
 262                         reg = <0x0800 0 0 0 0>;
 263                         #address-cells = <3>;
 264                         #size-cells = <2>;
 265                         #interrupt-cells = <1>;
 266                         ranges;
 267                         status = "disabled";
 268
 269                         interrupt-map-mask = <0 0 0 7>;
 270                         interrupt-map = <0 0 0 1 &pcie_intc1 0>,
 271                                         <0 0 0 2 &pcie_intc1 1>,
 272                                         <0 0 0 3 &pcie_intc1 2>,
 273                                         <0 0 0 4 &pcie_intc1 3>;
 274                         pcie_intc1: interrupt-controller {
 275                                 interrupt-controller;
 276                                 #address-cells = <0>;
 277                                 #interrupt-cells = <1>;
 278                         };
 279                 };
 280         };
 281
 282         sata: sata@1a200000 {
 283                 compatible = "mediatek,mtk-ahci";
 284                 reg = <0x1a200000 0x1100>;
 285                 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
 286                         <&pciesys MT7622_SATA_PHY_SW_RST>,
 287                         <&pciesys MT7622_SATA_PHY_REG_RST>;
 288                 reset-names = "axi", "sw", "reg";
 289                 mediatek,phy-mode = <&pciesys>;
 290                 ports-implemented = <0x1>;
 291                 phys = <&sata_port PHY_TYPE_SATA>;
 292                 phy-names = "sata-phy";
 293                 status = "okay";
 294         };
 295
 296         sata_phy: sata-phy@1a243000 {
 297                 compatible = "mediatek,generic-tphy-v1";
 298                 reg = <0x1a243000 0x0100>;
 299                 #address-cells = <1>;
 300                 #size-cells = <1>;
 301                 ranges;
 302                 status = "okay";
 303
 304                 sata_port: sata-phy@1a243000 {
 305                         reg = <0x1a243000 0x0100>;
 306                         clocks = <&topckgen CLK_TOP_ETH_500M>;
 307                         clock-names = "ref";
 308                         #phy-cells = <1>;
 309                         status = "okay";
 310                 };
 311         };
 312
 313         ssusb: usb@1a0c0000 {
 314                 compatible = "mediatek,mt7622-xhci",
 315                              "mediatek,mtk-xhci";
 316                 reg = <0x1a0c0000 0x01000>,
 317                       <0x1a0c4700 0x0100>;
 318                 reg-names = "mac", "ippc";
 319                 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
 320                 power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
 321                 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
 322                          <&ssusbsys CLK_SSUSB_REF_EN>,
 323                          <&ssusbsys CLK_SSUSB_MCU_EN>,
 324                          <&ssusbsys CLK_SSUSB_DMA_EN>;
 325                 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
 326                 phys = <&u2port0 PHY_TYPE_USB2>,
 327                        <&u3port0 PHY_TYPE_USB3>,
 328                        <&u2port1 PHY_TYPE_USB2>;
 329                 status = "disabled";
 330         };
 331
 332         u3phy: usb-phy@1a0c4000 {
 333                 compatible = "mediatek,mt7622-u3phy",
 334                              "mediatek,generic-tphy-v1";
 335                 reg = <0x1a0c4000 0x700>;
 336                 #address-cells = <1>;
 337                 #size-cells = <1>;
 338                 ranges;
 339                 status = "disabled";
 340
 341                 u2port0: usb-phy@1a0c4800 {
 342                         reg = <0x1a0c4800 0x0100>;
 343                         #phy-cells = <1>;
 344                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
 345                         clock-names = "ref";
 346                 };
 347
 348                 u3port0: usb-phy@1a0c4900 {
 349                         reg = <0x1a0c4900 0x0700>;
 350                         #phy-cells = <1>;
 351                 };
 352
 353                 u2port1: usb-phy@1a0c5000 {
 354                         reg = <0x1a0c5000 0x0100>;
 355                         #phy-cells = <1>;
 356                         clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
 357                         clock-names = "ref";
 358                 };
 359         };
 360
 361         ethsys: syscon@1b000000 {
 362                 compatible = "mediatek,mt7622-ethsys", "syscon";
 363                 reg = <0x1b000000 0x1000>;
 364                 #clock-cells = <1>;
 365                 #reset-cells = <1>;
 366         };
 367
 368         eth: ethernet@1b100000 {
 369                 compatible = "mediatek,mt7622-eth", "syscon";
 370                 reg = <0x1b100000 0x20000>;
 371                 clocks = <&topckgen CLK_TOP_ETH_SEL>,
 372                          <&ethsys CLK_ETH_ESW_EN>,
 373                          <&ethsys CLK_ETH_GP0_EN>,
 374                          <&ethsys CLK_ETH_GP1_EN>,
 375                          <&ethsys CLK_ETH_GP2_EN>,
 376                          <&sgmiisys CLK_SGMII_TX250M_EN>,
 377                          <&sgmiisys CLK_SGMII_RX250M_EN>,
 378                          <&sgmiisys CLK_SGMII_CDR_REF>,
 379                          <&sgmiisys CLK_SGMII_CDR_FB>,
 380                          <&topckgen CLK_TOP_SGMIIPLL>,
 381                          <&apmixedsys CLK_APMIXED_ETH2PLL>;
 382                 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
 383                               "sgmii_tx250m", "sgmii_rx250m",
 384                               "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
 385                               "eth2pll";
 386                 power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
 387                 resets = <&ethsys ETHSYS_FE_RST>;
 388                 reset-names = "fe";
 389                 mediatek,ethsys = <&ethsys>;
 390                 mediatek,sgmiisys = <&sgmiisys>;
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 status = "disabled";
 394         };
 395
 396         sgmiisys: sgmiisys@1b128000 {
 397                 compatible = "mediatek,mt7622-sgmiisys", "syscon";
 398                 reg = <0x1b128000 0x3000>;
 399                 #clock-cells = <1>;
 400         };
 401
 402         pwm: pwm@11006000 {
 403                 compatible = "mediatek,mt7622-pwm";
 404                 reg = <0x11006000 0x1000>;
 405                 #clock-cells = <1>;
 406                 #pwm-cells = <2>;
 407                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
 408                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
 409                          <&pericfg CLK_PERI_PWM_PD>,
 410                          <&pericfg CLK_PERI_PWM1_PD>,
 411                          <&pericfg CLK_PERI_PWM2_PD>,
 412                          <&pericfg CLK_PERI_PWM3_PD>,
 413                          <&pericfg CLK_PERI_PWM4_PD>,
 414                          <&pericfg CLK_PERI_PWM5_PD>,
 415                          <&pericfg CLK_PERI_PWM6_PD>;
 416                 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
 417                               "pwm5", "pwm6";
 418                 status = "disabled";
 419         };
 420
 421 };