arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014-2015, Freescale Semiconductor, Inc.
   4  * Copyright 2019-2020 NXP
   5  *
   6  * Derived from arch/power/cpu/mpc85xx/speed.c
   7  */
   8
   9 #include <common.h>
  10 #include <clock_legacy.h>
  11 #include <cpu_func.h>
  12 #include <asm/global_data.h>
  13 #include <linux/compiler.h>
  14 #include <fsl_ifc.h>
  15 #include <asm/processor.h>
  16 #include <asm/io.h>
  17 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
  18 #include <asm/arch/clock.h>
  19 #include <asm/arch/soc.h>
  20 #include "cpu.h"
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 void get_sys_info(struct sys_info *sys_info)
  25 {
  26         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  27         struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
  28                 (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
  29                 (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
  30         };
  31         struct ccsr_clk_ctrl __iomem *clk_ctrl =
  32                 (void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
  33         unsigned int cpu;
  34         const u8 core_cplx_pll[16] = {
  35                 [0] = 0,        /* CC1 PPL / 1 */
  36                 [1] = 0,        /* CC1 PPL / 2 */
  37                 [2] = 0,        /* CC1 PPL / 4 */
  38                 [4] = 1,        /* CC2 PPL / 1 */
  39                 [5] = 1,        /* CC2 PPL / 2 */
  40                 [6] = 1,        /* CC2 PPL / 4 */
  41                 [8] = 2,        /* CC3 PPL / 1 */
  42                 [9] = 2,        /* CC3 PPL / 2 */
  43                 [10] = 2,       /* CC3 PPL / 4 */
  44                 [12] = 3,       /* CC4 PPL / 1 */
  45                 [13] = 3,       /* CC4 PPL / 2 */
  46                 [14] = 3,       /* CC4 PPL / 4 */
  47         };
  48
  49         const u8 core_cplx_pll_div[16] = {
  50                 [0] = 1,        /* CC1 PPL / 1 */
  51                 [1] = 2,        /* CC1 PPL / 2 */
  52                 [2] = 4,        /* CC1 PPL / 4 */
  53                 [4] = 1,        /* CC2 PPL / 1 */
  54                 [5] = 2,        /* CC2 PPL / 2 */
  55                 [6] = 4,        /* CC2 PPL / 4 */
  56                 [8] = 1,        /* CC3 PPL / 1 */
  57                 [9] = 2,        /* CC3 PPL / 2 */
  58                 [10] = 4,       /* CC3 PPL / 4 */
  59                 [12] = 1,       /* CC4 PPL / 1 */
  60                 [13] = 2,       /* CC4 PPL / 2 */
  61                 [14] = 4,       /* CC4 PPL / 4 */
  62         };
  63
  64         uint i, cluster;
  65 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
  66         uint rcw_tmp;
  67 #endif
  68         uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
  69         uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
  70         unsigned long sysclk = get_board_sys_clk();
  71         int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
  72         u32 c_pll_sel, cplx_pll;
  73         void *offset;
  74
  75         sys_info->freq_systembus = sysclk;
  76 #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || defined(CONFIG_STATIC_DDR_CLK_FREQ)
  77         sys_info->freq_ddrbus = get_board_ddr_clk();
  78 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  79         sys_info->freq_ddrbus2 = get_board_ddr_clk();
  80 #endif
  81 #else
  82         sys_info->freq_ddrbus = sysclk;
  83 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  84         sys_info->freq_ddrbus2 = sysclk;
  85 #endif
  86 #endif
  87
  88         /* The freq_systembus is used to record frequency of platform PLL */
  89         sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
  90                         FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT) &
  91                         FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK;
  92         sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
  93                         FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
  94                         FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
  95 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  96         if (soc_has_dp_ddr()) {
  97                 sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
  98                         FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
  99                         FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
 100         } else {
 101                 sys_info->freq_ddrbus2 = 0;
 102         }
 103 #endif
 104
 105         for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
 106                 /*
 107                  * fixme: prefer to combine the following into one line, but
 108                  * cannot pass compiling without warning about in_le32.
 109                  */
 110                 offset = (void *)((size_t)clk_grp[i/3] +
 111                          offsetof(struct ccsr_clk_cluster_group,
 112                                   pllngsr[i%3].gsr));
 113                 ratio[i] = (in_le32(offset) >> 1) & 0x3f;
 114                 freq_c_pll[i] = sysclk * ratio[i];
 115         }
 116
 117         for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
 118                 cluster = fsl_qoriq_core_to_cluster(cpu);
 119                 c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27)
 120                             & 0xf;
 121                 cplx_pll = core_cplx_pll[c_pll_sel];
 122                 cplx_pll += cc_group[cluster] - 1;
 123                 sys_info->freq_processor[cpu] =
 124                         freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 125         }
 126
 127 #if defined(CONFIG_FSL_IFC)
 128         sys_info->freq_localbus = sys_info->freq_systembus /
 129                                                 CONFIG_SYS_FSL_IFC_CLK_DIV;
 130 #endif
 131
 132 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
 133 #define HWA_CGA_M2_CLK_SEL      0x00380000
 134 #define HWA_CGA_M2_CLK_SHIFT    19
 135         rcw_tmp = in_le32(&gur->rcwsr[5]);
 136         switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
 137         case 1:
 138                 sys_info->freq_cga_m2 = freq_c_pll[1];
 139                 break;
 140         case 2:
 141                 sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
 142                 break;
 143         case 3:
 144                 sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
 145                 break;
 146         case 4:
 147                 sys_info->freq_cga_m2 = freq_c_pll[1] / 4;
 148                 break;
 149         case 6:
 150                 sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
 151                 break;
 152         case 7:
 153                 sys_info->freq_cga_m2 = freq_c_pll[0] / 3;
 154                 break;
 155         default:
 156                 printf("Error: Unknown peripheral clock select!\n");
 157                 break;
 158         }
 159 #endif
 160 }
 161
 162 int get_clocks(void)
 163 {
 164         struct sys_info sys_info;
 165 #ifdef CONFIG_FSL_ESDHC
 166         u32 clock = 0;
 167 #endif
 168         get_sys_info(&sys_info);
 169         gd->cpu_clk = sys_info.freq_processor[0];
 170         gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
 171         gd->mem_clk = sys_info.freq_ddrbus;
 172 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 173         gd->arch.mem2_clk = sys_info.freq_ddrbus2;
 174 #endif
 175
 176 #ifdef CONFIG_FSL_ESDHC
 177 #if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
 178         clock = sys_info.freq_cga_m2;
 179 #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2162A)
 180         clock = sys_info.freq_systembus;
 181 #endif
 182         gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
 183         gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
 184 #endif
 185
 186         if (gd->cpu_clk != 0)
 187                 return 0;
 188         else
 189                 return 1;
 190 }
 191
 192 /********************************************
 193  * get_bus_freq
 194  * return platform clock in Hz
 195  *********************************************/
 196 ulong get_bus_freq(ulong dummy)
 197 {
 198         if (!gd->bus_clk)
 199                 get_clocks();
 200
 201         return gd->bus_clk;
 202 }
 203
 204 /********************************************
 205  * get_ddr_freq
 206  * return ddr bus freq in Hz
 207  *********************************************/
 208 ulong get_ddr_freq(ulong ctrl_num)
 209 {
 210         if (!gd->mem_clk)
 211                 get_clocks();
 212
 213         /*
 214          * DDR controller 0 & 1 are on memory complex 0
 215          * DDR controller 2 is on memory complext 1
 216          */
 217 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 218         if (ctrl_num >= 2)
 219                 return gd->arch.mem2_clk;
 220 #endif
 221
 222         return gd->mem_clk;
 223 }
 224
 225 int get_i2c_freq(ulong dummy)
 226 {
 227         return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
 228 }
 229
 230 int get_dspi_freq(ulong dummy)
 231 {
 232         return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
 233 }
 234
 235 int get_serial_clock(void)
 236 {
 237         return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
 238 }
 239
 240 unsigned int mxc_get_clock(enum mxc_clock clk)
 241 {
 242         switch (clk) {
 243         case MXC_I2C_CLK:
 244                 return get_i2c_freq(0);
 245         case MXC_DSPI_CLK:
 246                 return get_dspi_freq(0);
 247         default:
 248                 printf("Unsupported clock\n");
 249         }
 250         return 0;
 251 }