4 select ARM_ERRATA_855873 if !TFABOOT
11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
16 select ARCH_EARLY_INIT_R
17 select BOARD_EARLY_INIT_F
19 select SYS_I2C_MXC_I2C1 if !DM_I2C
20 select SYS_I2C_MXC_I2C2 if !DM_I2C
25 select ARMV8_SET_SMPEN
29 select SYS_FSL_HAS_CCI400
34 select SYS_FSL_DDR_VER_50
35 select SYS_FSL_HAS_DDR3
36 select SYS_FSL_HAS_DDR4
37 select SYS_FSL_HAS_SEC
38 select SYS_FSL_SEC_COMPAT_5
41 select ARCH_EARLY_INIT_R
42 select BOARD_EARLY_INIT_F
44 select SYS_FSL_ERRATUM_A008997
45 select SYS_FSL_ERRATUM_A009007
46 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
47 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
48 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
49 select SYS_FSL_ERRATUM_A050382
50 select SYS_FSL_ERRATUM_A011334
51 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
52 select RESV_RAM if GIC_V3_ITS
57 select ARMV8_SET_SMPEN
58 select ARM_ERRATA_855873 if !TFABOOT
61 select HAS_FSL_XHCI_USB if USB_HOST
66 select SYS_FSL_DDR_VER_50
67 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
68 select SYS_FSL_ERRATUM_A008997
69 select SYS_FSL_ERRATUM_A009007
70 select SYS_FSL_ERRATUM_A009008
71 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
72 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
73 select SYS_FSL_ERRATUM_A009798
74 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
75 select SYS_FSL_ERRATUM_A010315
76 select SYS_FSL_ERRATUM_A010539
77 select SYS_FSL_HAS_DDR3
78 select SYS_FSL_HAS_DDR4
79 select ARCH_EARLY_INIT_R
80 select BOARD_EARLY_INIT_F
82 select SYS_I2C_MXC_I2C1 if !DM_I2C
83 select SYS_I2C_MXC_I2C2 if !DM_I2C
84 select SYS_I2C_MXC_I2C3 if !DM_I2C
85 select SYS_I2C_MXC_I2C4 if !DM_I2C
91 select ARMV8_SET_SMPEN
94 select HAS_FSL_XHCI_USB if USB_HOST
99 select SYS_FSL_DDR_VER_50
100 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
101 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
102 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
103 select SYS_FSL_ERRATUM_A008997
104 select SYS_FSL_ERRATUM_A009007
105 select SYS_FSL_ERRATUM_A009008
106 select SYS_FSL_ERRATUM_A009798
107 select SYS_FSL_ERRATUM_A009801
108 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
109 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
110 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
111 select SYS_FSL_ERRATUM_A010539
112 select SYS_FSL_HAS_DDR4
113 select SYS_FSL_SRDS_2
114 select ARCH_EARLY_INIT_R
115 select BOARD_EARLY_INIT_F
117 select SYS_I2C_MXC_I2C1 if !DM_I2C
118 select SYS_I2C_MXC_I2C2 if !DM_I2C
119 select SYS_I2C_MXC_I2C3 if !DM_I2C
120 select SYS_I2C_MXC_I2C4 if !DM_I2C
124 imply SPL_SYS_I2C_LEGACY
128 select ARMV8_SET_SMPEN
129 select ARM_ERRATA_855873 if !TFABOOT
130 select FSL_LAYERSCAPE
132 select SYS_FSL_SRDS_1
133 select SYS_HAS_SERDES
135 select SYS_FSL_DDR_LE
136 select SYS_FSL_DDR_VER_50
139 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
140 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
141 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
142 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
143 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
144 select SYS_FSL_ERRATUM_A009007
145 select SYS_FSL_HAS_CCI400
146 select SYS_FSL_HAS_DDR4
147 select SYS_FSL_HAS_RGMII
148 select SYS_FSL_HAS_SEC
149 select SYS_FSL_SEC_COMPAT_5
150 select SYS_FSL_SEC_LE
151 select SYS_FSL_SRDS_1
152 select SYS_FSL_SRDS_2
155 select FSL_TZPC_BP147
156 select ARCH_EARLY_INIT_R
157 select BOARD_EARLY_INIT_F
159 select SYS_I2C_MXC_I2C1 if !TFABOOT
160 select SYS_I2C_MXC_I2C2 if !TFABOOT
161 select SYS_I2C_MXC_I2C3 if !TFABOOT
162 select SYS_I2C_MXC_I2C4 if !TFABOOT
163 select RESV_RAM if GIC_V3_ITS
166 imply SPL_SYS_I2C_LEGACY
171 select ARMV8_SET_SMPEN
172 select ARM_ERRATA_826974
173 select ARM_ERRATA_828024
174 select ARM_ERRATA_829520
175 select ARM_ERRATA_833471
176 select FSL_LAYERSCAPE
178 select SYS_FSL_SRDS_1
179 select SYS_HAS_SERDES
181 select SYS_FSL_DDR_LE
182 select SYS_FSL_DDR_VER_50
183 select SYS_FSL_HAS_CCN504
184 select SYS_FSL_HAS_DP_DDR
185 select SYS_FSL_HAS_SEC
186 select SYS_FSL_HAS_DDR4
187 select SYS_FSL_SEC_COMPAT_5
188 select SYS_FSL_SEC_LE
189 select SYS_FSL_SRDS_2
193 select FSL_TZPC_BP147
194 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
195 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
196 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
197 select SYS_FSL_ERRATUM_A008585
198 select SYS_FSL_ERRATUM_A008997
199 select SYS_FSL_ERRATUM_A009007
200 select SYS_FSL_ERRATUM_A009008
201 select SYS_FSL_ERRATUM_A009635
202 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
203 select SYS_FSL_ERRATUM_A009798
204 select SYS_FSL_ERRATUM_A009801
205 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
206 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
207 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
208 select SYS_FSL_ERRATUM_A009203
209 select ARCH_EARLY_INIT_R
210 select BOARD_EARLY_INIT_F
212 select SYS_I2C_MXC_I2C1 if !TFABOOT
213 select SYS_I2C_MXC_I2C2 if !TFABOOT
214 select SYS_I2C_MXC_I2C3 if !TFABOOT
215 select SYS_I2C_MXC_I2C4 if !TFABOOT
216 select RESV_RAM if GIC_V3_ITS
217 imply DISTRO_DEFAULTS
220 imply SPL_SYS_I2C_LEGACY
224 select ARMV8_SET_SMPEN
227 select SYS_HAS_SERDES
228 select SYS_FSL_SRDS_1
229 select SYS_FSL_SRDS_2
231 select SYS_FSL_DDR_LE
232 select SYS_FSL_DDR_VER_50
235 select SYS_FSL_ERRATUM_A050204
236 select SYS_FSL_ERRATUM_A011334
237 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
238 select SYS_FSL_HAS_RGMII
239 select SYS_FSL_HAS_SEC
240 select SYS_FSL_HAS_CCN508
241 select SYS_FSL_HAS_DDR4
242 select SYS_FSL_SEC_COMPAT_5
243 select SYS_FSL_SEC_LE
244 select ARCH_EARLY_INIT_R
245 select BOARD_EARLY_INIT_F
247 select RESV_RAM if GIC_V3_ITS
248 imply DISTRO_DEFAULTS
252 imply SPL_SYS_I2C_LEGACY
256 select ARMV8_SET_SMPEN
258 select HAS_FSL_XHCI_USB if USB_HOST
260 select SYS_HAS_SERDES
261 select SYS_FSL_SRDS_1
262 select SYS_FSL_SRDS_2
263 select SYS_NXP_SRDS_3
265 select SYS_FSL_DDR_LE
266 select SYS_FSL_DDR_VER_50
269 select SYS_FSL_ERRATUM_A050204
270 select SYS_FSL_ERRATUM_A011334
271 select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
272 select SYS_FSL_HAS_RGMII
273 select SYS_FSL_HAS_SEC
274 select SYS_FSL_HAS_CCN508
275 select SYS_FSL_HAS_DDR4
276 select SYS_FSL_SEC_COMPAT_5
277 select SYS_FSL_SEC_LE
278 select ARCH_EARLY_INIT_R
279 select BOARD_EARLY_INIT_F
281 select RESV_RAM if GIC_V3_ITS
282 imply DISTRO_DEFAULTS
287 imply SPL_SYS_I2C_LEGACY
291 select SYS_FSL_HAS_CCI400
292 select SYS_FSL_HAS_SEC
293 select SYS_FSL_SEC_COMPAT_5
294 select SYS_FSL_SEC_BE
297 select ARCH_MISC_INIT
303 menu "Layerscape architecture"
304 depends on FSL_LSCH2 || FSL_LSCH3
306 config FSL_LAYERSCAPE
309 config HAS_FEATURE_GIC64K_ALIGN
311 default y if ARCH_LS1043A
313 config HAS_FEATURE_ENHANCED_MSI
315 default y if ARCH_LS1043A
317 menu "Layerscape PPA"
319 bool "FSL Layerscape PPA firmware support"
320 depends on !ARMV8_PSCI
321 select ARMV8_SEC_FIRMWARE_SUPPORT
322 select SEC_FIRMWARE_ARMV8_PSCI
323 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
325 The FSL Primary Protected Application (PPA) is a software component
326 which is loaded during boot stage, and then remains resident in RAM
327 and runs in the TrustZone after boot.
330 config SPL_FSL_LS_PPA
331 bool "FSL Layerscape PPA firmware support for SPL build"
332 depends on !ARMV8_PSCI
333 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
334 select SEC_FIRMWARE_ARMV8_PSCI
335 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
337 The FSL Primary Protected Application (PPA) is a software component
338 which is loaded during boot stage, and then remains resident in RAM
339 and runs in the TrustZone after boot. This is to load PPA during SPL
340 stage instead of the RAM version of U-Boot. Once PPA is initialized,
341 the rest of U-Boot (including RAM version) runs at EL2.
343 prompt "FSL Layerscape PPA firmware loading-media select"
344 depends on FSL_LS_PPA
345 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
346 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
347 default SYS_LS_PPA_FW_IN_XIP
349 config SYS_LS_PPA_FW_IN_XIP
352 Say Y here if the PPA firmware locate at XIP flash, such
353 as NOR or QSPI flash.
355 config SYS_LS_PPA_FW_IN_MMC
356 bool "eMMC or SD Card"
358 Say Y here if the PPA firmware locate at eMMC/SD card.
360 config SYS_LS_PPA_FW_IN_NAND
363 Say Y here if the PPA firmware locate at NAND flash.
367 config LS_PPA_ESBC_HDR_SIZE
368 hex "Length of PPA ESBC header"
369 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
372 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
373 NAND to memory to validate PPA image.
377 config SYS_FSL_ERRATUM_A008997
378 bool "Workaround for USB PHY erratum A008997"
380 config SYS_FSL_ERRATUM_A009007
383 Workaround for USB PHY erratum A009007
385 config SYS_FSL_ERRATUM_A009008
386 bool "Workaround for USB PHY erratum A009008"
388 config SYS_FSL_ERRATUM_A009798
389 bool "Workaround for USB PHY erratum A009798"
391 config SYS_FSL_ERRATUM_A050204
392 bool "Workaround for USB PHY erratum A050204"
394 USB3.0 Receiver needs to enable fixed equalization
395 for each of PHY instances in an SOC. This is similar
396 to erratum A-009007, but this one is for LX2160A and LX2162A,
397 and the register value is different.
399 config SYS_FSL_ERRATUM_A010315
400 bool "Workaround for PCIe erratum A010315"
402 config SYS_FSL_ERRATUM_A010539
403 bool "Workaround for PIN MUX erratum A010539"
406 int "Maximum number of CPUs permitted for Layerscape"
407 default 2 if ARCH_LS1028A
408 default 4 if ARCH_LS1043A
409 default 4 if ARCH_LS1046A
410 default 16 if ARCH_LS2080A
411 default 8 if ARCH_LS1088A
412 default 16 if ARCH_LX2160A
413 default 16 if ARCH_LX2162A
416 Set this number to the maximum number of possible CPUs in the SoC.
417 SoCs may have multiple clusters with each cluster may have multiple
418 ports. If some ports are reserved but higher ports are used for
419 cores, count the reserved ports. This will allocate enough memory
420 in spin table to properly handle all cores.
423 bool "Fan controller"
425 Enable the EMC2305 fan controller for configuration of fan
431 Enable Freescale Secure Boot feature
434 bool "Init the QSPI AHB bus"
436 The default setting for QSPI AHB bus just support 3bytes addressing.
437 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
438 bus for those flashes to support the full QSPI flash size.
440 config FSPI_AHB_EN_4BYTE
441 bool "Enable 4-byte Fast Read command for AHB mode"
444 The default setting for FlexSPI AHB bus just supports 3-byte addressing.
445 But some FlexSPI flash sizes are up to 64MBytes.
446 This flag enables fast read command for AHB mode and modifies required
447 LUT to support full FlexSPI flash.
449 config SYS_CCI400_OFFSET
450 hex "Offset for CCI400 base"
451 depends on SYS_FSL_HAS_CCI400
452 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
453 default 0x180000 if FSL_LSCH2
455 Offset for CCI400 base
456 CCI400 base addr = CCSRBAR + CCI400_OFFSET
458 config SYS_FSL_IFC_BANK_COUNT
459 int "Maximum banks of Integrated flash controller"
460 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
461 default 4 if ARCH_LS1043A
462 default 4 if ARCH_LS1046A
463 default 8 if ARCH_LS2080A || ARCH_LS1088A
465 config SYS_FSL_HAS_CCI400
468 config SYS_FSL_HAS_CCN504
471 config SYS_FSL_HAS_CCN508
474 config SYS_FSL_HAS_DP_DDR
477 config SYS_FSL_SRDS_1
480 config SYS_FSL_SRDS_2
483 config SYS_NXP_SRDS_3
486 config SYS_HAS_SERDES
498 config FSL_TZPC_BP147
502 menu "Layerscape clock tree configuration"
503 depends on FSL_LSCH2 || FSL_LSCH3
506 bool "Enable clock tree initialization"
509 config CLUSTER_CLK_FREQ
510 int "Reference clock of core cluster"
511 depends on ARCH_LS1012A
514 This number is the reference clock frequency of core PLL.
515 For most platforms, the core PLL and Platform PLL have the same
516 reference clock, but for some platforms, LS1012A for instance,
517 they are provided sepatately.
519 config SYS_FSL_PCLK_DIV
520 int "Platform clock divider"
521 default 1 if ARCH_LS1028A
522 default 1 if ARCH_LS1043A
523 default 1 if ARCH_LS1046A
524 default 1 if ARCH_LS1088A
527 This is the divider that is used to derive Platform clock from
528 Platform PLL, in another word:
529 Platform_clk = Platform_PLL_freq / this_divider
531 config SYS_FSL_DSPI_CLK_DIV
532 int "DSPI clock divider"
533 default 1 if ARCH_LS1043A
536 This is the divider that is used to derive DSPI clock from Platform
537 clock, in another word DSPI_clk = Platform_clk / this_divider.
539 config SYS_FSL_DUART_CLK_DIV
540 int "DUART clock divider"
541 default 1 if ARCH_LS1043A
542 default 4 if ARCH_LX2160A
543 default 4 if ARCH_LX2162A
546 This is the divider that is used to derive DUART clock from Platform
547 clock, in another word DUART_clk = Platform_clk / this_divider.
549 config SYS_FSL_I2C_CLK_DIV
550 int "I2C clock divider"
551 default 1 if ARCH_LS1043A
552 default 4 if ARCH_LS1012A
553 default 4 if ARCH_LS1028A
554 default 8 if ARCH_LX2160A
555 default 8 if ARCH_LX2162A
556 default 8 if ARCH_LS1088A
559 This is the divider that is used to derive I2C clock from Platform
560 clock, in another word I2C_clk = Platform_clk / this_divider.
562 config SYS_FSL_IFC_CLK_DIV
563 int "IFC clock divider"
564 default 1 if ARCH_LS1043A
565 default 4 if ARCH_LS1012A
566 default 4 if ARCH_LS1028A
567 default 8 if ARCH_LX2160A
568 default 8 if ARCH_LX2162A
569 default 8 if ARCH_LS1088A
572 This is the divider that is used to derive IFC clock from Platform
573 clock, in another word IFC_clk = Platform_clk / this_divider.
575 config SYS_FSL_LPUART_CLK_DIV
576 int "LPUART clock divider"
577 default 1 if ARCH_LS1043A
580 This is the divider that is used to derive LPUART clock from Platform
581 clock, in another word LPUART_clk = Platform_clk / this_divider.
583 config SYS_FSL_SDHC_CLK_DIV
584 int "SDHC clock divider"
585 default 1 if ARCH_LS1043A
586 default 1 if ARCH_LS1012A
589 This is the divider that is used to derive SDHC clock from Platform
590 clock, in another word SDHC_clk = Platform_clk / this_divider.
592 config SYS_FSL_QMAN_CLK_DIV
593 int "QMAN clock divider"
594 default 1 if ARCH_LS1043A
597 This is the divider that is used to derive QMAN clock from Platform
598 clock, in another word QMAN_clk = Platform_clk / this_divider.
604 Reserve memory from the top, tracked by gd->arch.resv_ram. This
605 reserved RAM can be used by special driver that resides in memory
606 after U-Boot exits. It's up to implementation to allocate and allow
607 access to this reserved memory. For example, the reserved RAM can
608 be at the high end of physical memory. The reserve RAM may be
609 excluded from memory bank(s) passed to OS, or marked as reserved.
614 Ethernet controller 1, this is connected to
615 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
616 Provides DPAA2 capabilities
621 Ethernet controller 2, this is connected to
622 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
623 Provides DPAA2 capabilities
625 config SYS_FSL_ERRATUM_A008336
628 config SYS_FSL_ERRATUM_A008514
631 config SYS_FSL_ERRATUM_A008585
634 config SYS_FSL_ERRATUM_A008850
637 config SYS_FSL_ERRATUM_A009203
640 config SYS_FSL_ERRATUM_A009635
643 config SYS_FSL_ERRATUM_A009660
646 config SYS_FSL_ERRATUM_A050382
649 config SYS_FSL_HAS_RGMII
651 depends on SYS_FSL_EC1 || SYS_FSL_EC2
654 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
656 config HAS_FSL_XHCI_USB
659 For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
660 pins, select it when the pins are assigned to USB.
662 config SYS_FSL_BOOTROM_BASE
667 config SYS_FSL_BOOTROM_SIZE