arch/arm/cpu/armv7/ls102xa/fdt.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <net.h>
   9 #include <asm/global_data.h>
  10 #include <linux/libfdt.h>
  11 #include <fdt_support.h>
  12 #include <asm/io.h>
  13 #include <asm/processor.h>
  14 #include <asm/arch/clock.h>
  15 #include <linux/ctype.h>
  16 #ifdef CONFIG_FSL_ESDHC
  17 #include <fsl_esdhc.h>
  18 #endif
  19 #include <tsec.h>
  20 #include <asm/arch/immap_ls102xa.h>
  21 #include <fsl_sec.h>
  22 #include <dm.h>
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 void ft_fixup_enet_phy_connect_type(void *fdt)
  27 {
  28 #ifdef CONFIG_DM_ETH
  29         struct udevice *dev;
  30 #else
  31         struct eth_device *dev;
  32 #endif
  33         struct tsec_private *priv;
  34         const char *enet_path, *phy_path;
  35         char enet[16];
  36         char phy[16];
  37         int phy_node;
  38         int i = 0;
  39         uint32_t ph;
  40 #ifdef CONFIG_DM_ETH
  41         char *name[3] = { "ethernet@2d10000", "ethernet@2d50000",
  42                           "ethernet@2d90000" };
  43 #else
  44         char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
  45 #endif
  46
  47         for (; i < ARRAY_SIZE(name); i++) {
  48                 dev = eth_get_dev_by_name(name[i]);
  49                 if (dev) {
  50                         sprintf(enet, "ethernet%d", i);
  51                         sprintf(phy, "enet%d_rgmii_phy", i);
  52                 } else {
  53                         continue;
  54                 }
  55
  56 #ifdef CONFIG_DM_ETH
  57                 priv = dev_get_priv(dev);
  58 #else
  59                 priv = dev->priv;
  60 #endif
  61                 if (priv->flags & TSEC_SGMII)
  62                         continue;
  63
  64                 enet_path = fdt_get_alias(fdt, enet);
  65                 if (!enet_path)
  66                         continue;
  67
  68                 phy_path = fdt_get_alias(fdt, phy);
  69                 if (!phy_path)
  70                         continue;
  71
  72                 phy_node = fdt_path_offset(fdt, phy_path);
  73                 if (phy_node < 0)
  74                         continue;
  75
  76                 ph = fdt_create_phandle(fdt, phy_node);
  77                 if (ph)
  78                         do_fixup_by_path_u32(fdt, enet_path,
  79                                              "phy-handle", ph, 1);
  80
  81                 do_fixup_by_path(fdt, enet_path, "phy-connection-type",
  82                                  phy_string_for_interface(
  83                                  PHY_INTERFACE_MODE_RGMII_ID),
  84                                  strlen(phy_string_for_interface(
  85                                  PHY_INTERFACE_MODE_RGMII_ID)) + 1,
  86                                  1);
  87         }
  88 }
  89
  90 void ft_cpu_setup(void *blob, struct bd_info *bd)
  91 {
  92         int off;
  93         int val;
  94         const char *sysclk_path;
  95         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  96         unsigned int svr;
  97         svr = in_be32(&gur->svr);
  98
  99         unsigned long busclk = get_bus_freq(0);
 100
 101         /* delete crypto node if not on an E-processor */
 102         if (!IS_E_PROCESSOR(svr))
 103                 fdt_fixup_crypto_node(blob, 0);
 104 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
 105         else {
 106                 ccsr_sec_t __iomem *sec;
 107
 108                 sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
 109                 fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
 110         }
 111 #endif
 112
 113         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 114         while (off != -FDT_ERR_NOTFOUND) {
 115                 val = gd->cpu_clk;
 116                 fdt_setprop(blob, off, "clock-frequency", &val, 4);
 117                 off = fdt_node_offset_by_prop_value(blob, off,
 118                                                     "device_type", "cpu", 4);
 119         }
 120
 121         do_fixup_by_prop_u32(blob, "device_type", "soc",
 122                              4, "bus-frequency", busclk, 1);
 123
 124         ft_fixup_enet_phy_connect_type(blob);
 125
 126 #ifdef CONFIG_SYS_NS16550
 127         do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
 128                                "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 129 #endif
 130
 131         sysclk_path = fdt_get_alias(blob, "sysclk");
 132         if (sysclk_path)
 133                 do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
 134                                      get_board_sys_clk(), 1);
 135         do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
 136                                "clock-frequency", get_board_sys_clk(), 1);
 137
 138 #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
 139 #define UBOOT_HEAD_LEN  0x1000
 140         /*
 141          * Reserved memory in SD boot deep sleep case.
 142          * Second stage uboot binary and malloc space should be reserved.
 143          * If the memory they occupied has not been reserved, then this
 144          * space would be used by kernel and overwritten in uboot when
 145          * deep sleep resume, which cause deep sleep failed.
 146          * Since second uboot binary has a head, that space need to be
 147          * reserved either(assuming its size is less than 0x1000).
 148          */
 149         off = fdt_add_mem_rsv(blob, CONFIG_TEXT_BASE - UBOOT_HEAD_LEN,
 150                               CONFIG_SYS_MONITOR_LEN +
 151                               CONFIG_SYS_SPL_MALLOC_SIZE + UBOOT_HEAD_LEN);
 152         if (off < 0)
 153                 printf("Failed to reserve memory for SD boot deep sleep: %s\n",
 154                        fdt_strerror(off));
 155 #endif
 156
 157 #if defined(CONFIG_FSL_ESDHC)
 158         fdt_fixup_esdhc(blob, bd);
 159 #endif
 160
 161         /*
 162          * platform bus clock = system bus clock/2
 163          * Here busclk = system bus clock
 164          * We are using the platform bus clock as 1588 Timer reference
 165          * clock source select
 166          */
 167         do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
 168                                "timer-frequency", busclk / 2, 1);
 169
 170         /*
 171          * clock-freq should change to clock-frequency and
 172          * flexcan-v1.0 should change to p1010-flexcan respectively
 173          * in the future.
 174          */
 175         do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
 176                                "clock_freq", busclk / 2, 1);
 177
 178         do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
 179                                "clock-frequency", busclk / 2, 1);
 180
 181         do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
 182                                "clock-frequency", busclk / 2, 1);
 183
 184 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 185         off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
 186                                             CONFIG_SYS_IFC_ADDR);
 187         fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
 188 #else
 189         off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
 190                                             QSPI0_BASE_ADDR);
 191         fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
 192         off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
 193                                             DSPI1_BASE_ADDR);
 194         fdt_set_node_status(blob, off, FDT_STATUS_DISABLED);
 195 #endif
 196 }