1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
11 imply SPL_SEPARATE_BSS
14 bool "Enable support for CRC32 instruction"
18 ARMv8 implements dedicated crc32 instruction for crc32 calculation.
19 This is faster than software crc32 calculation. This instruction may
20 not be present on all ARMv8.0, but is always present on ARMv8.1 and
23 config COUNTER_FREQUENCY
24 int "Timer clock frequency"
25 depends on ARM64 || CPU_V7A
26 default 8000000 if IMX8 || MX7 || MX6UL || MX6ULL
27 default 24000000 if ARCH_SUNXI || ARCH_EXYNOS || ROCKCHIP_RK3128 || \
28 ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
29 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
30 default 100000000 if ARCH_ZYNQMP
33 For platforms with ARMv8-A and ARMv7-A which features a system
34 counter, those platforms needs software to program the counter
35 frequency. Setup time clock frequency for certain platform.
36 0 means no need to configure the system counter frequency.
37 For platforms needs the frequency set in U-Boot with a
38 pre-defined value, should have the macro defined as a non-zero value.
40 config POSITION_INDEPENDENT
41 bool "Generate position-independent pre-relocation code"
42 depends on ARM64 || CPU_V7A
44 U-Boot expects to be linked to a specific hard-coded address, and to
45 be loaded to and run from that address. This option lifts that
46 restriction, thus allowing the code to be loaded to and executed from
47 almost any 4K aligned address. This logic relies on the relocation
48 information that is embedded in the binary to support U-Boot
49 relocating itself to the top-of-RAM later during execution.
51 config INIT_SP_RELATIVE
52 bool "Specify the early stack pointer relative to the .bss section"
54 default n if ARCH_QEMU
55 default y if POSITION_INDEPENDENT
57 U-Boot typically uses a hard-coded value for the stack pointer
58 before relocation. Enable this option to instead calculate the
59 initial SP at run-time. This is useful to avoid hard-coding addresses
60 into U-Boot, so that it can be loaded and executed at arbitrary
61 addresses and thus avoid using arbitrary addresses at runtime.
63 If this option is enabled, the early stack pointer is set to
64 &_bss_start with a offset value added. The offset is specified by
65 SYS_INIT_SP_BSS_OFFSET.
67 config SYS_INIT_SP_BSS_OFFSET
68 int "Early stack offset from the .bss base address"
70 depends on INIT_SP_RELATIVE
73 This option's value is the offset added to &_bss_start in order to
74 calculate the stack pointer. This offset should be large enough so
75 that the early malloc region, global data (gd), and early stack usage
76 do not overlap any appended DTB.
78 config SPL_SYS_NO_VECTOR_TABLE
82 config LINUX_KERNEL_IMAGE_HEADER
86 Place a Linux kernel image header at the start of the U-Boot binary.
87 The format of the header is described in the Linux kernel source at
88 Documentation/arm64/booting.txt. This feature is useful since the
89 image header reports the amount of memory (BSS and similar) that
90 U-Boot needs to use, but which isn't part of the binary.
92 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
93 depends on LINUX_KERNEL_IMAGE_HEADER
96 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
97 TEXT_OFFSET value written to the Linux kernel image header.
109 ARM GICV3 Interrupt translation service (ITS).
110 Basic support for programming locality specific peripheral
111 interrupts (LPI) configuration tables and enable LPI tables.
112 LPI configuration table can be used by u-boot or Linux.
113 ARM GICV3 has limitation, once the LPI table is enabled, LPI
114 configuration table can not be re-programmed, unless GICV3 reset.
120 config DMA_ADDR_T_64BIT
130 config GPIO_EXTRA_HEADER
133 # Used for compatibility with asm files copied from the kernel
134 config ARM_ASM_UNIFIED
138 # Used for compatibility with asm files copied from the kernel
142 config SYS_ICACHE_OFF
143 bool "Do not enable icache"
145 Do not enable instruction cache in U-Boot.
147 config SPL_SYS_ICACHE_OFF
148 bool "Do not enable icache in SPL"
150 default SYS_ICACHE_OFF
152 Do not enable instruction cache in SPL.
154 config SYS_DCACHE_OFF
155 bool "Do not enable dcache"
157 Do not enable data cache in U-Boot.
159 config SPL_SYS_DCACHE_OFF
160 bool "Do not enable dcache in SPL"
162 default SYS_DCACHE_OFF
164 Do not enable data cache in SPL.
166 config SYS_ARM_CACHE_CP15
167 bool "CP15 based cache enabling support"
169 Select this if your processor suports enabling caches by using
173 bool "MMU-based Paged Memory Management Support"
174 select SYS_ARM_CACHE_CP15
176 Select if you want MMU-based virtualised addressing space
177 support via paged memory management.
180 bool 'Use the ARM v7 PMSA Compliant MPU'
182 Some ARM systems without an MMU have instead a Memory Protection
183 Unit (MPU) that defines the type and permissions for regions of
185 If your CPU has an MPU then you should choose 'y' here unless you
186 know that you do not want to use the MPU.
188 # If set, the workarounds for these ARM errata are applied early during U-Boot
189 # startup. Note that in general these options force the workarounds to be
190 # applied; no CPU-type/version detection exists, unlike the similar options in
191 # the Linux kernel. Do not set these options unless they apply! Also note that
192 # the following can be machine-specific errata. These do have ability to
193 # provide rudimentary version and machine-specific checks, but expect no
195 # CONFIG_ARM_ERRATA_430973
196 # CONFIG_ARM_ERRATA_454179
197 # CONFIG_ARM_ERRATA_621766
198 # CONFIG_ARM_ERRATA_798870
199 # CONFIG_ARM_ERRATA_801819
200 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
201 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
203 config ARM_ERRATA_430973
206 config ARM_ERRATA_454179
209 config ARM_ERRATA_621766
212 config ARM_ERRATA_716044
215 config ARM_ERRATA_725233
218 config ARM_ERRATA_742230
221 config ARM_ERRATA_743622
224 config ARM_ERRATA_751472
227 config ARM_ERRATA_761320
230 config ARM_ERRATA_773022
233 config ARM_ERRATA_774769
236 config ARM_ERRATA_794072
239 config ARM_ERRATA_798870
242 config ARM_ERRATA_801819
245 config ARM_ERRATA_826974
248 config ARM_ERRATA_828024
251 config ARM_ERRATA_829520
254 config ARM_ERRATA_833069
257 config ARM_ERRATA_833471
260 config ARM_ERRATA_845369
263 config ARM_ERRATA_852421
266 config ARM_ERRATA_852423
269 config ARM_ERRATA_855873
272 config ARM_CORTEX_A8_CVE_2017_5715
275 config ARM_CORTEX_A15_CVE_2017_5715
280 select SYS_CACHE_SHIFT_5
285 select SYS_CACHE_SHIFT_5
290 select SYS_CACHE_SHIFT_5
292 imply SPL_SEPARATE_BSS
296 select SYS_CACHE_SHIFT_5
301 select SYS_CACHE_SHIFT_5
303 imply SPL_SEPARATE_BSS
308 select SYS_CACHE_SHIFT_5
315 select SYS_CACHE_SHIFT_6
322 select SYS_CACHE_SHIFT_5
323 select SYS_THUMB_BUILD
329 select SYS_ARM_CACHE_CP15
331 select SYS_CACHE_SHIFT_6
335 select SYS_CACHE_SHIFT_5
344 select SYS_CACHE_SHIFT_5
348 default "arm720t" if CPU_ARM720T
349 default "arm920t" if CPU_ARM920T
350 default "arm926ejs" if CPU_ARM926EJS
351 default "arm946es" if CPU_ARM946ES
352 default "arm1136" if CPU_ARM1136
353 default "arm1176" if CPU_ARM1176
354 default "armv7" if CPU_V7A
355 default "armv7" if CPU_V7R
356 default "armv7m" if CPU_V7M
357 default "pxa" if CPU_PXA
358 default "sa1100" if CPU_SA1100
359 default "armv8" if ARM64
363 default 4 if CPU_ARM720T
364 default 4 if CPU_ARM920T
365 default 5 if CPU_ARM926EJS
366 default 5 if CPU_ARM946ES
367 default 6 if CPU_ARM1136
368 default 6 if CPU_ARM1176
373 default 4 if CPU_SA1100
377 prompt "Select the ARM data write cache policy"
378 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
380 default SYS_ARM_CACHE_WRITEBACK
382 config SYS_ARM_CACHE_WRITEBACK
383 bool "Write-back (WB)"
385 A write updates the cache only and marks the cache line as dirty.
386 External memory is updated only when the line is evicted or explicitly
389 config SYS_ARM_CACHE_WRITETHROUGH
390 bool "Write-through (WT)"
392 A write updates both the cache and the external memory system.
393 This does not mark the cache line as dirty.
395 config SYS_ARM_CACHE_WRITEALLOC
396 bool "Write allocation (WA)"
398 A cache line is allocated on a write miss. This means that executing a
399 store instruction on the processor might cause a burst read to occur.
400 There is a linefill to obtain the data for the cache line, before the
404 config ARCH_VERY_EARLY_INIT
407 config SPL_ARCH_VERY_EARLY_INIT
411 bool "Enable ARCH_CPU_INIT"
413 Some architectures require a call to arch_cpu_init().
414 Say Y here to enable it
416 config SYS_ARCH_TIMER
417 bool "ARM Generic Timer support"
418 depends on CPU_V7A || ARM64
421 The ARM Generic Timer (aka arch-timer) provides an architected
422 interface to a timer source on an SoC.
423 It is mandatory for ARMv8 implementation and widely available
427 bool "Support for ARM SMC Calling Convention (SMCCC)"
428 depends on CPU_V7A || ARM64
431 Say Y here if you want to enable ARM SMC Calling Convention.
432 This should be enabled if U-Boot needs to communicate with system
433 firmware (for example, PSCI) according to SMCCC.
436 bool "Support ARM semihosting"
438 Semihosting is a method for a target to communicate with a host
439 debugger. It uses special instructions which the debugger will trap
440 on and interpret. This allows U-Boot to read/write files, print to
441 the console, and execute arbitrary commands on the host system.
443 Enabling this option will add support for reading and writing files
444 on the host system. If you don't have a debugger attached then trying
445 to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
447 config SEMIHOSTING_FALLBACK
448 bool "Recover gracefully when semihosting fails"
449 depends on SEMIHOSTING && ARM64
452 Normally, if U-Boot makes a semihosting call and no debugger is
453 attached, then it will panic due to a synchronous abort
454 exception. This config adds an exception handler which will allow
455 U-Boot to recover. Say 'y' if unsure.
457 config SPL_SEMIHOSTING
458 bool "Support ARM semihosting in SPL"
461 Semihosting is a method for a target to communicate with a host
462 debugger. It uses special instructions which the debugger will trap
463 on and interpret. This allows U-Boot to read/write files, print to
464 the console, and execute arbitrary commands on the host system.
466 Enabling this option will add support for reading and writing files
467 on the host system. If you don't have a debugger attached then trying
468 to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
470 config SPL_SEMIHOSTING_FALLBACK
471 bool "Recover gracefully when semihosting fails in SPL"
472 depends on SPL_SEMIHOSTING && ARM64
473 select ARMV8_SPL_EXCEPTION_VECTORS
476 Normally, if U-Boot makes a semihosting call and no debugger is
477 attached, then it will panic due to a synchronous abort
478 exception. This config adds an exception handler which will allow
479 U-Boot to recover. Say 'y' if unsure.
481 config SYS_THUMB_BUILD
482 bool "Build U-Boot using the Thumb instruction set"
485 Use this flag to build U-Boot using the Thumb instruction set for
486 ARM architectures. Thumb instruction set provides better code
487 density. For ARM architectures that support Thumb2 this flag will
488 result in Thumb2 code generated by GCC.
490 config SPL_SYS_THUMB_BUILD
491 bool "Build SPL using the Thumb instruction set"
492 default y if SYS_THUMB_BUILD
493 depends on !ARM64 && SPL
495 Use this flag to build SPL using the Thumb instruction set for
496 ARM architectures. Thumb instruction set provides better code
497 density. For ARM architectures that support Thumb2 this flag will
498 result in Thumb2 code generated by GCC.
500 config TPL_SYS_THUMB_BUILD
501 bool "Build TPL using the Thumb instruction set"
502 default y if SYS_THUMB_BUILD
503 depends on TPL && !ARM64
505 Use this flag to build TPL using the Thumb instruction set for
506 ARM architectures. Thumb instruction set provides better code
507 density. For ARM architectures that support Thumb2 this flag will
508 result in Thumb2 code generated by GCC.
511 config SYS_L2CACHE_OFF
514 If SoC does not support L2CACHE or one does not want to enable
515 L2CACHE, choose this option.
517 config ENABLE_ARM_SOC_BOOT0_HOOK
518 bool "prepare BOOT0 header"
520 If the SoC's BOOT0 requires a header area filled with (magic)
521 values, then choose this option, and create a file included as
522 <asm/arch/boot0.h> which contains the required assembler code.
524 config USE_ARCH_MEMCPY
525 bool "Use an assembly optimized implementation of memcpy"
527 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
529 Enable the generation of an optimized version of memcpy.
530 Such an implementation may be faster under some conditions
531 but may increase the binary size.
533 config SPL_USE_ARCH_MEMCPY
534 bool "Use an assembly optimized implementation of memcpy for SPL"
535 default y if USE_ARCH_MEMCPY
538 Enable the generation of an optimized version of memcpy.
539 Such an implementation may be faster under some conditions
540 but may increase the binary size.
542 config TPL_USE_ARCH_MEMCPY
543 bool "Use an assembly optimized implementation of memcpy for TPL"
544 default y if USE_ARCH_MEMCPY
547 Enable the generation of an optimized version of memcpy.
548 Such an implementation may be faster under some conditions
549 but may increase the binary size.
551 config USE_ARCH_MEMMOVE
552 bool "Use an assembly optimized implementation of memmove" if !ARM64
553 default USE_ARCH_MEMCPY if ARM64
556 Enable the generation of an optimized version of memmove.
557 Such an implementation may be faster under some conditions
558 but may increase the binary size.
560 config SPL_USE_ARCH_MEMMOVE
561 bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
562 default SPL_USE_ARCH_MEMCPY if ARM64
563 depends on SPL && ARM64
565 Enable the generation of an optimized version of memmove.
566 Such an implementation may be faster under some conditions
567 but may increase the binary size.
569 config TPL_USE_ARCH_MEMMOVE
570 bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
571 default TPL_USE_ARCH_MEMCPY if ARM64
572 depends on TPL && ARM64
574 Enable the generation of an optimized version of memmove.
575 Such an implementation may be faster under some conditions
576 but may increase the binary size.
578 config USE_ARCH_MEMSET
579 bool "Use an assembly optimized implementation of memset"
581 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
583 Enable the generation of an optimized version of memset.
584 Such an implementation may be faster under some conditions
585 but may increase the binary size.
587 config SPL_USE_ARCH_MEMSET
588 bool "Use an assembly optimized implementation of memset for SPL"
589 default y if USE_ARCH_MEMSET
592 Enable the generation of an optimized version of memset.
593 Such an implementation may be faster under some conditions
594 but may increase the binary size.
596 config TPL_USE_ARCH_MEMSET
597 bool "Use an assembly optimized implementation of memset for TPL"
598 default y if USE_ARCH_MEMSET
601 Enable the generation of an optimized version of memset.
602 Such an implementation may be faster under some conditions
603 but may increase the binary size.
605 config ARM64_SUPPORT_AARCH32
606 bool "ARM64 system support AArch32 execution state"
608 default y if !TARGET_THUNDERX_88XX
610 This ARM64 system supports AArch32 execution state.
613 def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
616 prompt "Target select"
621 select GPIO_EXTRA_HEADER
622 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
623 select SPL_SEPARATE_BSS if SPL
628 select GPIO_EXTRA_HEADER
629 select SPL_DM_SPI if SPL
632 Support for TI's DaVinci platform.
635 bool "Marvell Kirkwood"
636 select ARCH_MISC_INIT
637 select BOARD_EARLY_INIT_F
639 select GPIO_EXTRA_HEADER
642 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
648 select GPIO_EXTRA_HEADER
649 select SPL_DM_SPI if SPL
650 select SPL_DM_SPI_FLASH if SPL
659 select GPIO_EXTRA_HEADER
660 select SPL_SEPARATE_BSS if SPL
662 config TARGET_STV0991
663 bool "Support stv0991"
669 select GPIO_EXTRA_HEADER
676 bool "Broadcom BCM283X family"
680 select GPIO_EXTRA_HEADER
683 select SERIAL_SEARCH_ALL
688 bool "Broadcom BCM63158 family"
694 bool "Broadcom BCM6753 family"
701 bool "Broadcom BCM68360 family"
707 bool "Broadcom BCM6858 family"
713 bool "Broadcom BCM7XXX family"
716 select GPIO_EXTRA_HEADER
719 imply OF_HAS_PRIOR_STAGE
721 This enables support for Broadcom ARM-based set-top box
722 chipsets, including the 7445 family of chips.
725 bool "Broadcom broadband chip family"
729 config TARGET_VEXPRESS_CA9X4
730 bool "Support vexpress_ca9x4"
734 config TARGET_BCMCYGNUS
735 bool "Support bcmcygnus"
737 select GPIO_EXTRA_HEADER
739 imply BCM_SF2_ETH_GMAC
747 bool "Support Broadcom Northstar2"
749 select GPIO_EXTRA_HEADER
751 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
752 ARMv8 Cortex-A57 processors targeting a broad range of networking
756 bool "Support Broadcom NS3"
758 select BOARD_LATE_INIT
760 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
761 ARMv8 Cortex-A72 processors targeting a broad range of networking
765 bool "Samsung EXYNOS"
775 select GPIO_EXTRA_HEADER
776 imply SYS_THUMB_BUILD
781 bool "Samsung S5PC1XX"
787 select GPIO_EXTRA_HEADER
791 bool "Calxeda Highbank"
802 imply OF_HAS_PRIOR_STAGE
804 config ARCH_INTEGRATOR
805 bool "ARM Ltd. Integrator family"
808 select GPIO_EXTRA_HEADER
813 bool "Qualcomm IPQ40xx SoCs"
819 select GPIO_EXTRA_HEADER
832 select GPIO_EXTRA_HEADER
834 select SYS_ARCH_TIMER
835 select SYS_THUMB_BUILD
841 bool "Texas Instruments' K3 Architecture"
846 config ARCH_OMAP2PLUS
849 select GPIO_EXTRA_HEADER
850 select SPL_BOARD_INIT if SPL
851 select SPL_STACK_R if SPL
853 imply TI_SYSC if DM && OF_CONTROL
856 imply SPL_SEPARATE_BSS
860 select GPIO_EXTRA_HEADER
861 imply DISTRO_DEFAULTS
864 Support for the Meson SoC family developed by Amlogic Inc.,
865 targeted at media players and tablet computers. We currently
866 support the S905 (GXBaby) 64-bit SoC.
871 select GPIO_EXTRA_HEADER
874 select SPL_LIBCOMMON_SUPPORT if SPL
875 select SPL_LIBGENERIC_SUPPORT if SPL
876 select SPL_OF_CONTROL if SPL
879 Support for the MediaTek SoCs family developed by MediaTek Inc.
880 Please refer to doc/README.mediatek for more information.
883 bool "NXP LPC32xx platform"
888 select GPIO_EXTRA_HEADER
894 bool "NXP i.MX8 platform"
896 select SYS_FSL_HAS_SEC
897 select SYS_FSL_SEC_COMPAT_4
898 select SYS_FSL_SEC_LE
900 select GPIO_EXTRA_HEADER
903 select ENABLE_ARM_SOC_BOOT0_HOOK
907 bool "NXP i.MX8M platform"
909 select GPIO_EXTRA_HEADER
911 select SYS_FSL_HAS_SEC
912 select SYS_FSL_SEC_COMPAT_4
913 select SYS_FSL_SEC_LE
921 bool "NXP i.MX8ULP platform"
927 select GPIO_EXTRA_HEADER
932 bool "NXP i.MXRT platform"
936 select GPIO_EXTRA_HEADER
942 bool "NXP i.MX23 family"
944 select GPIO_EXTRA_HEADER
950 bool "NXP i.MX28 family"
952 select GPIO_EXTRA_HEADER
958 bool "NXP i.MX31 family"
960 select GPIO_EXTRA_HEADER
965 select BOARD_POSTCLK_INIT
967 select GPIO_EXTRA_HEADER
969 select SYS_FSL_HAS_SEC
970 select SYS_FSL_SEC_COMPAT_4
971 select SYS_FSL_SEC_LE
972 select ROM_UNIFIED_SECTIONS
974 imply SYS_THUMB_BUILD
978 select ARCH_MISC_INIT
980 select GPIO_EXTRA_HEADER
982 select SYS_FSL_HAS_SEC
983 select SYS_FSL_SEC_COMPAT_4
984 select SYS_FSL_SEC_LE
985 imply BOARD_EARLY_INIT_F
987 imply SYS_THUMB_BUILD
991 select BOARD_POSTCLK_INIT
993 select GPIO_EXTRA_HEADER
995 select SYS_FSL_HAS_SEC
996 select SYS_FSL_SEC_COMPAT_4
997 select SYS_FSL_SEC_LE
999 imply SYS_THUMB_BUILD
1000 imply SPL_SEPARATE_BSS
1003 bool "Freescale MX5"
1004 select BOARD_EARLY_INIT_F
1006 select GPIO_EXTRA_HEADER
1011 bool "Nexell S5P4418/S5P6818 SoC"
1012 select ENABLE_ARM_SOC_BOOT0_HOOK
1014 select GPIO_EXTRA_HEADER
1017 bool "Support Nuvoton SoCs"
1038 select LINUX_KERNEL_IMAGE_HEADER
1039 select OF_BOARD_SETUP
1042 select POSITION_INDEPENDENT
1048 select SYSRESET_WATCHDOG
1049 select SYSRESET_WATCHDOG_AUTO
1053 imply DISTRO_DEFAULTS
1054 imply OF_HAS_PRIOR_STAGE
1057 bool "Actions Semi OWL SoCs"
1061 select GPIO_EXTRA_HEADER
1066 select SYS_RELOC_GD_ENV_ADDR
1070 bool "QEMU Virtual Platform"
1079 imply OF_HAS_PRIOR_STAGE
1082 bool "Renesas ARM SoCs"
1085 select GPIO_EXTRA_HEADER
1086 imply BOARD_EARLY_INIT_F
1089 imply SYS_THUMB_BUILD
1090 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
1092 config ARCH_SNAPDRAGON
1093 bool "Qualcomm Snapdragon SoCs"
1098 select GPIO_EXTRA_HEADER
1107 bool "Altera SOCFPGA family"
1108 select ARCH_EARLY_INIT_R
1109 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
1110 select ARM64 if TARGET_SOCFPGA_SOC64
1111 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1115 select GPIO_EXTRA_HEADER
1116 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1118 select SPL_DM_RESET if DM_RESET
1119 select SPL_DM_SERIAL
1120 select SPL_LIBCOMMON_SUPPORT
1121 select SPL_LIBGENERIC_SUPPORT
1122 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
1123 select SPL_OF_CONTROL
1124 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
1130 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1132 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1133 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
1143 imply SPL_DM_SPI_FLASH
1144 imply SPL_LIBDISK_SUPPORT
1146 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1147 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1148 imply SPL_SPI_FLASH_SUPPORT
1153 bool "Support sunxi (Allwinner) SoCs"
1156 select CMD_MMC if MMC
1157 select CMD_USB if DISTRO_DEFAULTS && USB_HOST
1162 select DM_I2C if I2C
1163 select DM_SPI if SPI
1164 select DM_SPI_FLASH if SPI
1166 select DM_MMC if MMC
1167 select DM_SCSI if SCSI
1169 select GPIO_EXTRA_HEADER
1170 select OF_BOARD_SETUP
1174 select SPECIFY_CONSOLE_INDEX
1175 select SPL_SEPARATE_BSS if SPL
1176 select SPL_STACK_R if SPL
1177 select SPL_SYS_MALLOC_SIMPLE if SPL
1178 select SPL_SYS_THUMB_BUILD if !ARM64
1181 select SYS_THUMB_BUILD if !ARM64
1182 select USB if DISTRO_DEFAULTS
1183 select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
1184 select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
1185 select SPL_USE_TINY_PRINTF
1187 select SYS_RELOC_GD_ENV_ADDR
1188 imply BOARD_LATE_INIT
1191 imply CMD_UBI if MTD_RAW_NAND
1192 imply DISTRO_DEFAULTS
1195 imply OF_LIBFDT_OVERLAY
1196 imply PRE_CONSOLE_BUFFER
1198 imply SPL_LIBCOMMON_SUPPORT
1199 imply SPL_LIBGENERIC_SUPPORT
1200 imply SPL_MMC if MMC
1204 imply SYSRESET_WATCHDOG
1205 imply SYSRESET_WATCHDOG_AUTO
1210 bool "ST-Ericsson U8500 Series"
1214 select DM_MMC if MMC
1216 select DM_USB_GADGET if DM_USB
1220 imply AB8500_USB_PHY
1221 imply ARM_PL180_MMCI
1226 imply NOMADIK_MTU_TIMER
1231 imply SYS_THUMB_BUILD
1232 imply SYSRESET_SYSCON
1235 bool "Support Xilinx Versal Platform"
1239 select DM_ETH if NET
1240 select DM_MMC if MMC
1245 imply BOARD_LATE_INIT
1246 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1249 bool "Freescale Vybrid"
1251 select GPIO_EXTRA_HEADER
1253 select SYS_FSL_ERRATUM_ESDHC111
1258 bool "Xilinx Zynq based platform"
1262 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1264 select DM_ETH if NET
1265 select DM_MMC if MMC
1271 select SPL_BOARD_INIT if SPL
1272 select SPL_CLK if SPL
1273 select SPL_DM if SPL
1274 select SPL_DM_SPI if SPL
1275 select SPL_DM_SPI_FLASH if SPL
1276 select SPL_OF_CONTROL if SPL
1277 select SPL_SEPARATE_BSS if SPL
1279 imply ARCH_EARLY_INIT_R
1280 imply BOARD_LATE_INIT
1284 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1287 config ARCH_ZYNQMP_R5
1288 bool "Xilinx ZynqMP R5 based platform"
1292 select DM_ETH if NET
1293 select DM_MMC if MMC
1300 bool "Xilinx ZynqMP based platform"
1304 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1305 select DM_ETH if NET
1307 select DM_MMC if MMC
1309 select DM_SPI if SPI
1310 select DM_SPI_FLASH if DM_SPI
1314 select SPL_BOARD_INIT if SPL
1315 select SPL_CLK if SPL
1316 select SPL_DM if SPL
1317 select SPL_DM_SPI if SPI && SPL_DM
1318 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1319 select SPL_DM_MAILBOX if SPL
1320 imply SPL_FIRMWARE if SPL
1321 select SPL_SEPARATE_BSS if SPL
1325 imply BOARD_LATE_INIT
1327 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1331 imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
1335 select GPIO_EXTRA_HEADER
1336 imply DISTRO_DEFAULTS
1339 config ARCH_VEXPRESS64
1340 bool "Support ARMv8 Arm Ltd. VExpress based boards and models"
1348 select MTD_NOR_FLASH if MTD
1349 select FLASH_CFI_DRIVER if MTD
1350 select ENV_IS_IN_FLASH if MTD
1351 imply DISTRO_DEFAULTS
1353 config TARGET_CORSTONE1000
1354 bool "Support Corstone1000 Platform"
1359 config TARGET_TOTAL_COMPUTE
1360 bool "Support Total Compute Platform"
1368 config TARGET_LS2080A_EMU
1369 bool "Support ls2080a_emu"
1372 select ARMV8_MULTIENTRY
1373 select FSL_DDR_SYNC_REFRESH
1374 select GPIO_EXTRA_HEADER
1376 Support for Freescale LS2080A_EMU platform.
1377 The LS2080A Development System (EMULATOR) is a pre-silicon
1378 development platform that supports the QorIQ LS2080A
1379 Layerscape Architecture processor.
1381 config TARGET_LS1088AQDS
1382 bool "Support ls1088aqds"
1385 select ARMV8_MULTIENTRY
1386 select ARCH_SUPPORT_TFABOOT
1387 select BOARD_LATE_INIT
1388 select GPIO_EXTRA_HEADER
1390 select FSL_DDR_INTERACTIVE if !SD_BOOT
1392 Support for NXP LS1088AQDS platform.
1393 The LS1088A Development System (QDS) is a high-performance
1394 development platform that supports the QorIQ LS1088A
1395 Layerscape Architecture processor.
1397 config TARGET_LS2080AQDS
1398 bool "Support ls2080aqds"
1401 select ARMV8_MULTIENTRY
1402 select ARCH_SUPPORT_TFABOOT
1403 select BOARD_LATE_INIT
1404 select GPIO_EXTRA_HEADER
1409 select FSL_DDR_INTERACTIVE if !SPL
1411 Support for Freescale LS2080AQDS platform.
1412 The LS2080A Development System (QDS) is a high-performance
1413 development platform that supports the QorIQ LS2080A
1414 Layerscape Architecture processor.
1416 config TARGET_LS2080ARDB
1417 bool "Support ls2080ardb"
1420 select ARMV8_MULTIENTRY
1421 select ARCH_SUPPORT_TFABOOT
1422 select BOARD_LATE_INIT
1425 select FSL_DDR_INTERACTIVE if !SPL
1426 select GPIO_EXTRA_HEADER
1430 Support for Freescale LS2080ARDB platform.
1431 The LS2080A Reference design board (RDB) is a high-performance
1432 development platform that supports the QorIQ LS2080A
1433 Layerscape Architecture processor.
1435 config TARGET_LS2081ARDB
1436 bool "Support ls2081ardb"
1439 select ARMV8_MULTIENTRY
1440 select BOARD_LATE_INIT
1441 select GPIO_EXTRA_HEADER
1444 Support for Freescale LS2081ARDB platform.
1445 The LS2081A Reference design board (RDB) is a high-performance
1446 development platform that supports the QorIQ LS2081A/LS2041A
1447 Layerscape Architecture processor.
1449 config TARGET_LX2160ARDB
1450 bool "Support lx2160ardb"
1453 select ARMV8_MULTIENTRY
1454 select ARCH_SUPPORT_TFABOOT
1455 select BOARD_LATE_INIT
1456 select GPIO_EXTRA_HEADER
1458 Support for NXP LX2160ARDB platform.
1459 The lx2160ardb (LX2160A Reference design board (RDB)
1460 is a high-performance development platform that supports the
1461 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1463 config TARGET_LX2160AQDS
1464 bool "Support lx2160aqds"
1467 select ARMV8_MULTIENTRY
1468 select ARCH_SUPPORT_TFABOOT
1469 select BOARD_LATE_INIT
1470 select GPIO_EXTRA_HEADER
1472 Support for NXP LX2160AQDS platform.
1473 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1474 is a high-performance development platform that supports the
1475 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1477 config TARGET_LX2162AQDS
1478 bool "Support lx2162aqds"
1480 select ARCH_MISC_INIT
1482 select ARMV8_MULTIENTRY
1483 select ARCH_SUPPORT_TFABOOT
1484 select BOARD_LATE_INIT
1485 select GPIO_EXTRA_HEADER
1487 Support for NXP LX2162AQDS platform.
1488 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1491 bool "Support HiKey 96boards Consumer Edition Platform"
1496 select GPIO_EXTRA_HEADER
1499 select SPECIFY_CONSOLE_INDEX
1502 Support for HiKey 96boards platform. It features a HI6220
1503 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1505 config TARGET_HIKEY960
1506 bool "Support HiKey960 96boards Consumer Edition Platform"
1510 select GPIO_EXTRA_HEADER
1515 Support for HiKey960 96boards platform. It features a HI3660
1516 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1518 config TARGET_POPLAR
1519 bool "Support Poplar 96boards Enterprise Edition Platform"
1523 select GPIO_EXTRA_HEADER
1528 Support for Poplar 96boards EE platform. It features a HI3798cv200
1529 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1530 making it capable of running any commercial set-top solution based on
1533 config TARGET_LS1012AQDS
1534 bool "Support ls1012aqds"
1537 select ARCH_SUPPORT_TFABOOT
1538 select BOARD_LATE_INIT
1539 select GPIO_EXTRA_HEADER
1541 Support for Freescale LS1012AQDS platform.
1542 The LS1012A Development System (QDS) is a high-performance
1543 development platform that supports the QorIQ LS1012A
1544 Layerscape Architecture processor.
1546 config TARGET_LS1012ARDB
1547 bool "Support ls1012ardb"
1550 select ARCH_SUPPORT_TFABOOT
1551 select BOARD_LATE_INIT
1552 select GPIO_EXTRA_HEADER
1556 Support for Freescale LS1012ARDB platform.
1557 The LS1012A Reference design board (RDB) is a high-performance
1558 development platform that supports the QorIQ LS1012A
1559 Layerscape Architecture processor.
1561 config TARGET_LS1012A2G5RDB
1562 bool "Support ls1012a2g5rdb"
1565 select ARCH_SUPPORT_TFABOOT
1566 select BOARD_LATE_INIT
1567 select GPIO_EXTRA_HEADER
1570 Support for Freescale LS1012A2G5RDB platform.
1571 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1572 development platform that supports the QorIQ LS1012A
1573 Layerscape Architecture processor.
1575 config TARGET_LS1012AFRWY
1576 bool "Support ls1012afrwy"
1579 select ARCH_SUPPORT_TFABOOT
1580 select BOARD_LATE_INIT
1581 select GPIO_EXTRA_HEADER
1585 Support for Freescale LS1012AFRWY platform.
1586 The LS1012A FRWY board (FRWY) is a high-performance
1587 development platform that supports the QorIQ LS1012A
1588 Layerscape Architecture processor.
1590 config TARGET_LS1012AFRDM
1591 bool "Support ls1012afrdm"
1594 select ARCH_SUPPORT_TFABOOT
1595 select GPIO_EXTRA_HEADER
1597 Support for Freescale LS1012AFRDM platform.
1598 The LS1012A Freedom board (FRDM) is a high-performance
1599 development platform that supports the QorIQ LS1012A
1600 Layerscape Architecture processor.
1602 config TARGET_LS1028AQDS
1603 bool "Support ls1028aqds"
1606 select ARMV8_MULTIENTRY
1607 select ARCH_SUPPORT_TFABOOT
1608 select BOARD_LATE_INIT
1609 select GPIO_EXTRA_HEADER
1611 Support for Freescale LS1028AQDS platform
1612 The LS1028A Development System (QDS) is a high-performance
1613 development platform that supports the QorIQ LS1028A
1614 Layerscape Architecture processor.
1616 config TARGET_LS1028ARDB
1617 bool "Support ls1028ardb"
1620 select ARMV8_MULTIENTRY
1621 select ARCH_SUPPORT_TFABOOT
1622 select BOARD_LATE_INIT
1623 select GPIO_EXTRA_HEADER
1625 Support for Freescale LS1028ARDB platform
1626 The LS1028A Development System (RDB) is a high-performance
1627 development platform that supports the QorIQ LS1028A
1628 Layerscape Architecture processor.
1630 config TARGET_LS1088ARDB
1631 bool "Support ls1088ardb"
1634 select ARMV8_MULTIENTRY
1635 select ARCH_SUPPORT_TFABOOT
1636 select BOARD_LATE_INIT
1638 select FSL_DDR_INTERACTIVE if !SD_BOOT
1639 select GPIO_EXTRA_HEADER
1641 Support for NXP LS1088ARDB platform.
1642 The LS1088A Reference design board (RDB) is a high-performance
1643 development platform that supports the QorIQ LS1088A
1644 Layerscape Architecture processor.
1646 config TARGET_LS1021AQDS
1647 bool "Support ls1021aqds"
1649 select ARCH_SUPPORT_PSCI
1650 select BOARD_EARLY_INIT_F
1651 select BOARD_LATE_INIT
1653 select CPU_V7_HAS_NONSEC
1654 select CPU_V7_HAS_VIRT
1655 select LS1_DEEP_SLEEP
1658 select FSL_DDR_INTERACTIVE
1659 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1660 select GPIO_EXTRA_HEADER
1661 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1664 config TARGET_LS1021ATWR
1665 bool "Support ls1021atwr"
1667 select ARCH_SUPPORT_PSCI
1668 select BOARD_EARLY_INIT_F
1669 select BOARD_LATE_INIT
1671 select CPU_V7_HAS_NONSEC
1672 select CPU_V7_HAS_VIRT
1673 select LS1_DEEP_SLEEP
1675 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1676 select GPIO_EXTRA_HEADER
1679 config TARGET_PG_WCOM_SELI8
1680 bool "Support Hitachi-Powergrids SELI8 service unit card"
1682 select ARCH_SUPPORT_PSCI
1683 select BOARD_EARLY_INIT_F
1684 select BOARD_LATE_INIT
1686 select CPU_V7_HAS_NONSEC
1687 select CPU_V7_HAS_VIRT
1689 select FSL_DDR_INTERACTIVE
1690 select GPIO_EXTRA_HEADER
1694 Support for Hitachi-Powergrids SELI8 service unit card.
1695 SELI8 is a QorIQ LS1021a based service unit card used
1696 in XMC20 and FOX615 product families.
1698 config TARGET_PG_WCOM_EXPU1
1699 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1701 select ARCH_SUPPORT_PSCI
1702 select BOARD_EARLY_INIT_F
1703 select BOARD_LATE_INIT
1705 select CPU_V7_HAS_NONSEC
1706 select CPU_V7_HAS_VIRT
1708 select FSL_DDR_INTERACTIVE
1712 Support for Hitachi-Powergrids EXPU1 service unit card.
1713 EXPU1 is a QorIQ LS1021a based service unit card used
1714 in XMC20 and FOX615 product families.
1716 config TARGET_LS1021ATSN
1717 bool "Support ls1021atsn"
1719 select ARCH_SUPPORT_PSCI
1720 select BOARD_EARLY_INIT_F
1721 select BOARD_LATE_INIT
1723 select CPU_V7_HAS_NONSEC
1724 select CPU_V7_HAS_VIRT
1725 select LS1_DEEP_SLEEP
1727 select GPIO_EXTRA_HEADER
1730 config TARGET_LS1021AIOT
1731 bool "Support ls1021aiot"
1733 select ARCH_SUPPORT_PSCI
1734 select BOARD_LATE_INIT
1736 select CPU_V7_HAS_NONSEC
1737 select CPU_V7_HAS_VIRT
1739 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1740 select GPIO_EXTRA_HEADER
1743 Support for Freescale LS1021AIOT platform.
1744 The LS1021A Freescale board (IOT) is a high-performance
1745 development platform that supports the QorIQ LS1021A
1746 Layerscape Architecture processor.
1748 config TARGET_LS1043AQDS
1749 bool "Support ls1043aqds"
1752 select ARMV8_MULTIENTRY
1753 select ARCH_SUPPORT_TFABOOT
1754 select BOARD_EARLY_INIT_F
1755 select BOARD_LATE_INIT
1757 select FSL_DDR_INTERACTIVE if !SPL
1758 select FSL_DSPI if !SPL_NO_DSPI
1759 select DM_SPI_FLASH if FSL_DSPI
1760 select GPIO_EXTRA_HEADER
1764 Support for Freescale LS1043AQDS platform.
1766 config TARGET_LS1043ARDB
1767 bool "Support ls1043ardb"
1770 select ARMV8_MULTIENTRY
1771 select ARCH_SUPPORT_TFABOOT
1772 select BOARD_EARLY_INIT_F
1773 select BOARD_LATE_INIT
1775 select FSL_DSPI if !SPL_NO_DSPI
1776 select DM_SPI_FLASH if FSL_DSPI
1777 select GPIO_EXTRA_HEADER
1779 Support for Freescale LS1043ARDB platform.
1781 config TARGET_LS1046AQDS
1782 bool "Support ls1046aqds"
1785 select ARMV8_MULTIENTRY
1786 select ARCH_SUPPORT_TFABOOT
1787 select BOARD_EARLY_INIT_F
1788 select BOARD_LATE_INIT
1789 select DM_SPI_FLASH if DM_SPI
1791 select FSL_DDR_BIST if !SPL
1792 select FSL_DDR_INTERACTIVE if !SPL
1793 select FSL_DDR_INTERACTIVE if !SPL
1794 select GPIO_EXTRA_HEADER
1797 Support for Freescale LS1046AQDS platform.
1798 The LS1046A Development System (QDS) is a high-performance
1799 development platform that supports the QorIQ LS1046A
1800 Layerscape Architecture processor.
1802 config TARGET_LS1046ARDB
1803 bool "Support ls1046ardb"
1806 select ARMV8_MULTIENTRY
1807 select ARCH_SUPPORT_TFABOOT
1808 select BOARD_EARLY_INIT_F
1809 select BOARD_LATE_INIT
1810 select DM_SPI_FLASH if DM_SPI
1811 select POWER_MC34VR500
1814 select FSL_DDR_INTERACTIVE if !SPL
1815 select GPIO_EXTRA_HEADER
1818 Support for Freescale LS1046ARDB platform.
1819 The LS1046A Reference Design Board (RDB) is a high-performance
1820 development platform that supports the QorIQ LS1046A
1821 Layerscape Architecture processor.
1823 config TARGET_LS1046AFRWY
1824 bool "Support ls1046afrwy"
1827 select ARMV8_MULTIENTRY
1828 select ARCH_SUPPORT_TFABOOT
1829 select BOARD_EARLY_INIT_F
1830 select BOARD_LATE_INIT
1831 select DM_SPI_FLASH if DM_SPI
1832 select GPIO_EXTRA_HEADER
1835 Support for Freescale LS1046AFRWY platform.
1836 The LS1046A Freeway Board (FRWY) is a high-performance
1837 development platform that supports the QorIQ LS1046A
1838 Layerscape Architecture processor.
1844 select ARMV8_MULTIENTRY
1860 select GPIO_EXTRA_HEADER
1861 select SPL_DM if SPL
1862 select SPL_DM_SPI if SPL
1863 select SPL_DM_SPI_FLASH if SPL
1864 select SPL_DM_I2C if SPL
1865 select SPL_DM_MMC if SPL
1866 select SPL_DM_SERIAL if SPL
1868 Support for Kontron SMARC-sAL28 board.
1871 bool "Support ten64"
1873 select ARCH_MISC_INIT
1875 select ARMV8_MULTIENTRY
1876 select ARCH_SUPPORT_TFABOOT
1877 select BOARD_LATE_INIT
1879 select FSL_DDR_INTERACTIVE if !SD_BOOT
1880 select GPIO_EXTRA_HEADER
1882 Support for Traverse Technologies Ten64 board, based
1885 config ARCH_UNIPHIER
1886 bool "Socionext UniPhier SoCs"
1887 select BOARD_LATE_INIT
1896 select OF_BOARD_SETUP
1900 select SPL_BOARD_INIT if SPL
1901 select SPL_DM if SPL
1902 select SPL_LIBCOMMON_SUPPORT if SPL
1903 select SPL_LIBGENERIC_SUPPORT if SPL
1904 select SPL_OF_CONTROL if SPL
1905 select SPL_PINCTRL if SPL
1908 imply DISTRO_DEFAULTS
1911 Support for UniPhier SoC family developed by Socionext Inc.
1912 (formerly, System LSI Business Division of Panasonic Corporation)
1914 config ARCH_SYNQUACER
1915 bool "Socionext SynQuacer SoCs"
1921 select SYSRESET_PSCI
1924 Support for SynQuacer SoC family developed by Socionext Inc.
1925 This SoC is used on 96boards EE DeveloperBox.
1928 bool "Support STMicroelectronics STM32 MCU with cortex M"
1935 bool "Support STMicroelectronics SoCs"
1944 Support for STMicroelectronics STiH407/10 SoC family.
1945 This SoC is used on Linaro 96Board STiH410-B2260
1948 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1949 select ARCH_MISC_INIT
1950 select ARCH_SUPPORT_TFABOOT
1951 select BOARD_LATE_INIT
1960 select OF_SYSTEM_SETUP
1965 select SYS_THUMB_BUILD
1969 imply OF_LIBFDT_OVERLAY
1970 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1974 Support for STM32MP SoC family developed by STMicroelectronics,
1975 MPUs based on ARM cortex A core
1976 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1977 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1979 SPL is the unsecure FSBL for the basic boot chain.
1981 config ARCH_ROCKCHIP
1982 bool "Support Rockchip SoCs"
1984 select BINMAN if SPL_OPTEE || (SPL && !ARM64)
1994 select ENABLE_ARM_SOC_BOOT0_HOOK
1997 select SPL_DM if SPL
1998 select SPL_DM_SPI if SPL
1999 select SPL_DM_SPI_FLASH if SPL
2001 select SYS_THUMB_BUILD if !ARM64
2004 imply DEBUG_UART_BOARD_INIT
2005 imply DISTRO_DEFAULTS
2007 imply SARADC_ROCKCHIP
2009 imply SPL_SYS_MALLOC_SIMPLE
2012 imply USB_FUNCTION_FASTBOOT
2014 config ARCH_OCTEONTX
2015 bool "Support OcteonTX SoCs"
2018 select GPIO_EXTRA_HEADER
2022 select BOARD_LATE_INIT
2023 select SYS_CACHE_SHIFT_7
2024 select SYS_PCI_64BIT if PCI
2025 imply OF_HAS_PRIOR_STAGE
2027 config ARCH_OCTEONTX2
2028 bool "Support OcteonTX2 SoCs"
2031 select GPIO_EXTRA_HEADER
2035 select BOARD_LATE_INIT
2036 select SYS_CACHE_SHIFT_7
2037 select SYS_PCI_64BIT if PCI
2038 imply OF_HAS_PRIOR_STAGE
2040 config TARGET_THUNDERX_88XX
2041 bool "Support ThunderX 88xx"
2043 select GPIO_EXTRA_HEADER
2046 select SYS_CACHE_SHIFT_7
2049 bool "Support Aspeed SoCs"
2054 config TARGET_DURIAN
2055 bool "Support Phytium Durian Platform"
2057 select GPIO_EXTRA_HEADER
2059 Support for durian platform.
2060 It has 2GB Sdram, uart and pcie.
2062 config TARGET_POMELO
2063 bool "Support Phytium Pomelo Platform"
2075 select DM_ETH if NET
2078 Support for pomelo platform.
2079 It has 8GB Sdram, uart and pcie.
2081 config TARGET_PRESIDIO_ASIC
2082 bool "Support Cortina Presidio ASIC Platform"
2086 config TARGET_XENGUEST_ARM64
2087 bool "Xen guest ARM64"
2091 select LINUX_KERNEL_IMAGE_HEADER
2094 imply OF_HAS_PRIOR_STAGE
2097 bool "Support HPE GXP SoCs"
2104 config SUPPORT_PASSING_ATAGS
2105 bool "Support pre-devicetree ATAG-based booting"
2107 imply SETUP_MEMORY_TAGS
2109 Support for booting older Linux kernels, using ATAGs rather than
2110 passing a devicetree. This is option is rarely used, and the
2111 semantics are defined at
2112 https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
2114 config SETUP_MEMORY_TAGS
2115 bool "Pass memory size information via ATAG"
2116 depends on SUPPORT_PASSING_ATAGS
2119 bool "Pass Linux kernel cmdline via ATAG"
2120 depends on SUPPORT_PASSING_ATAGS
2123 bool "Pass initrd starting point and size via ATAG"
2124 depends on SUPPORT_PASSING_ATAGS
2127 bool "Pass system revision via ATAG"
2128 depends on SUPPORT_PASSING_ATAGS
2131 bool "Pass system serial number via ATAG"
2132 depends on SUPPORT_PASSING_ATAGS
2134 config STATIC_MACH_TYPE
2135 bool "Statically define the Machine ID number"
2137 When booting via ATAGs, enable this option if we know the correct
2138 machine ID number to use at compile time. Some systems will be
2139 passed the number dynamically by whatever loads U-Boot.
2142 int "Machine ID number"
2143 depends on STATIC_MACH_TYPE
2145 When booting via ATAGs, the machine type must be passed as a number.
2146 For the full list see https://www.arm.linux.org.uk/developer/machines
2148 config ARCH_SUPPORT_TFABOOT
2152 bool "Support for booting from TF-A"
2153 depends on ARCH_SUPPORT_TFABOOT
2155 Some platforms support the setup of secure registers (for instance
2156 for CPU errata handling) or provide secure services like PSCI.
2157 Those services could also be provided by other firmware parts
2158 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
2159 does not need to (and cannot) execute this code.
2160 Enabling this option will make a U-Boot binary that is relying
2161 on other firmware layers to provide secure functionality.
2163 config TI_SECURE_DEVICE
2164 bool "HS Device Type Support"
2165 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
2167 If a high secure (HS) device type is being used, this config
2168 must be set. This option impacts various aspects of the
2169 build system (to create signed boot images that can be
2170 authenticated) and the code. See the doc/README.ti-secure
2171 file for further details.
2173 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
2174 config ISW_ENTRY_ADDR
2175 hex "Address in memory or XIP address of bootloader entry point"
2176 default 0x402F4000 if AM43XX
2177 default 0x402F0400 if AM33XX
2178 default 0x40301350 if OMAP54XX
2180 After any reset, the boot ROM searches the boot media for a valid
2181 boot image. For non-XIP devices, the ROM then copies the image into
2182 internal memory. For all boot modes, after the ROM processes the
2183 boot image it eventually computes the entry point address depending
2184 on the device type (secure/non-secure), boot media (xip/non-xip) and
2188 config SYS_KWD_CONFIG
2189 string "kwbimage config file path"
2190 depends on ARCH_KIRKWOOD || ARCH_MVEBU
2191 default "arch/arm/mach-mvebu/kwbimage.cfg"
2193 Path within the source directory to the kwbimage.cfg file to use
2194 when packaging the U-Boot image for use.
2196 source "arch/arm/mach-apple/Kconfig"
2198 source "arch/arm/mach-aspeed/Kconfig"
2200 source "arch/arm/mach-at91/Kconfig"
2202 source "arch/arm/mach-bcm283x/Kconfig"
2204 source "arch/arm/mach-bcmbca/Kconfig"
2206 source "arch/arm/mach-bcmstb/Kconfig"
2208 source "arch/arm/mach-davinci/Kconfig"
2210 source "arch/arm/mach-exynos/Kconfig"
2212 source "arch/arm/mach-hpe/gxp/Kconfig"
2214 source "arch/arm/mach-highbank/Kconfig"
2216 source "arch/arm/mach-integrator/Kconfig"
2218 source "arch/arm/mach-ipq40xx/Kconfig"
2220 source "arch/arm/mach-k3/Kconfig"
2222 source "arch/arm/mach-keystone/Kconfig"
2224 source "arch/arm/mach-kirkwood/Kconfig"
2226 source "arch/arm/mach-lpc32xx/Kconfig"
2228 source "arch/arm/mach-mvebu/Kconfig"
2230 source "arch/arm/mach-octeontx/Kconfig"
2232 source "arch/arm/mach-octeontx2/Kconfig"
2234 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
2236 source "arch/arm/mach-imx/mx3/Kconfig"
2238 source "arch/arm/mach-imx/mx5/Kconfig"
2240 source "arch/arm/mach-imx/mx6/Kconfig"
2242 source "arch/arm/mach-imx/mx7/Kconfig"
2244 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2246 source "arch/arm/mach-imx/imx8/Kconfig"
2248 source "arch/arm/mach-imx/imx8m/Kconfig"
2250 source "arch/arm/mach-imx/imx8ulp/Kconfig"
2252 source "arch/arm/mach-imx/imxrt/Kconfig"
2254 source "arch/arm/mach-imx/mxs/Kconfig"
2256 source "arch/arm/mach-omap2/Kconfig"
2258 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2260 source "arch/arm/mach-orion5x/Kconfig"
2262 source "arch/arm/mach-owl/Kconfig"
2264 source "arch/arm/mach-rmobile/Kconfig"
2266 source "arch/arm/mach-meson/Kconfig"
2268 source "arch/arm/mach-mediatek/Kconfig"
2270 source "arch/arm/mach-qemu/Kconfig"
2272 source "arch/arm/mach-rockchip/Kconfig"
2274 source "arch/arm/mach-s5pc1xx/Kconfig"
2276 source "arch/arm/mach-snapdragon/Kconfig"
2278 source "arch/arm/mach-socfpga/Kconfig"
2280 source "arch/arm/mach-sti/Kconfig"
2282 source "arch/arm/mach-stm32/Kconfig"
2284 source "arch/arm/mach-stm32mp/Kconfig"
2286 source "arch/arm/mach-sunxi/Kconfig"
2288 source "arch/arm/mach-tegra/Kconfig"
2290 source "arch/arm/mach-u8500/Kconfig"
2292 source "arch/arm/mach-uniphier/Kconfig"
2294 source "arch/arm/cpu/armv7/vf610/Kconfig"
2296 source "arch/arm/mach-zynq/Kconfig"
2298 source "arch/arm/mach-zynqmp/Kconfig"
2300 source "arch/arm/mach-versal/Kconfig"
2302 source "arch/arm/mach-zynqmp-r5/Kconfig"
2304 source "arch/arm/cpu/armv7/Kconfig"
2306 source "arch/arm/cpu/armv8/Kconfig"
2308 source "arch/arm/mach-imx/Kconfig"
2310 source "arch/arm/mach-nexell/Kconfig"
2312 source "arch/arm/mach-npcm/Kconfig"
2314 source "board/armltd/total_compute/Kconfig"
2315 source "board/armltd/corstone1000/Kconfig"
2316 source "board/bosch/shc/Kconfig"
2317 source "board/bosch/guardian/Kconfig"
2318 source "board/Marvell/octeontx/Kconfig"
2319 source "board/Marvell/octeontx2/Kconfig"
2320 source "board/armltd/vexpress/Kconfig"
2321 source "board/armltd/vexpress64/Kconfig"
2322 source "board/cortina/presidio-asic/Kconfig"
2323 source "board/broadcom/bcm963158/Kconfig"
2324 source "board/broadcom/bcm96753ref/Kconfig"
2325 source "board/broadcom/bcm968360bg/Kconfig"
2326 source "board/broadcom/bcm968580xref/Kconfig"
2327 source "board/broadcom/bcmns3/Kconfig"
2328 source "board/cavium/thunderx/Kconfig"
2329 source "board/eets/pdu001/Kconfig"
2330 source "board/emulation/qemu-arm/Kconfig"
2331 source "board/freescale/ls2080aqds/Kconfig"
2332 source "board/freescale/ls2080ardb/Kconfig"
2333 source "board/freescale/ls1088a/Kconfig"
2334 source "board/freescale/ls1028a/Kconfig"
2335 source "board/freescale/ls1021aqds/Kconfig"
2336 source "board/freescale/ls1043aqds/Kconfig"
2337 source "board/freescale/ls1021atwr/Kconfig"
2338 source "board/freescale/ls1021atsn/Kconfig"
2339 source "board/freescale/ls1021aiot/Kconfig"
2340 source "board/freescale/ls1046aqds/Kconfig"
2341 source "board/freescale/ls1043ardb/Kconfig"
2342 source "board/freescale/ls1046ardb/Kconfig"
2343 source "board/freescale/ls1046afrwy/Kconfig"
2344 source "board/freescale/ls1012aqds/Kconfig"
2345 source "board/freescale/ls1012ardb/Kconfig"
2346 source "board/freescale/ls1012afrdm/Kconfig"
2347 source "board/freescale/lx2160a/Kconfig"
2348 source "board/grinn/chiliboard/Kconfig"
2349 source "board/hisilicon/hikey/Kconfig"
2350 source "board/hisilicon/hikey960/Kconfig"
2351 source "board/hisilicon/poplar/Kconfig"
2352 source "board/isee/igep003x/Kconfig"
2353 source "board/kontron/sl28/Kconfig"
2354 source "board/myir/mys_6ulx/Kconfig"
2355 source "board/siemens/common/Kconfig"
2356 source "board/seeed/npi_imx6ull/Kconfig"
2357 source "board/socionext/developerbox/Kconfig"
2358 source "board/st/stv0991/Kconfig"
2359 source "board/tcl/sl50/Kconfig"
2360 source "board/traverse/ten64/Kconfig"
2361 source "board/variscite/dart_6ul/Kconfig"
2362 source "board/vscom/baltos/Kconfig"
2363 source "board/phytium/durian/Kconfig"
2364 source "board/phytium/pomelo/Kconfig"
2365 source "board/xen/xenguest_arm64/Kconfig"
2367 source "arch/arm/Kconfig.debug"