soc: starfive: Add feature for hw event masks

Add hw event masks off feature for use with other drives.

Signed-off-by: Walker Chen <walker.chen@linux.starfivetech.com>
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Change-Id: I5b8862cd50b35f0b8ceed770d95a5c17bde8b12c

diff --git a/drivers/pmdomain/starfive/jh71xx-pmu.c b/drivers/pmdomain/starfive/jh71xx-pmu.c
index 7d5f50d..8bb03c9 100644 (file)
--- a/drivers/pmdomain/starfive/jh71xx-pmu.c
+++ b/drivers/pmdomain/starfive/jh71xx-pmu.c
@@ -16,6 +16,7 @@
 #include <dt-bindings/power/starfive,jh7110-pmu.h>
 
 /* register offset */
+#define JH71XX_PMU_HW_EVENT_TURN_OFF_MASK 0x08
 #define JH71XX_PMU_SW_TURN_ON_POWER    0x0C
 #define JH71XX_PMU_SW_TURN_OFF_POWER   0x10
 #define JH71XX_PMU_SW_ENCOURAGE                0x44
@@ -72,6 +73,14 @@ struct jh71xx_pmu_dev {
        struct generic_pm_domain genpd;
 };
 
+static void __iomem *pmu_base;
+
+void jh71xx_pmu_hw_event_turn_off_mask(u32 mask)
+{
+       writel(mask, pmu_base + JH71XX_PMU_HW_EVENT_TURN_OFF_MASK);
+}
+EXPORT_SYMBOL(jh71xx_pmu_hw_event_turn_off_mask);
+
 static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_on)
 {
        struct jh71xx_pmu *pmu = pmd->pmu;
@@ -316,6 +325,8 @@ static int jh71xx_pmu_probe(struct platform_device *pdev)
                return ret;
        }
 
+       pmu_base = pmu->base;
+
        dev_dbg(dev, "registered %u power domains\n", i);
 
        return 0;

diff --git a/include/soc/starfive/jh71xx_pmu.h b/include/soc/starfive/jh71xx_pmu.h
new file mode 100644 (file)
index 0000000..425fea5
--- /dev/null
+++ b/include/soc/starfive/jh71xx_pmu.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * StarFive JH71XX PMU (Power Management Unit) Controller Driver
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+
+#ifndef __SOC_STARFIVE_JH71XX_PMU_H__
+#define __SOC_STARFIVE_JH71XX_PMU_H__
+
+void jh71xx_pmu_hw_event_turn_off_mask(u32 mask);
+
+#endif /* __SOC_STARFIVE_JH71XX_PMU_H__ */