arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "jh7110-clk.dtsi"
   9 #include <dt-bindings/reset/starfive-jh7110.h>
  10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
  12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
  13 #include <dt-bindings/power/jh7110-power.h>
  14
  15 / {
  16         compatible = "starfive,jh7110";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cluster0_opp: opp-table-0 {
  21                         compatible = "operating-points-v2";
  22                         opp-shared;
  23                         opp-375000000 {
  24                                         opp-hz = /bits/ 64 <375000000>;
  25                                         opp-microvolt = <800000>;
  26                         };
  27                         opp-500000000 {
  28                                         opp-hz = /bits/ 64 <500000000>;
  29                                         opp-microvolt = <800000>;
  30                         };
  31                         opp-750000000 {
  32                                         opp-hz = /bits/ 64 <750000000>;
  33                                         opp-microvolt = <800000>;
  34                                         opp-suspend;
  35                         };
  36                         opp-1500000000 {
  37                                         opp-hz = /bits/ 64 <1500000000>;
  38                                         opp-microvolt = <1040000>;
  39                         };
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 cpu0: cpu@0 {
  47                         compatible = "sifive,u74-mc", "riscv";
  48                         reg = <0>;
  49                         d-cache-block-size = <64>;
  50                         d-cache-sets = <64>;
  51                         d-cache-size = <8192>;
  52                         d-tlb-sets = <1>;
  53                         d-tlb-size = <40>;
  54                         device_type = "cpu";
  55                         i-cache-block-size = <64>;
  56                         i-cache-sets = <64>;
  57                         i-cache-size = <16384>;
  58                         i-tlb-sets = <1>;
  59                         i-tlb-size = <40>;
  60                         mmu-type = "riscv,sv39";
  61                         next-level-cache = <&cachectrl>;
  62                         riscv,isa = "rv64imac";
  63                         tlb-split;
  64                         status = "disabled";
  65
  66                         cpu0intctrl: interrupt-controller {
  67                                 #interrupt-cells = <1>;
  68                                 compatible = "riscv,cpu-intc";
  69                                 interrupt-controller;
  70                         };
  71                 };
  72
  73                 cpu1: cpu@1 {
  74                         compatible = "sifive,u74-mc", "riscv";
  75                         reg = <1>;
  76                         d-cache-block-size = <64>;
  77                         d-cache-sets = <64>;
  78                         d-cache-size = <32768>;
  79                         d-tlb-sets = <1>;
  80                         d-tlb-size = <40>;
  81                         device_type = "cpu";
  82                         i-cache-block-size = <64>;
  83                         i-cache-sets = <64>;
  84                         i-cache-size = <32768>;
  85                         i-tlb-sets = <1>;
  86                         i-tlb-size = <40>;
  87                         mmu-type = "riscv,sv39";
  88                         next-level-cache = <&cachectrl>;
  89                         riscv,isa = "rv64imafdc";
  90                         tlb-split;
  91                         status = "okay";
  92                         operating-points-v2 = <&cluster0_opp>;
  93
  94                         cpu1intctrl: interrupt-controller {
  95                                 #interrupt-cells = <1>;
  96                                 compatible = "riscv,cpu-intc";
  97                                 interrupt-controller;
  98                         };
  99                 };
 100
 101                 cpu2: cpu@2 {
 102                         compatible = "sifive,u74-mc", "riscv";
 103                         reg = <2>;
 104                         d-cache-block-size = <64>;
 105                         d-cache-sets = <64>;
 106                         d-cache-size = <32768>;
 107                         d-tlb-sets = <1>;
 108                         d-tlb-size = <40>;
 109                         device_type = "cpu";
 110                         i-cache-block-size = <64>;
 111                         i-cache-sets = <64>;
 112                         i-cache-size = <32768>;
 113                         i-tlb-sets = <1>;
 114                         i-tlb-size = <40>;
 115                         mmu-type = "riscv,sv39";
 116                         next-level-cache = <&cachectrl>;
 117                         riscv,isa = "rv64imafdc";
 118                         tlb-split;
 119                         status = "okay";
 120                         operating-points-v2 = <&cluster0_opp>;
 121
 122                         cpu2intctrl: interrupt-controller {
 123                                 #interrupt-cells = <1>;
 124                                 compatible = "riscv,cpu-intc";
 125                                 interrupt-controller;
 126                         };
 127                 };
 128
 129                 cpu3: cpu@3 {
 130                         compatible = "sifive,u74-mc", "riscv";
 131                         reg = <3>;
 132                         d-cache-block-size = <64>;
 133                         d-cache-sets = <64>;
 134                         d-cache-size = <32768>;
 135                         d-tlb-sets = <1>;
 136                         d-tlb-size = <40>;
 137                         device_type = "cpu";
 138                         i-cache-block-size = <64>;
 139                         i-cache-sets = <64>;
 140                         i-cache-size = <32768>;
 141                         i-tlb-sets = <1>;
 142                         i-tlb-size = <40>;
 143                         mmu-type = "riscv,sv39";
 144                         next-level-cache = <&cachectrl>;
 145                         riscv,isa = "rv64imafdc";
 146                         tlb-split;
 147                         status = "okay";
 148                         operating-points-v2 = <&cluster0_opp>;
 149
 150                         cpu3intctrl: interrupt-controller {
 151                                 #interrupt-cells = <1>;
 152                                 compatible = "riscv,cpu-intc";
 153                                 interrupt-controller;
 154                         };
 155                 };
 156
 157                 cpu4: cpu@4 {
 158                         compatible = "sifive,u74-mc", "riscv";
 159                         reg = <4>;
 160                         d-cache-block-size = <64>;
 161                         d-cache-sets = <64>;
 162                         d-cache-size = <32768>;
 163                         d-tlb-sets = <1>;
 164                         d-tlb-size = <40>;
 165                         device_type = "cpu";
 166                         i-cache-block-size = <64>;
 167                         i-cache-sets = <64>;
 168                         i-cache-size = <32768>;
 169                         i-tlb-sets = <1>;
 170                         i-tlb-size = <40>;
 171                         mmu-type = "riscv,sv39";
 172                         next-level-cache = <&cachectrl>;
 173                         riscv,isa = "rv64imafdc";
 174                         tlb-split;
 175                         status = "okay";
 176                         operating-points-v2 = <&cluster0_opp>;
 177
 178                         cpu4intctrl: interrupt-controller {
 179                                 #interrupt-cells = <1>;
 180                                 compatible = "riscv,cpu-intc";
 181                                 interrupt-controller;
 182                         };
 183                 };
 184         };
 185
 186         soc: soc {
 187                 compatible = "simple-bus";
 188                 interrupt-parent = <&plic>;
 189                 #address-cells = <2>;
 190                 #size-cells = <2>;
 191                 #clock-cells = <1>;
 192                 ranges;
 193
 194                 cachectrl: cache-controller@2010000 {
 195                         compatible = "sifive,fu740-c000-ccache", "cache";
 196                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 197                         reg-names = "control", "sideband";
 198                         interrupts = <1 3 4 2>;
 199                         cache-block-size = <64>;
 200                         cache-level = <2>;
 201                         cache-sets = <2048>;
 202                         cache-size = <2097152>;
 203                         cache-unified;
 204                 };
 205
 206                 aon_syscon: aon_syscon@17010000 {
 207                         compatible = "syscon";
 208                         reg = <0x0 0x17010000 0x0 0x1000>;
 209                 };
 210
 211                 phyctrl0: multi-phyctrl@10210000 {
 212                         compatible = "starfive,phyctrl";
 213                         reg = <0x0 0x10210000 0x0 0x10000>;
 214                 };
 215
 216                 phyctrl1: pcie1-phyctrl@10220000 {
 217                         compatible = "starfive,phyctrl";
 218                         reg = <0x0 0x10220000 0x0 0x10000>;
 219                 };
 220
 221                 stg_syscon: stg_syscon@10240000 {
 222                         compatible = "syscon";
 223                         reg = <0x0 0x10240000 0x0 0x1000>;
 224                 };
 225
 226                 sys_syscon: sys_syscon@13030000 {
 227                         compatible = "syscon";
 228                         reg = <0x0 0x13030000 0x0 0x1000>;
 229                 };
 230
 231                 clint: clint@2000000 {
 232                         compatible = "riscv,clint0";
 233                         reg = <0x0 0x2000000 0x0 0x10000>;
 234                         reg-names = "control";
 235                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 236                                                 &cpu1intctrl 3 &cpu1intctrl 7
 237                                                 &cpu2intctrl 3 &cpu2intctrl 7
 238                                                 &cpu3intctrl 3 &cpu3intctrl 7
 239                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 240                         #interrupt-cells = <1>;
 241                 };
 242
 243                 plic: plic@c000000 {
 244                         compatible = "riscv,plic0";
 245                         reg = <0x0 0xc000000 0x0 0x4000000>;
 246                         reg-names = "control";
 247                         interrupts-extended = <&cpu0intctrl 11
 248                                                 &cpu1intctrl 11 &cpu1intctrl 9
 249                                                 &cpu2intctrl 11 &cpu2intctrl 9
 250                                                 &cpu3intctrl 11 &cpu3intctrl 9
 251                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 252                         interrupt-controller;
 253                         #interrupt-cells = <1>;
 254                         riscv,max-priority = <7>;
 255                         riscv,ndev = <136>;
 256                 };
 257
 258                 clkgen: clock-controller {
 259                         compatible = "starfive,jh7110-clkgen";
 260                         reg = <0x0 0x13020000 0x0 0x10000>,
 261                                 <0x0 0x10230000 0x0 0x10000>,
 262                                 <0x0 0x17000000 0x0 0x10000>;
 263                         reg-names = "sys", "stg", "aon";
 264                         clocks = <&osc>, <&gmac1_rmii_refin>,
 265                                  <&gmac1_rgmii_rxin>,
 266                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 267                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 268                                  <&tdm_ext>, <&mclk_ext>,
 269                                  <&jtag_tck_inner>, <&bist_apb>,
 270                                  <&clk_rtc>,
 271                                  <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 272                         clock-names = "osc", "gmac1_rmii_refin",
 273                                 "gmac1_rgmii_rxin",
 274                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
 275                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
 276                                 "tdm_ext", "mclk_ext",
 277                                 "jtag_tck_inner", "bist_apb",
 278                                 "clk_rtc",
 279                                 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
 280                         #clock-cells = <1>;
 281                         starfive,sys-syscon = <&sys_syscon 0x18 0x1c
 282                                         0x20 0x24 0x28 0x2c 0x30 0x34>;
 283                         status = "okay";
 284                 };
 285
 286                 clkvout: clock-controller@295C0000 {
 287                         compatible = "starfive,jh7110-clk-vout";
 288                         reg = <0x0 0x295C0000 0x0 0x10000>;
 289                         reg-names = "vout";
 290                         clocks = <&hdmitx0_pixelclk>,
 291                                  <&mipitx_dphy_rxesc>,
 292                                  <&mipitx_dphy_txbytehs>,
 293                                  <&clkgen JH7110_VOUT_SRC>,
 294                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
 295                         clock-names = "hdmitx0_pixelclk",
 296                                       "mipitx_dphy_rxesc",
 297                                       "mipitx_dphy_txbytehs",
 298                                       "vout_src",
 299                                       "vout_top_ahb";
 300                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
 301                         reset-names = "vout_src";
 302                         #clock-cells = <1>;
 303                         power-domains = <&pwrc JH7110_PD_VOUT>;
 304                         status = "okay";
 305                 };
 306
 307                 clkisp: clock-controller@19810000 {
 308                         compatible = "starfive,jh7110-clk-isp";
 309                         reg = <0x0 0x19810000 0x0 0x10000>;
 310                         reg-names = "isp";
 311                         #clock-cells = <1>;
 312                         clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
 313                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 314                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 315                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 316                         clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
 317                                       "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
 318                                       "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
 319                                       "u0_sft7110_noc_bus_clk_isp_axi";
 320                         resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 321                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
 322                                  <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
 323                         reset-names = "rst_isp_top_n", "rst_isp_top_axi",
 324                                       "rst_isp_noc_bus_n";
 325                         power-domains = <&pwrc JH7110_PD_ISP>;
 326                         status = "okay";
 327                 };
 328
 329                 qspi: spi@13010000 {
 330                         compatible = "cdns,qspi-nor";
 331                         #address-cells = <1>;
 332                         #size-cells = <0>;
 333                         reg = <0x0 0x13010000 0x0 0x10000
 334                                 0x0 0x21000000 0x0 0x400000>;
 335                         interrupts = <25>;
 336                         clocks = <&clkgen JH7110_QSPI_CLK_REF>,
 337                                  <&clkgen JH7110_QSPI_CLK_APB>,
 338                                  <&clkgen JH7110_AHB1>,
 339                                  <&clkgen JH7110_QSPI_CLK_AHB>;
 340                         clock-names = "clk_ref",
 341                                       "clk_apb",
 342                                       "ahb1",
 343                                       "clk_ahb";
 344                         resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 345                                  <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 346                                  <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 347                         cdns,fifo-depth = <256>;
 348                         cdns,fifo-width = <4>;
 349                         cdns,trigger-address = <0x0>;
 350                         spi-max-frequency = <250000000>;
 351
 352                         nor_flash: nor-flash@0 {
 353                                 compatible = "jedec,spi-nor";
 354                                 reg=<0>;
 355                                 cdns,read-delay = <5>;
 356                                 spi-max-frequency = <100000000>;
 357                                 cdns,tshsl-ns = <1>;
 358                                 cdns,tsd2d-ns = <1>;
 359                                 cdns,tchsh-ns = <1>;
 360                                 cdns,tslch-ns = <1>;
 361
 362                                 partitions {
 363                                         compatible = "fixed-partitions";
 364                                         #address-cells = <1>;
 365                                         #size-cells = <1>;
 366
 367                                         spl@0 {
 368                                                 reg = <0x0 0x20000>;
 369                                         };
 370                                         uboot@100000 {
 371                                                 reg = <0x100000 0x300000>;
 372                                         };
 373                                         data@f00000 {
 374                                                 reg = <0xf00000 0x100000>;
 375                                         };
 376                                 };
 377                         };
 378                 };
 379
 380                 otp: otp@17050000 {
 381                         compatible = "starfive,jh7110-otp";
 382                         reg = <0x0 0x17050000 0x0 0x10000>;
 383                         clock-frequency = <4000000>;
 384                         clocks = <&clkgen JH7110_OTPC_CLK_APB>;
 385                         clock-names = "apb";
 386                 };
 387
 388                 usbdrd30: usbdrd{
 389                         compatible = "starfive,jh7110-cdns3";
 390                         reg = <0x0 0x10210000 0x0 0x1000>,
 391                               <0x0 0x10200000 0x0 0x1000>;
 392                         clocks = <&clkgen JH7110_USB_125M>,
 393                                  <&clkgen JH7110_USB0_CLK_APP_125>,
 394                                  <&clkgen JH7110_USB0_CLK_LPM>,
 395                                  <&clkgen JH7110_USB0_CLK_STB>,
 396                                  <&clkgen JH7110_USB0_CLK_USB_APB>,
 397                                  <&clkgen JH7110_USB0_CLK_AXI>,
 398                                  <&clkgen JH7110_USB0_CLK_UTMI_APB>,
 399                                  <&clkgen JH7110_PCIE0_CLK_APB>;
 400                         clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
 401                         resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 402                                  <&rstgen RSTN_U0_CDN_USB_APB>,
 403                                  <&rstgen RSTN_U0_CDN_USB_AXI>,
 404                                  <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
 405                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
 406                         reset-names = "pwrup","apb","axi","utmi", "phy";
 407                         starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
 408                         starfive,sys-syscon = <&sys_syscon 0x18>;
 409                         status = "disabled";
 410                         #address-cells = <2>;
 411                         #size-cells = <2>;
 412                         #interrupt-cells = <1>;
 413                         ranges;
 414                         usbdrd_cdns3: usb@10100000 {
 415                                 compatible = "cdns,usb3";
 416                                 reg = <0x0 0x10100000 0x0 0x10000>,
 417                                       <0x0 0x10110000 0x0 0x10000>,
 418                                       <0x0 0x10120000 0x0 0x10000>;
 419                                 reg-names = "otg", "xhci", "dev";
 420                                 interrupts = <100>, <108>, <110>;
 421                                 interrupt-names = "host", "peripheral", "otg";
 422                                 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
 423                                 maximum-speed = "super-speed";
 424                         };
 425                 };
 426
 427                 timer: timer@13050000 {
 428                         compatible = "starfive,jh7110-timers";
 429                         reg = <0x0 0x13050000 0x0 0x10000>;
 430                         interrupts = <69>, <70>, <71> ,<72>;
 431                         interrupt-names = "timer0", "timer1",
 432                                           "timer2", "timer3";
 433                         clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
 434                                  <&clkgen JH7110_TIMER_CLK_TIMER1>,
 435                                  <&clkgen JH7110_TIMER_CLK_TIMER2>,
 436                                  <&clkgen JH7110_TIMER_CLK_TIMER3>,
 437                                  <&clkgen JH7110_TIMER_CLK_APB>;
 438                         clock-names = "timer0", "timer1",
 439                                       "timer2", "timer3", "apb_clk";
 440                         resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
 441                                  <&rstgen RSTN_U0_TIMER_TIMER1>,
 442                                  <&rstgen RSTN_U0_TIMER_TIMER2>,
 443                                  <&rstgen RSTN_U0_TIMER_TIMER3>,
 444                                  <&rstgen RSTN_U0_TIMER_APB>;
 445                         reset-names = "timer0", "timer1",
 446                                       "timer2", "timer3", "apb_rst";
 447                         clock-frequency = <24000000>;
 448                         status = "okay";
 449                 };
 450
 451                 wdog: wdog@13070000 {
 452                         compatible = "starfive,jh7110-wdt";
 453                         reg = <0x0 0x13070000 0x0 0x10000>;
 454                         interrupts = <68>;
 455                         interrupt-names = "wdog";
 456                         clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
 457                                  <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
 458                         clock-names = "core_clk", "apb_clk";
 459                         resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
 460                                  <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
 461                         reset-names = "rst_apb", "rst_core";
 462                         timeout-sec = <15>;
 463                         status = "okay";
 464                 };
 465
 466                 rtc: rtc@17040000 {
 467                         compatible = "starfive,jh7110-rtc";
 468                         reg = <0x0 0x17040000 0x0 0x10000>;
 469                         interrupts = <10>, <11>, <12>;
 470                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 471                         clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
 472                                  <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 473                         clock-names = "pclk", "cal_clk";
 474                         resets = <&rstgen RSTN_U0_RTC_HMS_OSC32K>,
 475                                  <&rstgen RSTN_U0_RTC_HMS_APB>,
 476                                  <&rstgen RSTN_U0_RTC_HMS_CAL>;
 477                         reset-names = "rst_osc", "rst_apb", "rst_cal";
 478                         rtc,cal-clock-freq = <1000000>;
 479                         status = "okay";
 480                 };
 481
 482                 pwrc: power-controller@17030000 {
 483                         compatible = "starfive,jh7110-pmu";
 484                         reg = <0x0 0x17030000 0x0 0x10000>;
 485                         interrupts = <111>;
 486                         #power-domain-cells = <1>;
 487                         status = "okay";
 488                 };
 489
 490                 uart0: serial@10000000 {
 491                         compatible = "snps,dw-apb-uart";
 492                         reg = <0x0 0x10000000 0x0 0x10000>;
 493                         reg-io-width = <4>;
 494                         reg-shift = <2>;
 495                         clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 496                                  <&clkgen JH7110_UART0_CLK_APB>;
 497                         clock-names = "baudclk", "apb_pclk";
 498                         resets = <&rstgen RSTN_U0_DW_UART_APB>,
 499                                 <&rstgen RSTN_U0_DW_UART_CORE>;
 500                         interrupts = <32>;
 501                         status = "disabled";
 502                 };
 503
 504                 uart1: serial@10010000 {
 505                         compatible = "snps,dw-apb-uart";
 506                         reg = <0x0 0x10010000 0x0 0x10000>;
 507                         reg-io-width = <4>;
 508                         reg-shift = <2>;
 509                         clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 510                                  <&clkgen JH7110_UART1_CLK_APB>;
 511                         clock-names = "baudclk", "apb_pclk";
 512                         resets = <&rstgen RSTN_U1_DW_UART_APB>,
 513                                 <&rstgen RSTN_U1_DW_UART_CORE>;
 514                         interrupts = <33>;
 515                         status = "disabled";
 516                 };
 517
 518                 uart2: serial@10020000 {
 519                         compatible = "snps,dw-apb-uart";
 520                         reg = <0x0 0x10020000 0x0 0x10000>;
 521                         reg-io-width = <4>;
 522                         reg-shift = <2>;
 523                         clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 524                                  <&clkgen JH7110_UART2_CLK_APB>;
 525                         clock-names = "baudclk", "apb_pclk";
 526                         resets = <&rstgen RSTN_U2_DW_UART_APB>,
 527                                 <&rstgen RSTN_U2_DW_UART_CORE>;
 528                         interrupts = <34>;
 529                         status = "disabled";
 530                 };
 531
 532                 uart3: serial@12000000 {
 533                         compatible = "snps,dw-apb-uart";
 534                         reg = <0x0 0x12000000 0x0 0x10000>;
 535                         reg-io-width = <4>;
 536                         reg-shift = <2>;
 537                         clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 538                                  <&clkgen JH7110_UART3_CLK_APB>;
 539                         clock-names = "baudclk", "apb_pclk";
 540                         resets = <&rstgen RSTN_U3_DW_UART_APB>,
 541                                 <&rstgen RSTN_U3_DW_UART_CORE>;
 542                         interrupts = <45>;
 543                         status = "disabled";
 544                 };
 545
 546                 uart4: serial@12010000 {
 547                         compatible = "snps,dw-apb-uart";
 548                         reg = <0x0 0x12010000 0x0 0x10000>;
 549                         reg-io-width = <4>;
 550                         reg-shift = <2>;
 551                         clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 552                                  <&clkgen JH7110_UART4_CLK_APB>;
 553                         clock-names = "baudclk", "apb_pclk";
 554                         resets = <&rstgen RSTN_U4_DW_UART_APB>,
 555                                 <&rstgen RSTN_U4_DW_UART_CORE>;
 556                         interrupts = <46>;
 557                         status = "disabled";
 558                 };
 559
 560                 uart5: serial@12020000 {
 561                         compatible = "snps,dw-apb-uart";
 562                         reg = <0x0 0x12020000 0x0 0x10000>;
 563                         reg-io-width = <4>;
 564                         reg-shift = <2>;
 565                         clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 566                                  <&clkgen JH7110_UART5_CLK_APB>;
 567                         clock-names = "baudclk", "apb_pclk";
 568                         resets = <&rstgen RSTN_U5_DW_UART_APB>,
 569                                 <&rstgen RSTN_U5_DW_UART_CORE>;
 570                         interrupts = <47>;
 571                         status = "disabled";
 572                 };
 573
 574                 dma: dma-controller@16050000 {
 575                         compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a";
 576                         reg = <0x0 0x16050000 0x0 0x10000>;
 577                         clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
 578                                  <&clkgen JH7110_DMA1P_CLK_AHB>,
 579                                  <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>;
 580                         clock-names = "core-clk", "cfgr-clk", "stg_clk";
 581                         resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
 582                                  <&rstgen RSTN_U0_DW_DMA1P_AHB>,
 583                                  <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
 584                         reset-names = "rst_axi", "rst_ahb", "rst_stg";
 585                         interrupts = <73>;
 586                         #dma-cells = <2>;
 587                         dma-channels = <4>;
 588                         snps,dma-masters = <1>;
 589                         snps,data-width = <3>;
 590                         snps,num-hs-if = <56>;
 591                         snps,block-size = <65536 65536 65536 65536>;
 592                         snps,priority = <0 1 2 3>;
 593                         snps,axi-max-burst-len = <16>;
 594                         status = "disabled";
 595                 };
 596
 597                 gpio: gpio@13040000 {
 598                         compatible = "starfive,jh7110-sys-pinctrl";
 599                         reg = <0x0 0x13040000 0x0 0x10000>;
 600                         reg-names = "control";
 601                         clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
 602                         resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
 603                         interrupts = <86>;
 604                         interrupt-controller;
 605                         #gpio-cells = <2>;
 606                         ngpios = <64>;
 607                         status = "okay";
 608                 };
 609
 610                 gpioa: gpio@17020000 {
 611                         compatible = "starfive,jh7110-aon-pinctrl";
 612                         reg = <0x0 0x17020000 0x0 0x10000>;
 613                         reg-names = "control";
 614                         resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
 615                         interrupts = <85>;
 616                         interrupt-controller;
 617                         #gpio-cells = <2>;
 618                         ngpios = <4>;
 619                         status = "okay";
 620                 };
 621
 622                 sfctemp: tmon@120e0000  {
 623                         compatible = "starfive,jh7110-temp";
 624                         reg = <0x0 0x120e0000 0x0 0x10000>;
 625                         interrupts = <81>;
 626                         clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
 627                                  <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
 628                         clock-names = "sense", "bus";
 629                         resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
 630                                  <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
 631                         reset-names = "sense", "bus";
 632                         #thermal-sensor-cells = <0>;
 633                         status = "disabled";
 634                 };
 635
 636                 thermal-zones {
 637                         cpu-thermal {
 638                                 polling-delay-passive = <250>;
 639                                 polling-delay = <15000>;
 640
 641                                 thermal-sensors = <&sfctemp>;
 642
 643                                 cooling-maps {
 644                                 };
 645
 646                                 trips {
 647                                         cpu_alert0: cpu_alert0 {
 648                                                 /* milliCelsius */
 649                                                 temperature = <75000>;
 650                                                 hysteresis = <2000>;
 651                                                 type = "passive";
 652                                         };
 653
 654                                         cpu_crit: cpu_crit {
 655                                                 /* milliCelsius */
 656                                                 temperature = <90000>;
 657                                                 hysteresis = <2000>;
 658                                                 type = "critical";
 659                                         };
 660                                 };
 661                         };
 662                 };
 663
 664                 trng: trng@1600C000 {
 665                         compatible = "starfive,jh7110-trng";
 666                         reg = <0x0 0x1600C000 0x0 0x4000>;
 667                         clocks = <&clkgen JH7110_SEC_HCLK>,
 668                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 669                         clock-names = "hclk", "ahb";
 670                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 671                         interrupts = <30>;
 672                         status = "disabled";
 673                 };
 674
 675                 sec_dma: sec_dma@16008000 {
 676                         compatible = "arm,pl080", "arm,primecell";
 677                         arm,primecell-periphid = <0x00041080>;
 678                         reg = <0x0 0x16008000 0x0 0x4000>;
 679                         reg-names = "sec_dma";
 680                         interrupts = <29>;
 681                         clocks = <&clkgen JH7110_SEC_HCLK>,
 682                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 683                         clock-names = "sec_hclk","apb_pclk";
 684                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 685                         reset-names = "sec_hre";
 686                         lli-bus-interface-ahb1;
 687                         mem-bus-interface-ahb1;
 688                         memcpy-burst-size = <256>;
 689                         memcpy-bus-width = <32>;
 690                         #dma-cells = <2>;
 691                         status = "disabled";
 692                 };
 693
 694                 crypto: crypto@16000000 {
 695                         compatible = "starfive,jh7110-sec";
 696                         reg = <0x0 0x16000000 0x0 0x4000>,
 697                               <0x0 0x16008000 0x0 0x4000>;
 698                         reg-names = "secreg","secdma";
 699                         interrupts = <28>, <29>;
 700                         interrupt-names = "secirq", "dmairq";
 701                         clocks = <&clkgen JH7110_SEC_HCLK>,
 702                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 703                         clock-names = "sec_hclk","sec_ahb";
 704                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 705                         reset-names = "sec_hre";
 706                         enable-side-channel-mitigation = "true";
 707                         enable-dma = "true";
 708                         dmas = <&sec_dma 1 2>,
 709                                <&sec_dma 0 2>;
 710                         dma-names = "sec_m","sec_p";
 711                         status = "disabled";
 712                 };
 713
 714                 i2c0: i2c@10030000 {
 715                         compatible = "snps,designware-i2c";
 716                         reg = <0x0 0x10030000 0x0 0x10000>;
 717                         clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
 718                                  <&clkgen JH7110_I2C0_CLK_APB>;
 719                         clock-names = "ref", "pclk";
 720                         resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 721                         interrupts = <35>;
 722                         #address-cells = <1>;
 723                         #size-cells = <0>;
 724                         status = "disabled";
 725                 };
 726
 727                 i2c1: i2c@10040000 {
 728                         compatible = "snps,designware-i2c";
 729                         reg = <0x0 0x10040000 0x0 0x10000>;
 730                         clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
 731                                  <&clkgen JH7110_I2C1_CLK_APB>;
 732                         clock-names = "ref", "pclk";
 733                         resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 734                         interrupts = <36>;
 735                         #address-cells = <1>;
 736                         #size-cells = <0>;
 737                         status = "disabled";
 738                 };
 739
 740                 i2c2: i2c@10050000 {
 741                         compatible = "snps,designware-i2c";
 742                         reg = <0x0 0x10050000 0x0 0x10000>;
 743                         clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
 744                                  <&clkgen JH7110_I2C2_CLK_APB>;
 745                         clock-names = "ref", "pclk";
 746                         resets = <&rstgen RSTN_U2_DW_I2C_APB>;
 747                         interrupts = <37>;
 748                         #address-cells = <1>;
 749                         #size-cells = <0>;
 750                         status = "disabled";
 751                 };
 752
 753                 i2c3: i2c@12030000 {
 754                         compatible = "snps,designware-i2c";
 755                         reg = <0x0 0x12030000 0x0 0x10000>;
 756                         clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
 757                                  <&clkgen JH7110_I2C3_CLK_APB>;
 758                         clock-names = "ref", "pclk";
 759                         resets = <&rstgen RSTN_U3_DW_I2C_APB>;
 760                         interrupts = <48>;
 761                         #address-cells = <1>;
 762                         #size-cells = <0>;
 763                         status = "disabled";
 764                 };
 765
 766                 i2c4: i2c@12040000 {
 767                         compatible = "snps,designware-i2c";
 768                         reg = <0x0 0x12040000 0x0 0x10000>;
 769                         clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
 770                                  <&clkgen JH7110_I2C4_CLK_APB>;
 771                         clock-names = "ref", "pclk";
 772                         resets = <&rstgen RSTN_U4_DW_I2C_APB>;
 773                         interrupts = <49>;
 774                         #address-cells = <1>;
 775                         #size-cells = <0>;
 776                         status = "disabled";
 777                 };
 778
 779                 i2c5: i2c@12050000 {
 780                         compatible = "snps,designware-i2c";
 781                         reg = <0x0 0x12050000 0x0 0x10000>;
 782                         clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
 783                                  <&clkgen JH7110_I2C5_CLK_APB>;
 784                         clock-names = "ref", "pclk";
 785                         resets = <&rstgen RSTN_U5_DW_I2C_APB>;
 786                         interrupts = <50>;
 787                         #address-cells = <1>;
 788                         #size-cells = <0>;
 789                         status = "disabled";
 790                 };
 791
 792                 i2c6: i2c@12060000 {
 793                         compatible = "snps,designware-i2c";
 794                         reg = <0x0 0x12060000 0x0 0x10000>;
 795                         clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
 796                                  <&clkgen JH7110_I2C6_CLK_APB>;
 797                         clock-names = "ref", "pclk";
 798                         resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 799                         interrupts = <51>;
 800                         #address-cells = <1>;
 801                         #size-cells = <0>;
 802                         status = "disabled";
 803                 };
 804
 805                 /* unremovable emmc as mmcblk0 */
 806                 sdio0: sdio0@16010000 {
 807                         compatible = "starfive,jh7110-sdio";
 808                         reg = <0x0 0x16010000 0x0 0x10000>;
 809                         clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
 810                                  <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 811                         clock-names = "biu","ciu";
 812                         resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
 813                         reset-names = "reset";
 814                         interrupts = <74>;
 815                         fifo-depth = <32>;
 816                         fifo-watermark-aligned;
 817                         data-addr = <0>;
 818                         starfive,sys-syscon = <&sys_syscon 0x14 0x1a 0x7c000000>;
 819                         status = "disabled";
 820                 };
 821
 822                 sdio1: sdio1@16020000 {
 823                         compatible = "starfive,jh7110-sdio";
 824                         reg = <0x0 0x16020000 0x0 0x10000>;
 825                         clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
 826                                  <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 827                         clock-names = "biu","ciu";
 828                         resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
 829                         reset-names = "reset";
 830                         interrupts = <75>;
 831                         fifo-depth = <32>;
 832                         fifo-watermark-aligned;
 833                         data-addr = <0>;
 834                         starfive,sys-syscon = <&sys_syscon 0x9c 0x1 0x3e>;
 835                         status = "disabled";
 836                 };
 837
 838                 vin_sysctl: vin_sysctl@19800000 {
 839                         compatible = "starfive,jh7110-vin";
 840                         reg = <0x0 0x19800000 0x0 0x10000>,
 841                                 <0x0 0x19810000 0x0 0x10000>,
 842                                 <0x0 0x19820000 0x0 0x10000>,
 843                                 <0x0 0x19840000 0x0 0x10000>,
 844                                 <0x0 0x19870000 0x0 0x30000>,
 845                                 <0x0 0x11840000 0x0 0x10000>,
 846                                 <0x0 0x17030000 0x0 0x10000>,
 847                                 <0x0 0x13020000 0x0 0x10000>;
 848                         reg-names = "csi2rx", "vclk", "vrst", "sctrl",
 849                                 "isp", "trst", "pmu", "syscrg";
 850                         clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
 851                                  <&clkisp JH7110_U0_VIN_PCLK>,
 852                                  <&clkisp JH7110_U0_VIN_SYS_CLK>,
 853                                  <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
 854                                  <&clkisp JH7110_DVP_INV>,
 855                                  <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
 856                                  <&clkisp JH7110_MIPI_RX0_PXL>,
 857                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
 858                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
 859                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
 860                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
 861                                  <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
 862                                  <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
 863                                  <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
 864                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 865                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
 866                         clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
 867                                 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
 868                                 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
 869                                 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
 870                                 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
 871                                 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
 872                                 "clk_ispcore_2x", "clk_isp_axi";
 873                         resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
 874                                  <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
 875                                  <&rstgen RSTN_U0_VIN_N_PCLK>,
 876                                  <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
 877                                  <&rstgen RSTN_U0_VIN_P_AXIRD>,
 878                                  <&rstgen RSTN_U0_VIN_P_AXIWR>,
 879                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
 880                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
 881                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
 882                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
 883                                  <&rstgen RSTN_U0_M31DPHY_HW>,
 884                                  <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
 885                                  <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 886                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
 887                         reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
 888                                 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
 889                                 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
 890                                 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
 891                                 "rst_isp_top_n", "rst_isp_top_axi";
 892                         starfive,aon-syscon = <&aon_syscon 0x00>;
 893                         power-domains = <&pwrc JH7110_PD_ISP>;
 894                         /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
 895                         interrupts = <92 87 88 89 90>;
 896                         status = "disabled";
 897                 };
 898
 899                 jpu: jpu@11900000 {
 900                         compatible = "starfive,jpu";
 901                         reg = <0x0 0x13090000 0x0 0x300>;
 902                         interrupts = <14>;
 903                         clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
 904                                  <&clkgen JH7110_CODAJ12_CLK_CORE>,
 905                                  <&clkgen JH7110_CODAJ12_CLK_APB>,
 906                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 907                         clock-names = "axi_clk", "core_clk",
 908                                       "apb_clk", "noc_bus";
 909                         resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 910                                  <&rstgen RSTN_U0_CODAJ12_CORE>,
 911                                  <&rstgen RSTN_U0_CODAJ12_APB>;
 912                         reset-names = "rst_axi", "rst_core", "rst_apb";
 913                         power-domains = <&pwrc JH7110_PD_VDEC>;
 914                         status = "disabled";
 915                 };
 916
 917                 vpu_dec: vpu_dec@130A0000 {
 918                         compatible = "starfive,vdec";
 919                         reg = <0x0 0x130A0000 0x0 0x10000>;
 920                         interrupts = <13>;
 921                         clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
 922                                  <&clkgen JH7110_WAVE511_CLK_BPU>,
 923                                  <&clkgen JH7110_WAVE511_CLK_VCE>,
 924                                  <&clkgen JH7110_WAVE511_CLK_APB>,
 925                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 926                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 927                                       "apb_clk", "noc_bus";
 928                         resets = <&rstgen RSTN_U0_WAVE511_AXI>,
 929                                 <&rstgen RSTN_U0_WAVE511_BPU>,
 930                                 <&rstgen RSTN_U0_WAVE511_VCE>,
 931                                 <&rstgen RSTN_U0_WAVE511_APB>,
 932                                 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
 933                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 934                                       "rst_apb", "rst_sram";
 935                         starfive,vdec_noc_ctrl;
 936                         power-domains = <&pwrc JH7110_PD_VDEC>;
 937                         status = "disabled";
 938                 };
 939
 940                 vpu_enc: vpu_enc@130B0000 {
 941                         compatible = "starfive,venc";
 942                         reg = <0x0 0x130B0000 0x0 0x10000>;
 943                         interrupts = <15>;
 944                         clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
 945                                  <&clkgen JH7110_WAVE420L_CLK_BPU>,
 946                                  <&clkgen JH7110_WAVE420L_CLK_VCE>,
 947                                  <&clkgen JH7110_WAVE420L_CLK_APB>,
 948                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 949                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 950                                       "apb_clk", "noc_bus";
 951                         resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
 952                                  <&rstgen RSTN_U0_WAVE420L_BPU>,
 953                                  <&rstgen RSTN_U0_WAVE420L_VCE>,
 954                                  <&rstgen RSTN_U0_WAVE420L_APB>,
 955                                  <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 956                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 957                                       "rst_apb", "rst_sram";
 958                         starfive,venc_noc_ctrl;
 959                         power-domains = <&pwrc JH7110_PD_VENC>;
 960                         status = "disabled";
 961                 };
 962
 963                 rstgen: reset-controller {
 964                         compatible = "starfive,jh7110-reset";
 965                         reg = <0x0 0x13020000 0x0 0x10000>,
 966                                 <0x0 0x10230000 0x0 0x10000>,
 967                                 <0x0 0x17000000 0x0 0x10000>,
 968                                 <0x0 0x19810000 0x0 0x10000>,
 969                                 <0x0 0x295C0000 0x0 0x10000>;
 970                         reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
 971                         #reset-cells = <1>;
 972                         status = "okay";
 973                 };
 974
 975                 stmmac_axi_setup: stmmac-axi-config {
 976                         snps,wr_osr_lmt = <0xf>;
 977                         snps,rd_osr_lmt = <0xf>;
 978                         snps,blen = <256 128 64 32 0 0 0>;
 979                 };
 980
 981                 gmac0: ethernet@16030000 {
 982                         compatible = "starfive,dwmac","snps,dwmac-5.10a";
 983                         reg = <0x0 0x16030000 0x0 0x10000>;
 984                         clock-names = "gtx",
 985                                 "tx",
 986                                 "ptp_ref",
 987                                 "stmmaceth",
 988                                 "pclk",
 989                                 "gtxc";
 990                         clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
 991                                  <&clkgen JH7110_U0_GMAC5_CLK_TX>,
 992                                  <&clkgen JH7110_GMAC0_PTP>,
 993                                  <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
 994                                  <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
 995                                  <&clkgen JH7110_GMAC0_GTXC>;
 996                         resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
 997                                  <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
 998                         reset-names = "ahb", "stmmaceth";
 999                         interrupts = <7>, <6>, <5> ;
1000                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1001                         max-frame-size = <9000>;
1002                         phy-mode = "rgmii-id";
1003                         snps,multicast-filter-bins = <64>;
1004                         snps,perfect-filter-entries = <128>;
1005                         rx-fifo-depth = <2048>;
1006                         tx-fifo-depth = <2048>;
1007                         snps,fixed-burst;
1008                         snps,no-pbl-x8;
1009                         snps,force_thresh_dma_mode;
1010                         snps,axi-config = <&stmmac_axi_setup>;
1011                         snps,tso;
1012                         snps,en-tx-lpi-clockgating;
1013                         snps,en-lpi;
1014                         snps,write-requests = <4>;
1015                         snps,read-requests = <4>;
1016                         snps,burst-map = <0x7>;
1017                         snps,txpbl = <16>;
1018                         snps,rxpbl = <16>;
1019                         status = "disabled";
1020                 };
1021
1022                 gmac1: ethernet@16040000 {
1023                         compatible = "starfive,dwmac","snps,dwmac-5.10a";
1024                         reg = <0x0 0x16040000 0x0 0x10000>;
1025                         clock-names = "gtx",
1026                                 "tx",
1027                                 "ptp_ref",
1028                                 "stmmaceth",
1029                                 "pclk",
1030                                 "gtxc";
1031                         clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
1032                                  <&clkgen JH7110_GMAC5_CLK_TX>,
1033                                  <&clkgen JH7110_GMAC5_CLK_PTP>,
1034                                  <&clkgen JH7110_GMAC5_CLK_AHB>,
1035                                  <&clkgen JH7110_GMAC5_CLK_AXI>,
1036                                  <&clkgen JH7110_GMAC1_GTXC>;
1037                         resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
1038                                  <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
1039                         reset-names = "ahb", "stmmaceth";
1040                         interrupts = <78>, <77>, <76> ;
1041                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1042                         max-frame-size = <9000>;
1043                         phy-mode = "rgmii-id";
1044                         snps,multicast-filter-bins = <64>;
1045                         snps,perfect-filter-entries = <128>;
1046                         rx-fifo-depth = <2048>;
1047                         tx-fifo-depth = <2048>;
1048                         snps,fixed-burst;
1049                         snps,no-pbl-x8;
1050                         snps,force_thresh_dma_mode;
1051                         snps,axi-config = <&stmmac_axi_setup>;
1052                         snps,tso;
1053                         snps,en-tx-lpi-clockgating;
1054                         snps,en-lpi;
1055                         snps,write-requests = <4>;
1056                         snps,read-requests = <4>;
1057                         snps,burst-map = <0x7>;
1058                         snps,txpbl = <16>;
1059                         snps,rxpbl = <16>;
1060                         status = "disabled";
1061                 };
1062
1063                 gpu: gpu@18000000 {
1064                         compatible = "img-gpu";
1065                         reg = <0x0 0x18000000 0x0 0x100000>,
1066                                 <0x0 0x130C000 0x0 0x10000>;
1067                         clocks = <&clkgen JH7110_GPU_CORE>,
1068                                  <&clkgen JH7110_GPU_CLK_APB>,
1069                                  <&clkgen JH7110_GPU_RTC_TOGGLE>,
1070                                  <&clkgen JH7110_GPU_CORE_CLK>,
1071                                  <&clkgen JH7110_GPU_SYS_CLK>,
1072                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
1073                         clock-names = "clk_bv", "clk_apb", "clk_rtc",
1074                                         "clk_core", "clk_sys", "clk_axi";
1075                         resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1076                                  <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1077                         reset-names = "rst_apb", "rst_doma";
1078                         power-domains = <&pwrc JH7110_PD_GPUA>;
1079                         interrupts = <82>;
1080                         current-clock = <8000000>;
1081                         status = "disabled";
1082                 };
1083
1084                 can0: can@130d0000 {
1085                         compatible = "starfive,jh7110-can", "ipms,can";
1086                         reg = <0x0 0x130d0000 0x0 0x1000>;
1087                         interrupts = <112>;
1088                         clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1089                                  <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1090                                  <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1091                         clock-names = "apb_clk", "core_clk", "timer_clk";
1092                         resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1093                                  <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1094                                  <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1095                         reset-names = "rst_apb", "rst_core", "rst_timer";
1096                         frequency = <40000000>;
1097                         starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1098                         syscon,can_or_canfd = <0>;
1099                         status = "disabled";
1100                 };
1101
1102                 can1: can@130e0000 {
1103                         compatible = "starfive,jh7110-can", "ipms,can";
1104                         reg = <0x0 0x130e0000 0x0 0x1000>;
1105                         interrupts = <113>;
1106                         clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1107                                  <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1108                                  <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1109                         clock-names = "apb_clk", "core_clk", "timer_clk";
1110                         resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1111                                  <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1112                                  <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1113                         reset-names = "rst_apb", "rst_core", "rst_timer";
1114                         frequency = <40000000>;
1115                         starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1116                         syscon,can_or_canfd = <1>;
1117                         status = "disabled";
1118                 };
1119
1120                 tdm: tdm@10090000 {
1121                         compatible = "starfive,jh7110-tdm";
1122                         reg = <0x0 0x10090000 0x0 0x1000>;
1123                         reg-names = "tdm";
1124                         clocks = <&clkgen JH7110_TDM_CLK_AHB>,
1125                                  <&clkgen JH7110_TDM_CLK_APB>,
1126                                  <&clkgen JH7110_TDM_INTERNAL>,
1127                                  <&tdm_ext>,
1128                                  <&clkgen JH7110_TDM_CLK_TDM>,
1129                                  <&clkgen JH7110_MCLK_INNER>;
1130                         clock-names = "clk_tdm_ahb", "clk_tdm_apb",
1131                                       "clk_tdm_internal", "clk_tdm_ext",
1132                                       "clk_tdm", "mclk_inner";
1133                         resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1134                                  <&rstgen RSTN_U0_TDM16SLOT_APB>,
1135                                  <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1136                         reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1137                         dmas = <&dma 20 1>, <&dma 21 1>;
1138                         dma-names = "rx","tx";
1139                         #sound-dai-cells = <0>;
1140                         status = "disabled";
1141                 };
1142
1143                 spdif0: spdif0@100a0000 {
1144                         compatible = "starfive,jh7110-spdif";
1145                         reg = <0x0 0x100a0000 0x0 0x1000>;
1146                         clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1147                                  <&clkgen JH7110_SPDIF_CLK_CORE>,
1148                                  <&clkgen JH7110_AUDIO_ROOT>,
1149                                  <&clkgen JH7110_MCLK_INNER>,
1150                                  <&mclk_ext>, <&clkgen JH7110_MCLK>;
1151                         clock-names = "spdif-apb", "spdif-core",
1152                                       "audroot", "mclk_inner",
1153                                       "mclk_ext", "mclk";
1154                         resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1155                         reset-names = "rst_apb";
1156                         interrupts = <84>;
1157                         interrupt-names = "tx";
1158                         #sound-dai-cells = <0>;
1159                         status = "disabled";
1160                 };
1161
1162                 pwmdac: pwmdac@100b0000 {
1163                         compatible = "starfive,jh7110-pwmdac";
1164                         reg = <0x0 0x100b0000 0x0 0x1000>;
1165                         clocks = <&clkgen JH7110_APB0>,
1166                                  <&clkgen JH7110_PWMDAC_CLK_APB>,
1167                                  <&clkgen JH7110_PWMDAC_CLK_CORE>;
1168                         clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1169                         resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1170                         reset-names = "rst-apb";
1171                         dmas = <&dma 22 1>;
1172                         dma-names = "tx";
1173                         #sound-dai-cells = <0>;
1174                         status = "disabled";
1175                 };
1176
1177                 i2stx: i2stx@100c0000 {
1178                         compatible = "snps,designware-i2stx";
1179                         reg = <0x0 0x100c0000 0x0 0x1000>;
1180                         interrupt-names = "tx";
1181                         #sound-dai-cells = <0>;
1182                         dmas = <&dma 28 1>;
1183                         dma-names = "rx";
1184                         status = "disabled";
1185                 };
1186
1187                 pdm: pdm@100d0000 {
1188                         compatible = "starfive,jh7110-pdm";
1189                         reg = <0x0 0x100d0000 0x0 0x1000>;
1190                         reg-names = "pdm";
1191                         clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1192                                  <&clkgen JH7110_PDM_CLK_APB>,
1193                                  <&clkgen JH7110_MCLK>,
1194                                  <&mclk_ext>;
1195                         clock-names = "pdm_mclk",
1196                                       "pdm_apb", "clk_mclk",
1197                                       "mclk_ext";
1198                         resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1199                                  <&rstgen RSTN_U0_PDM_4MIC_APB>;
1200                         reset-names = "pdm_dmic", "pdm_apb";
1201                         #sound-dai-cells = <0>;
1202                 };
1203
1204                 i2srx_mst: i2srx_mst@100e0000 {
1205                         compatible = "starfive,jh7110-i2srx-master";
1206                         reg = <0x0 0x100e0000 0x0 0x1000>;
1207                         clocks = <&clkgen JH7110_APB0>,
1208                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1209                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1210                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1211                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1212                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>,
1213                                  <&clkgen JH7110_MCLK>,
1214                                  <&mclk_ext>;
1215                         clock-names = "apb0", "i2srx_apb",
1216                                       "i2srx_bclk_mst", "i2srx_lrck_mst",
1217                                       "i2srx_bclk", "i2srx_lrck",
1218                                       "mclk", "mclk_ext";
1219                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1220                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1221                         reset-names = "rst_apb_rx", "rst_bclk_rx";
1222                         dmas = <&dma 24 1>;
1223                         dma-names = "rx";
1224                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1225                         #sound-dai-cells = <0>;
1226                         status = "disabled";
1227                 };
1228
1229                 i2srx_3ch: i2srx_3ch@100e0000 {
1230                         compatible = "starfive,jh7110-i2srx", "snps,designware-i2s";
1231                         reg = <0x0 0x100e0000 0x0 0x1000>;
1232                         clocks = <&clkgen JH7110_APB0>,
1233                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1234                                  <&clkgen JH7110_AUDIO_ROOT>,
1235                                  <&clkgen JH7110_MCLK_INNER>,
1236                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1237                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1238                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1239                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>,
1240                                  <&clkgen JH7110_MCLK>,
1241                                  <&mclk_ext>,
1242                                  <&i2srx_bclk_ext>,
1243                                  <&i2srx_lrck_ext>;
1244                         clock-names = "apb0", "3ch-apb",
1245                                       "audioroot", "mclk-inner",
1246                                       "bclk_mst", "3ch-lrck",
1247                                       "rx-bclk", "rx-lrck",
1248                                       "mclk", "mclk_ext",
1249                                       "bclk-ext", "lrck-ext";
1250                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1251                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1252                         dmas = <&dma 24 1>;
1253                         dma-names = "rx";
1254                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1255                         #sound-dai-cells = <0>;
1256                         status = "disabled";
1257                 };
1258
1259                 i2stx_4ch0: i2stx_4ch0@120b0000 {
1260                         compatible = "starfive,jh7110-i2stx-4ch0", "snps,designware-i2s";
1261                         reg = <0x0 0x120b0000 0x0 0x1000>;
1262                         clocks = <&clkgen JH7110_MCLK_INNER>,
1263                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1264                                  <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1265                                  <&clkgen JH7110_MCLK>,
1266                                  <&clkgen JH7110_I2STX0_4CHBCLK>,
1267                                  <&clkgen JH7110_I2STX0_4CHLRCK>,
1268                                  <&clkgen JH7110_I2STX0_4CHCLK_APB>,
1269                                  <&mclk_ext>;
1270                         clock-names = "inner", "bclk-mst",
1271                                         "lrck-mst", "mclk",
1272                                         "bclk0", "lrck0",
1273                                         "i2s_apb", "mclk_ext";
1274                         resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1275                                  <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1276                         reset-names = "rst_apb", "rst_bclk";
1277                         dmas = <&dma 47 1>;
1278                         dma-names = "tx";
1279                         #sound-dai-cells = <0>;
1280                         status = "disabled";
1281                 };
1282
1283                 i2stx_4ch1: i2stx_4ch1@120c0000 {
1284                         compatible = "starfive,jh7110-i2stx-4ch1", "snps,designware-i2s";
1285                         reg = <0x0 0x120c0000 0x0 0x1000>;
1286                         clocks = <&clkgen JH7110_AUDIO_ROOT>,
1287                                  <&clkgen JH7110_MCLK_INNER>,
1288                                  <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1289                                  <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1290                                  <&clkgen JH7110_MCLK>,
1291                                  <&clkgen JH7110_I2STX1_4CHBCLK>,
1292                                  <&clkgen JH7110_I2STX1_4CHLRCK>,
1293                                  <&clkgen JH7110_MCLK_OUT>,
1294                                  <&clkgen JH7110_APB0>,
1295                                  <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1296                                  <&mclk_ext>,
1297                                  <&i2stx_bclk_ext>,
1298                                  <&i2stx_lrck_ext>;
1299                         clock-names = "audroot", "mclk_inner", "bclk_mst",
1300                                       "lrck_mst", "mclk", "4chbclk",
1301                                       "4chlrck", "mclk_out",
1302                                       "apb0", "clk_apb",
1303                                       "mclk_ext", "bclk_ext", "lrck_ext";
1304                         resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1305                                  <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1306                         dmas = <&dma 48 1>;
1307                         dma-names = "tx";
1308                         #sound-dai-cells = <0>;
1309                         status = "disabled";
1310                 };
1311
1312                 ptc: pwm@120d0000 {
1313                         compatible = "starfive,jh7110-pwm";
1314                         reg = <0x0 0x120d0000 0x0 0x10000>;
1315                         reg-names = "control";
1316                         clocks = <&clkgen JH7110_PWM_CLK_APB>;
1317                         resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1318                         starfive,approx-freq = <2000000>;
1319                         #pwm-cells=<3>;
1320                         starfive,npwm = <8>;
1321                         status = "disabled";
1322                 };
1323
1324                 spdif_transmitter: spdif_transmitter {
1325                         compatible = "linux,spdif-dit";
1326                         #sound-dai-cells = <0>;
1327                         status = "disabled";
1328                 };
1329
1330                 pwmdac_codec: pwmdac-transmitter {
1331                         compatible = "starfive,jh7110-pwmdac-dit";
1332                         #sound-dai-cells = <0>;
1333                         status = "disabled";
1334                 };
1335
1336                 dmic_codec: dmic_codec {
1337                         compatible = "dmic-codec";
1338                         #sound-dai-cells = <0>;
1339                         status = "disabled";
1340                 };
1341
1342                 spi0: spi@10060000 {
1343                         compatible = "arm,pl022", "arm,primecell";
1344                         reg = <0x0 0x10060000 0x0 0x10000>;
1345                         clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1346                         clock-names = "apb_pclk";
1347                         resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1348                         reset-names = "rst_apb";
1349                         interrupts = <38>;
1350                         /* shortage of dma channel that not be used */
1351                         /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1352                         /*dma-names = "rx","tx";*/
1353                         arm,primecell-periphid = <0x00041022>;
1354                         num-cs = <1>;
1355                         #address-cells = <1>;
1356                         #size-cells = <0>;
1357                         status = "disabled";
1358                 };
1359
1360                 spi1: spi@10070000 {
1361                         compatible = "arm,pl022", "arm,primecell";
1362                         reg = <0x0 0x10070000 0x0 0x10000>;
1363                         clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1364                         clock-names = "apb_pclk";
1365                         resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1366                         reset-names = "rst_apb";
1367                         interrupts = <39>;
1368                         /* shortage of dma channel that not be used */
1369                         /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1370                         /*dma-names = "rx","tx";*/
1371                         arm,primecell-periphid = <0x00041022>;
1372                         num-cs = <1>;
1373                         #address-cells = <1>;
1374                         #size-cells = <0>;
1375                         status = "disabled";
1376                 };
1377
1378                 spi2: spi@10080000 {
1379                         compatible = "arm,pl022", "arm,primecell";
1380                         reg = <0x0 0x10080000 0x0 0x10000>;
1381                         clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1382                         clock-names = "apb_pclk";
1383                         resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1384                         reset-names = "rst_apb";
1385                         interrupts = <40>;
1386                         /* shortage of dma channel that not be used */
1387                         /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1388                         /*dma-names = "rx","tx";*/
1389                         arm,primecell-periphid = <0x00041022>;
1390                         num-cs = <1>;
1391                         #address-cells = <1>;
1392                         #size-cells = <0>;
1393                         status = "disabled";
1394                 };
1395
1396                 spi3: spi@12070000 {
1397                         compatible = "arm,pl022", "arm,primecell";
1398                         reg = <0x0 0x12070000 0x0 0x10000>;
1399                         clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1400                         clock-names = "apb_pclk";
1401                         resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1402                         reset-names = "rst_apb";
1403                         interrupts = <52>;
1404                         /* shortage of dma channel that not be used */
1405                         /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1406                         /*dma-names = "rx","tx";*/
1407                         arm,primecell-periphid = <0x00041022>;
1408                         num-cs = <1>;
1409                         #address-cells = <1>;
1410                         #size-cells = <0>;
1411                         status = "disabled";
1412                 };
1413
1414                 spi4: spi@12080000 {
1415                         compatible = "arm,pl022", "arm,primecell";
1416                         reg = <0x0 0x12080000 0x0 0x10000>;
1417                         clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1418                         clock-names = "apb_pclk";
1419                         resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1420                         reset-names = "rst_apb";
1421                         interrupts = <53>;
1422                         /* shortage of dma channel that not be used */
1423                         /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1424                         /*dma-names = "rx","tx";*/
1425                         arm,primecell-periphid = <0x00041022>;
1426                         num-cs = <1>;
1427                         #address-cells = <1>;
1428                         #size-cells = <0>;
1429                         status = "disabled";
1430                 };
1431
1432                 spi5: spi@12090000 {
1433                         compatible = "arm,pl022", "arm,primecell";
1434                         reg = <0x0 0x12090000 0x0 0x10000>;
1435                         clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1436                         clock-names = "apb_pclk";
1437                         resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1438                         reset-names = "rst_apb";
1439                         interrupts = <54>;
1440                         /* shortage of dma channel that not be used */
1441                         /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1442                         /*dma-names = "rx","tx";*/
1443                         arm,primecell-periphid = <0x00041022>;
1444                         num-cs = <1>;
1445                         #address-cells = <1>;
1446                         #size-cells = <0>;
1447                         status = "disabled";
1448                 };
1449
1450                 spi6: spi@120A0000 {
1451                         compatible = "arm,pl022", "arm,primecell";
1452                         reg = <0x0 0x120A0000 0x0 0x10000>;
1453                         clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1454                         clock-names = "apb_pclk";
1455                         resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1456                         reset-names = "rst_apb";
1457                         interrupts = <55>;
1458                         /* shortage of dma channel that not be used */
1459                         /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1460                         /*dma-names = "rx","tx";*/
1461                         arm,primecell-periphid = <0x00041022>;
1462                         num-cs = <1>;
1463                         #address-cells = <1>;
1464                         #size-cells = <0>;
1465                         status = "disabled";
1466                 };
1467
1468                 pcie0: pcie@2B000000 {
1469                         compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1470                         #address-cells = <3>;
1471                         #size-cells = <2>;
1472                         #interrupt-cells = <1>;
1473                         reg = <0x0 0x2B000000 0x0 0x1000000
1474                                0x9 0x40000000 0x0 0x10000000>;
1475                         reg-names = "reg", "config";
1476                         device_type = "pci";
1477                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
1478                         starfive,phyctrl = <&phyctrl0 0x28 0x80>;
1479                         bus-range = <0x0 0xff>;
1480                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
1481                                  <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
1482                         msi-parent = <&plic>;
1483                         interrupts = <56>;
1484                         interrupt-controller;
1485                         interrupt-names = "msi";
1486                         interrupt-parent = <&plic>;
1487                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1488                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1489                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1490                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1491                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1492                         resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1493                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1494                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1495                                  <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1496                                  <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1497                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1498                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1499                                       "rst_brg", "rst_core", "rst_apb";
1500                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1501                                  <&clkgen JH7110_PCIE0_CLK_TL>,
1502                                  <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1503                                  <&clkgen JH7110_PCIE0_CLK_APB>;
1504                         clock-names = "noc", "tl", "axi_mst0", "apb";
1505                         status = "disabled";
1506                 };
1507
1508                 pcie1: pcie@2C000000 {
1509                         compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1510                         #address-cells = <3>;
1511                         #size-cells = <2>;
1512                         #interrupt-cells = <1>;
1513                         reg = <0x0 0x2C000000 0x0 0x1000000
1514                                0x9 0xc0000000 0x0 0x10000000>;
1515                         reg-names = "reg", "config";
1516                         device_type = "pci";
1517                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
1518                         starfive,phyctrl = <&phyctrl1 0x28 0x80>;
1519                         bus-range = <0x0 0xff>;
1520                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
1521                                  <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
1522                         msi-parent = <&plic>;
1523                         interrupts = <57>;
1524                         interrupt-controller;
1525                         interrupt-names = "msi";
1526                         interrupt-parent = <&plic>;
1527                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1528                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1529                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1530                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1531                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1532                         resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1533                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1534                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1535                                  <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1536                                  <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1537                                  <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1538                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1539                                       "rst_brg", "rst_core", "rst_apb";
1540                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1541                                  <&clkgen JH7110_PCIE1_CLK_TL>,
1542                                  <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1543                                  <&clkgen JH7110_PCIE1_CLK_APB>;
1544                         clock-names = "noc", "tl", "axi_mst0", "apb";
1545                         status = "disabled";
1546                 };
1547
1548                 mailbox_contrl0: mailbox@0 {
1549                         compatible = "starfive,mail_box";
1550                         reg = <0x0 0x13060000 0x0 0x0001000>;
1551                         clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1552                         clock-names = "clk_apb";
1553                         resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1554                         reset-names = "mbx_rre";
1555                         interrupts = <26 27>;
1556                         #mbox-cells = <2>;
1557                         status = "disabled";
1558                 };
1559
1560                 mailbox_client0: mailbox_client@0 {
1561                         compatible = "starfive,mailbox-test";
1562                         mbox-names = "rx", "tx";
1563                         mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1564                         status = "disabled";
1565                 };
1566
1567                 display: display-subsystem {
1568                         compatible = "starfive,jh7110-display","verisilicon,display-subsystem";
1569                         ports = <&dc_out_dpi0>;
1570                         status = "disabled";
1571                 };
1572
1573                 dssctrl: dssctrl@295B0000 {
1574                         compatible = "starfive,jh7110-dssctrl","verisilicon,dss-ctrl", "syscon";
1575                         reg = <0 0x295B0000 0 0x90>;
1576                 };
1577
1578                 tda988x_pin: tda988x_pin {
1579                         compatible = "starfive,tda998x_rgb_pin";
1580                         status = "disabled";
1581                 };
1582
1583                 rgb_output: rgb-output {
1584                         compatible = "starfive,jh7110-rgb_output","verisilicon,rgb-encoder";
1585                         //verisilicon,dss-syscon = <&dssctrl>;
1586                         //verisilicon,mux-mask = <0x70 0x380>;
1587                         //verisilicon,mux-val = <0x40 0x280>;
1588                         status = "disabled";
1589                 };
1590
1591                 dc8200: dc8200@29400000 {
1592                         compatible = "starfive,jh7110-dc8200","verisilicon,dc8200";
1593                         verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1594                         reg = <0x0 0x29400000 0x0 0x100>,
1595                               <0x0 0x29400800 0x0 0x2000>,
1596                               <0x0 0x17030000 0x0 0x1000>;
1597                         interrupts = <95>;
1598                         status = "disabled";
1599                         clocks = <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1600                         <&clkgen JH7110_VOUT_SRC>,
1601                         <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1602                         <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1603                         <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1604                         <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1605                         <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1606                         <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1607                         <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1608                         <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1609                         <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1610                         <&hdmitx0_pixelclk>,
1611                         <&clkvout JH7110_DC8200_PIX0>,
1612                         <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1613                         <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1614                         clock-names = "noc_disp","vout_src",
1615                            "top_vout_axi","top_vout_ahb",
1616                            "pix_clk","vout_pix1",
1617                            "axi_clk","core_clk","vout_ahb",
1618                            "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1619                            "dc8200_pix0_out","dc8200_pix1_out";
1620                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1621                                  <&rstgen RSTN_U0_DC8200_AXI>,
1622                                  <&rstgen RSTN_U0_DC8200_AHB>,
1623                                  <&rstgen RSTN_U0_DC8200_CORE>,
1624                                  <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>;
1625                         reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1626                                         "rst_noc_disp";
1627                 };
1628
1629                 dsi_output: dsi-output {
1630                         compatible = "starfive,jh7110-display-encoder","verisilicon,dsi-encoder";
1631                         status = "disabled";
1632                 };
1633
1634                 mipi_dphy: mipi-dphy@295e0000{
1635                         compatible = "starfive,jh7110-mipi-dphy-tx","m31,mipi-dphy-tx";
1636                         reg = <0x0 0x295e0000 0x0 0x10000>;
1637                         clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1638                         clock-names = "dphy_txesc";
1639                         resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1640                                  <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1641                         reset-names = "dphy_sys", "dphy_txbytehs";
1642                         #phy-cells = <0>;
1643                         status = "disabled";
1644                 };
1645
1646                  mipi_dsi: mipi@295d0000 {
1647                         compatible = "starfive,jh7110-mipi_dsi","cdns,dsi";
1648                         reg = <0x0 0x295d0000 0x0 0x10000>;
1649                         interrupts = <98>;
1650                         reg-names = "dsi";
1651                         clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1652                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1653                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1654                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1655                         clock-names = "sys", "apb", "txesc", "dpi";
1656                         resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1657                                  <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1658                                  <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1659                                  <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1660                                  <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1661                                  <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1662                         reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1663                                         "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1664                         phys = <&mipi_dphy>;
1665                         phy-names = "dphy";
1666                         status = "disabled";
1667
1668                         port {
1669                                 dsi_out_port: endpoint@0 {
1670                                         remote-endpoint = <&panel_dsi_port>;
1671                                 };
1672                                 dsi_in_port: endpoint@1 {
1673                                         remote-endpoint = <&mipi_out>;
1674                                 };
1675                         };
1676
1677                         mipi_panel: panel@0 {
1678                                 /*compatible = "";*/
1679                                 status = "okay";
1680                         };
1681                 };
1682
1683                 hdmi: hdmi@29590000 {
1684                         compatible = "starfive,jh7110-hdmi","inno,hdmi";
1685                         reg = <0x0 0x29590000 0x0 0x4000>;
1686                         interrupts = <99>;
1687                         /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1688                         /*clocks = <&cru  PCLK_HDMI>;*/
1689                         /*clock-names = "pclk";*/
1690                         /*pinctrl-names = "default";*/
1691                         /*pinctrl-0 = <&hdmi_ctl>;*/
1692                         status = "disabled";
1693                         clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1694                                  <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1695                                  <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1696                                  <&hdmitx0_pixelclk>;
1697                         clock-names = "sysclk", "mclk","bclk","pclk";
1698                         resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1699                         reset-names = "hdmi_tx";
1700                         #sound-dai-cells = <0>;
1701                 };
1702
1703                 sound0: snd-card0 {
1704                         compatible = "simple-audio-card";
1705                         simple-audio-card,name = "Starfive-AC108-Sound-Card";
1706                         #address-cells = <1>;
1707                         #size-cells = <0>;
1708                 };
1709
1710                 sound1: snd-card1 {
1711                         compatible = "simple-audio-card";
1712                         simple-audio-card,name = "Starfive-HDMI-Sound-Card";
1713                         #address-cells = <1>;
1714                         #size-cells = <0>;
1715                 };
1716
1717                 sound2: snd-card2 {
1718                         compatible = "simple-audio-card";
1719                         simple-audio-card,name = "Starfive-PDM-Sound-Card";
1720                         #address-cells = <1>;
1721                         #size-cells = <0>;
1722                 };
1723
1724                 sound3: snd-card3 {
1725                         compatible = "simple-audio-card";
1726                         simple-audio-card,name = "Starfive-PWMDAC-Sound-Card";
1727                         #address-cells = <1>;
1728                         #size-cells = <0>;
1729                 };
1730
1731                 sound4: snd-card4 {
1732                         compatible = "simple-audio-card";
1733                         simple-audio-card,name = "Starfive-SPDIF-Sound-Card";
1734                         #address-cells = <1>;
1735                         #size-cells = <0>;
1736                 };
1737
1738                 sound5: snd-card5 {
1739                         compatible = "simple-audio-card";
1740                         simple-audio-card,name = "Starfive-TDM-Sound-Card";
1741                         #address-cells = <1>;
1742                         #size-cells = <0>;
1743                 };
1744
1745                 sound6: snd-card6 {
1746                         compatible = "simple-audio-card";
1747                         simple-audio-card,name = "Starfive-WM8960-Sound-Card";
1748                         #address-cells = <1>;
1749                         #size-cells = <0>;
1750                 };
1751
1752                 co_process: e24@0 {
1753                         compatible = "starfive,e24";
1754                         reg = <0x0 0xc0110000 0x0 0x00001000>,
1755                                 <0x0 0xc0111000 0x0 0x0001f000>;
1756                         reg-names = "ecmd", "espace";
1757                         clocks = <&clkgen JH7110_E2_RTC_CLK>,
1758                                  <&clkgen JH7110_E2_CLK_CORE>,
1759                                  <&clkgen JH7110_E2_CLK_DBG>;
1760                         clock-names = "clk_rtc", "clk_core", "clk_dbg";
1761                         resets = <&rstgen RSTN_U0_E24_CORE>;
1762                         reset-names = "e24_core";
1763                         starfive,stg-syscon = <&stg_syscon>;
1764                         interrupt-parent = <&plic>;
1765                         firmware-name = "e24_elf";
1766                         irq-mode = <1>;
1767                         mbox-names = "tx", "rx";
1768                         mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1769                         #address-cells = <1>;
1770                         #size-cells = <1>;
1771                         ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1772                         status = "disabled";
1773                         dsp@0 {};
1774                 };
1775
1776                 xrp: xrp@0 {
1777                         compatible = "cdns,xrp";
1778                         reg = <0x0  0x10230000 0x0 0x00010000
1779                                 0x0  0x10240000 0x0 0x00010000>;
1780                         memory-region = <&xrp_reserved>;
1781                         clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1782                         clock-names = "core_clk";
1783                         resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1784                                  <&rstgen RSTN_U0_HIFI4_AXI>;
1785                         reset-names = "rst_core","rst_axi";
1786                         starfive,stg-syscon = <&stg_syscon>;
1787                         firmware-name = "hifi4_elf";
1788                         #address-cells = <1>;
1789                         #size-cells = <1>;
1790                         ranges = <0x40000000 0x0 0x20000000 0x040000
1791                                 0xf0000000 0x0 0xf0000000 0x03000000>;
1792                         status = "disabled";
1793                         dsp@0 {
1794                         };
1795                 };
1796
1797                 starfive_cpufreq: starfive,jh7110-cpufreq {
1798                         compatible = "starfive,jh7110-cpufreq";
1799                         clocks = <&clkgen JH7110_CPU_CORE>;
1800                         clock-names = "cpu_clk";
1801                 };
1802         };
1803 };