drm/vc4: hvs: Boost the core clock during modeset

In order to prevent timeouts and stalls in the pipeline, the core clock
needs to be maxed at 500MHz during a modeset on the BCM2711.

Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/37ed9e0124c5cce005ddc8dafe821d8b0da036ff.1599120059.git-series.maxime@cerno.tech
[hoegeun.kwon: A screen cracking problem occurs in FHD(1920x1080). The
cause is that the clock should be kept at 500MHz, but it occurred when
the clock fell to 200MHz, so apply a patch.]
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Change-Id: Ie0d4880966c1644bfdf56bb49dbb82559978538c

diff --git a/drivers/gpu/drm/vc4/vc4_kms.c b/drivers/gpu/drm/vc4/vc4_kms.c
index 7f857af..ae514d4 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_kms.c
+++ b/drivers/gpu/drm/vc4/vc4_kms.c
@@ -239,8 +239,8 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
                vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel);
        }
 
-       if (!vc4->firmware_kms)
-               clk_set_rate(hvs->core_clk, 500000000);
+       if (vc4->hvs->hvs5)
+               clk_set_min_rate(hvs->core_clk, 500000000);
 
        drm_atomic_helper_wait_for_fences(dev, state, false);
 
@@ -267,9 +267,6 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state)
 
        drm_atomic_helper_commit_cleanup_done(state);
 
-       if (!vc4->firmware_kms)
-               clk_set_rate(hvs->core_clk, 200000000);
-
        drm_atomic_state_put(state);
 
        up(&vc4->async_modeset);