1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the distribution.
15 // - Neither the name of Sun Microsystems or the names of contributors may
16 // be used to endorse or promote products derived from this software without
17 // specific prior written permission.
19 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
20 // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2012 the V8 project authors. All rights reserved.
35 // A lightweight X64 Assembler.
37 #ifndef V8_X64_ASSEMBLER_X64_H_
38 #define V8_X64_ASSEMBLER_X64_H_
40 #include "src/serialize.h"
49 // 1) We would prefer to use an enum, but enum values are assignment-
50 // compatible with int, which has caused code-generation bugs.
52 // 2) We would prefer to use a class instead of a struct but we don't like
53 // the register initialization to depend on the particular initialization
54 // order (which appears to be different on OS X, Linux, and Windows for the
55 // installed versions of C++ we tried). Using a struct permits C-style
56 // "initialization". Also, the Register objects cannot be const as this
57 // forces initialization stubs in MSVC, making us dependent on initialization
60 // 3) By not using an enum, we are possibly preventing the compiler from
61 // doing certain constant folds, which may significantly reduce the
62 // code generated for some assembly instructions (because they boil down
63 // to a few constants). If this is a problem, we could change the code
64 // such that we use an enum in optimized mode, and the struct in debug
65 // mode. This way we get the compile-time error checking in debug mode
66 // and best performance in optimized code.
70 // The non-allocatable registers are:
71 // rsp - stack pointer
72 // rbp - frame pointer
73 // r10 - fixed scratch register
74 // r12 - smi constant register
75 // r13 - root register
76 static const int kMaxNumAllocatableRegisters = 11;
77 static int NumAllocatableRegisters() {
78 return kMaxNumAllocatableRegisters;
80 static const int kNumRegisters = 16;
82 static int ToAllocationIndex(Register reg) {
83 return kAllocationIndexByRegisterCode[reg.code()];
86 static Register FromAllocationIndex(int index) {
87 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
88 Register result = { kRegisterCodeByAllocationIndex[index] };
92 static const char* AllocationIndexToString(int index) {
93 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
94 const char* const names[] = {
110 static Register from_code(int code) {
111 Register r = { code };
114 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
115 bool is(Register reg) const { return code_ == reg.code_; }
116 // rax, rbx, rcx and rdx are byte registers, the rest are not.
117 bool is_byte_register() const { return code_ <= 3; }
126 // Return the high bit of the register code as a 0 or 1. Used often
127 // when constructing the REX prefix byte.
128 int high_bit() const {
131 // Return the 3 low bits of the register code. Used when encoding registers
132 // in modR/M, SIB, and opcode bytes.
133 int low_bits() const {
137 // Unfortunately we can't make this private in a struct when initializing
142 static const int kRegisterCodeByAllocationIndex[kMaxNumAllocatableRegisters];
143 static const int kAllocationIndexByRegisterCode[kNumRegisters];
146 const int kRegister_rax_Code = 0;
147 const int kRegister_rcx_Code = 1;
148 const int kRegister_rdx_Code = 2;
149 const int kRegister_rbx_Code = 3;
150 const int kRegister_rsp_Code = 4;
151 const int kRegister_rbp_Code = 5;
152 const int kRegister_rsi_Code = 6;
153 const int kRegister_rdi_Code = 7;
154 const int kRegister_r8_Code = 8;
155 const int kRegister_r9_Code = 9;
156 const int kRegister_r10_Code = 10;
157 const int kRegister_r11_Code = 11;
158 const int kRegister_r12_Code = 12;
159 const int kRegister_r13_Code = 13;
160 const int kRegister_r14_Code = 14;
161 const int kRegister_r15_Code = 15;
162 const int kRegister_no_reg_Code = -1;
164 const Register rax = { kRegister_rax_Code };
165 const Register rcx = { kRegister_rcx_Code };
166 const Register rdx = { kRegister_rdx_Code };
167 const Register rbx = { kRegister_rbx_Code };
168 const Register rsp = { kRegister_rsp_Code };
169 const Register rbp = { kRegister_rbp_Code };
170 const Register rsi = { kRegister_rsi_Code };
171 const Register rdi = { kRegister_rdi_Code };
172 const Register r8 = { kRegister_r8_Code };
173 const Register r9 = { kRegister_r9_Code };
174 const Register r10 = { kRegister_r10_Code };
175 const Register r11 = { kRegister_r11_Code };
176 const Register r12 = { kRegister_r12_Code };
177 const Register r13 = { kRegister_r13_Code };
178 const Register r14 = { kRegister_r14_Code };
179 const Register r15 = { kRegister_r15_Code };
180 const Register no_reg = { kRegister_no_reg_Code };
183 // Windows calling convention
184 const Register arg_reg_1 = { kRegister_rcx_Code };
185 const Register arg_reg_2 = { kRegister_rdx_Code };
186 const Register arg_reg_3 = { kRegister_r8_Code };
187 const Register arg_reg_4 = { kRegister_r9_Code };
189 // AMD64 calling convention
190 const Register arg_reg_1 = { kRegister_rdi_Code };
191 const Register arg_reg_2 = { kRegister_rsi_Code };
192 const Register arg_reg_3 = { kRegister_rdx_Code };
193 const Register arg_reg_4 = { kRegister_rcx_Code };
197 static const int kMaxNumRegisters = 16;
198 static const int kMaxNumAllocatableRegisters = 15;
199 static int NumAllocatableRegisters() {
200 return kMaxNumAllocatableRegisters;
203 static int ToAllocationIndex(XMMRegister reg) {
204 ASSERT(reg.code() != 0);
205 return reg.code() - 1;
208 static XMMRegister FromAllocationIndex(int index) {
209 ASSERT(0 <= index && index < kMaxNumAllocatableRegisters);
210 XMMRegister result = { index + 1 };
214 static const char* AllocationIndexToString(int index) {
215 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
216 const char* const names[] = {
236 static XMMRegister from_code(int code) {
238 ASSERT(code < kMaxNumRegisters);
239 XMMRegister r = { code };
242 bool is_valid() const { return 0 <= code_ && code_ < kMaxNumRegisters; }
243 bool is(XMMRegister reg) const { return code_ == reg.code_; }
249 // Return the high bit of the register code as a 0 or 1. Used often
250 // when constructing the REX prefix byte.
251 int high_bit() const {
254 // Return the 3 low bits of the register code. Used when encoding registers
255 // in modR/M, SIB, and opcode bytes.
256 int low_bits() const {
263 const XMMRegister xmm0 = { 0 };
264 const XMMRegister xmm1 = { 1 };
265 const XMMRegister xmm2 = { 2 };
266 const XMMRegister xmm3 = { 3 };
267 const XMMRegister xmm4 = { 4 };
268 const XMMRegister xmm5 = { 5 };
269 const XMMRegister xmm6 = { 6 };
270 const XMMRegister xmm7 = { 7 };
271 const XMMRegister xmm8 = { 8 };
272 const XMMRegister xmm9 = { 9 };
273 const XMMRegister xmm10 = { 10 };
274 const XMMRegister xmm11 = { 11 };
275 const XMMRegister xmm12 = { 12 };
276 const XMMRegister xmm13 = { 13 };
277 const XMMRegister xmm14 = { 14 };
278 const XMMRegister xmm15 = { 15 };
281 typedef XMMRegister DoubleRegister;
285 // any value < 0 is considered no_condition
305 // Fake conditions that are handled by the
306 // opcodes using them.
311 not_carry = above_equal,
313 not_zero = not_equal,
316 last_condition = greater
320 // Returns the equivalent of !cc.
321 // Negation of the default no_condition (-1) results in a non-default
322 // no_condition value (-2). As long as tests for no_condition check
323 // for condition < 0, this will work as expected.
324 inline Condition NegateCondition(Condition cc) {
325 return static_cast<Condition>(cc ^ 1);
329 // Commute a condition such that {a cond b == b cond' a}.
330 inline Condition CommuteCondition(Condition cc) {
347 return greater_equal;
354 // -----------------------------------------------------------------------------
355 // Machine instruction Immediates
357 class Immediate BASE_EMBEDDED {
359 explicit Immediate(int32_t value) : value_(value) {}
360 explicit Immediate(Smi* value) {
361 ASSERT(SmiValuesAre31Bits()); // Only available for 31-bit SMI.
362 value_ = static_cast<int32_t>(reinterpret_cast<intptr_t>(value));
368 friend class Assembler;
372 // -----------------------------------------------------------------------------
373 // Machine instruction Operands
380 times_int_size = times_4,
381 times_pointer_size = (kPointerSize == 8) ? times_8 : times_4
385 class Operand BASE_EMBEDDED {
388 Operand(Register base, int32_t disp);
390 // [base + index*scale + disp/r]
391 Operand(Register base,
396 // [index*scale + disp/r]
397 Operand(Register index,
401 // Offset from existing memory operand.
402 // Offset is added to existing displacement as 32-bit signed values and
403 // this must not overflow.
404 Operand(const Operand& base, int32_t offset);
406 // Checks whether either base or index register is the given register.
407 // Does not check the "reg" part of the Operand.
408 bool AddressUsesRegister(Register reg) const;
410 // Queries related to the size of the generated instruction.
411 // Whether the generated instruction will have a REX prefix.
412 bool requires_rex() const { return rex_ != 0; }
413 // Size of the ModR/M, SIB and displacement parts of the generated
415 int operand_size() const { return len_; }
420 // The number of bytes of buf_ in use.
423 // Set the ModR/M byte without an encoded 'reg' register. The
424 // register is encoded later as part of the emit_operand operation.
425 // set_modrm can be called before or after set_sib and set_disp*.
426 inline void set_modrm(int mod, Register rm);
428 // Set the SIB byte if one is needed. Sets the length to 2 rather than 1.
429 inline void set_sib(ScaleFactor scale, Register index, Register base);
431 // Adds operand displacement fields (offsets added to the memory address).
432 // Needs to be called after set_sib, not before it.
433 inline void set_disp8(int disp);
434 inline void set_disp32(int disp);
436 friend class Assembler;
440 #define ASSEMBLER_INSTRUCTION_LIST(V) \
463 // Shift instructions on operands/registers with kPointerSize, kInt32Size and
465 #define SHIFT_INSTRUCTION_LIST(V) \
475 class Assembler : public AssemblerBase {
477 // We check before assembling an instruction that there is sufficient
478 // space to write an instruction and its relocation information.
479 // The relocation writer's position must be kGap bytes above the end of
480 // the generated instructions. This leaves enough space for the
481 // longest possible x64 instruction, 15 bytes, and the longest possible
482 // relocation information encoding, RelocInfoWriter::kMaxLength == 16.
483 // (There is a 15 byte limit on x64 instruction length that rules out some
484 // otherwise valid instructions.)
485 // This allows for a single, fast space check per instruction.
486 static const int kGap = 32;
489 // Create an assembler. Instructions and relocation information are emitted
490 // into a buffer, with the instructions starting from the beginning and the
491 // relocation information starting from the end of the buffer. See CodeDesc
492 // for a detailed comment on the layout (globals.h).
494 // If the provided buffer is NULL, the assembler allocates and grows its own
495 // buffer, and buffer_size determines the initial buffer size. The buffer is
496 // owned by the assembler and deallocated upon destruction of the assembler.
498 // If the provided buffer is not NULL, the assembler uses the provided buffer
499 // for code generation and assumes its size to be buffer_size. If the buffer
500 // is too small, a fatal error occurs. No deallocation of the buffer is done
501 // upon destruction of the assembler.
502 Assembler(Isolate* isolate, void* buffer, int buffer_size);
503 virtual ~Assembler() { }
505 // GetCode emits any pending (non-emitted) code and fills the descriptor
506 // desc. GetCode() is idempotent; it returns the same result if no other
507 // Assembler functions are invoked in between GetCode() calls.
508 void GetCode(CodeDesc* desc);
510 // Read/Modify the code target in the relative branch/call instruction at pc.
511 // On the x64 architecture, we use relative jumps with a 32-bit displacement
512 // to jump to other Code objects in the Code space in the heap.
513 // Jumps to C functions are done indirectly through a 64-bit register holding
514 // the absolute address of the target.
515 // These functions convert between absolute Addresses of Code objects and
516 // the relative displacements stored in the code.
517 static inline Address target_address_at(Address pc,
518 ConstantPoolArray* constant_pool);
519 static inline void set_target_address_at(Address pc,
520 ConstantPoolArray* constant_pool,
522 ICacheFlushMode icache_flush_mode =
523 FLUSH_ICACHE_IF_NEEDED) ;
524 static inline Address target_address_at(Address pc, Code* code) {
525 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
526 return target_address_at(pc, constant_pool);
528 static inline void set_target_address_at(Address pc,
531 ICacheFlushMode icache_flush_mode =
532 FLUSH_ICACHE_IF_NEEDED) {
533 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
534 set_target_address_at(pc, constant_pool, target, icache_flush_mode);
537 // Return the code target address at a call site from the return address
538 // of that call in the instruction stream.
539 static inline Address target_address_from_return_address(Address pc);
541 // This sets the branch destination (which is in the instruction on x64).
542 // This is for calls and branches within generated code.
543 inline static void deserialization_set_special_target_at(
544 Address instruction_payload, Code* code, Address target) {
545 set_target_address_at(instruction_payload, code, target);
548 static inline RelocInfo::Mode RelocInfoNone() {
549 if (kPointerSize == kInt64Size) {
550 return RelocInfo::NONE64;
552 ASSERT(kPointerSize == kInt32Size);
553 return RelocInfo::NONE32;
557 inline Handle<Object> code_target_object_handle_at(Address pc);
558 inline Address runtime_entry_at(Address pc);
559 // Number of bytes taken up by the branch target in the code.
560 static const int kSpecialTargetSize = 4; // Use 32-bit displacement.
561 // Distance between the address of the code target in the call instruction
562 // and the return address pushed on the stack.
563 static const int kCallTargetAddressOffset = 4; // Use 32-bit displacement.
564 // The length of call(kScratchRegister).
565 static const int kCallScratchRegisterInstructionLength = 3;
566 // The length of call(Immediate32).
567 static const int kShortCallInstructionLength = 5;
568 // The length of movq(kScratchRegister, address).
569 static const int kMoveAddressIntoScratchRegisterInstructionLength =
571 // The length of movq(kScratchRegister, address) and call(kScratchRegister).
572 static const int kCallSequenceLength =
573 kMoveAddressIntoScratchRegisterInstructionLength +
574 kCallScratchRegisterInstructionLength;
576 // The js return and debug break slot must be able to contain an indirect
577 // call sequence, some x64 JS code is padded with int3 to make it large
578 // enough to hold an instruction when the debugger patches it.
579 static const int kJSReturnSequenceLength = kCallSequenceLength;
580 static const int kDebugBreakSlotLength = kCallSequenceLength;
581 static const int kPatchDebugBreakSlotReturnOffset = kCallTargetAddressOffset;
582 // Distance between the start of the JS return sequence and where the
583 // 32-bit displacement of a short call would be. The short call is from
584 // SetDebugBreakAtIC from debug-x64.cc.
585 static const int kPatchReturnSequenceAddressOffset =
586 kJSReturnSequenceLength - kPatchDebugBreakSlotReturnOffset;
587 // Distance between the start of the JS return sequence and where the
588 // 32-bit displacement of a short call would be. The short call is from
589 // SetDebugBreakAtIC from debug-x64.cc.
590 static const int kPatchDebugBreakSlotAddressOffset =
591 kDebugBreakSlotLength - kPatchDebugBreakSlotReturnOffset;
592 static const int kRealPatchReturnSequenceAddressOffset =
593 kMoveAddressIntoScratchRegisterInstructionLength - kPointerSize;
595 // One byte opcode for test eax,0xXXXXXXXX.
596 static const byte kTestEaxByte = 0xA9;
597 // One byte opcode for test al, 0xXX.
598 static const byte kTestAlByte = 0xA8;
599 // One byte opcode for nop.
600 static const byte kNopByte = 0x90;
602 // One byte prefix for a short conditional jump.
603 static const byte kJccShortPrefix = 0x70;
604 static const byte kJncShortOpcode = kJccShortPrefix | not_carry;
605 static const byte kJcShortOpcode = kJccShortPrefix | carry;
606 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero;
607 static const byte kJzShortOpcode = kJccShortPrefix | zero;
610 // ---------------------------------------------------------------------------
613 // Function names correspond one-to-one to x64 instruction mnemonics.
614 // Unless specified otherwise, instructions operate on 64-bit operands.
616 // If we need versions of an assembly instruction that operate on different
617 // width arguments, we add a single-letter suffix specifying the width.
618 // This is done for the following instructions: mov, cmp, inc, dec,
619 // add, sub, and test.
620 // There are no versions of these instructions without the suffix.
621 // - Instructions on 8-bit (byte) operands/registers have a trailing 'b'.
622 // - Instructions on 16-bit (word) operands/registers have a trailing 'w'.
623 // - Instructions on 32-bit (doubleword) operands/registers use 'l'.
624 // - Instructions on 64-bit (quadword) operands/registers use 'q'.
625 // - Instructions on operands/registers with pointer size use 'p'.
627 STATIC_ASSERT(kPointerSize == kInt64Size || kPointerSize == kInt32Size);
629 #define DECLARE_INSTRUCTION(instruction) \
631 void instruction##p(P1 p1) { \
632 emit_##instruction(p1, kPointerSize); \
636 void instruction##l(P1 p1) { \
637 emit_##instruction(p1, kInt32Size); \
641 void instruction##q(P1 p1) { \
642 emit_##instruction(p1, kInt64Size); \
645 template<class P1, class P2> \
646 void instruction##p(P1 p1, P2 p2) { \
647 emit_##instruction(p1, p2, kPointerSize); \
650 template<class P1, class P2> \
651 void instruction##l(P1 p1, P2 p2) { \
652 emit_##instruction(p1, p2, kInt32Size); \
655 template<class P1, class P2> \
656 void instruction##q(P1 p1, P2 p2) { \
657 emit_##instruction(p1, p2, kInt64Size); \
660 template<class P1, class P2, class P3> \
661 void instruction##p(P1 p1, P2 p2, P3 p3) { \
662 emit_##instruction(p1, p2, p3, kPointerSize); \
665 template<class P1, class P2, class P3> \
666 void instruction##l(P1 p1, P2 p2, P3 p3) { \
667 emit_##instruction(p1, p2, p3, kInt32Size); \
670 template<class P1, class P2, class P3> \
671 void instruction##q(P1 p1, P2 p2, P3 p3) { \
672 emit_##instruction(p1, p2, p3, kInt64Size); \
674 ASSEMBLER_INSTRUCTION_LIST(DECLARE_INSTRUCTION)
675 #undef DECLARE_INSTRUCTION
677 // Insert the smallest number of nop instructions
678 // possible to align the pc offset to a multiple
679 // of m, where m must be a power of 2.
681 void Nop(int bytes = 1);
682 // Aligns code to something that's optimal for a jump target for the platform.
683 void CodeTargetAlign();
689 void pushq(Immediate value);
690 // Push a 32 bit integer, and guarantee that it is actually pushed as a
691 // 32 bit value, the normal push will optimize the 8 bit case.
692 void pushq_imm32(int32_t imm32);
693 void pushq(Register src);
694 void pushq(const Operand& src);
696 void popq(Register dst);
697 void popq(const Operand& dst);
699 void enter(Immediate size);
703 void movb(Register dst, const Operand& src);
704 void movb(Register dst, Immediate imm);
705 void movb(const Operand& dst, Register src);
706 void movb(const Operand& dst, Immediate imm);
708 // Move the low 16 bits of a 64-bit register value to a 16-bit
710 void movw(Register dst, const Operand& src);
711 void movw(const Operand& dst, Register src);
712 void movw(const Operand& dst, Immediate imm);
714 // Move the offset of the label location relative to the current
715 // position (after the move) to the destination.
716 void movl(const Operand& dst, Label* src);
718 // Loads a pointer into a register with a relocation mode.
719 void movp(Register dst, void* ptr, RelocInfo::Mode rmode);
721 // Loads a 64-bit immediate into a register.
722 void movq(Register dst, int64_t value);
723 void movq(Register dst, uint64_t value);
725 void movsxbl(Register dst, const Operand& src);
726 void movsxbq(Register dst, const Operand& src);
727 void movsxwl(Register dst, const Operand& src);
728 void movsxwq(Register dst, const Operand& src);
729 void movsxlq(Register dst, Register src);
730 void movsxlq(Register dst, const Operand& src);
736 void repmovsp() { emit_repmovs(kPointerSize); }
737 void repmovsl() { emit_repmovs(kInt32Size); }
738 void repmovsq() { emit_repmovs(kInt64Size); }
740 // Instruction to load from an immediate 64-bit pointer into RAX.
741 void load_rax(void* ptr, RelocInfo::Mode rmode);
742 void load_rax(ExternalReference ext);
744 // Conditional moves.
745 void cmovq(Condition cc, Register dst, Register src);
746 void cmovq(Condition cc, Register dst, const Operand& src);
747 void cmovl(Condition cc, Register dst, Register src);
748 void cmovl(Condition cc, Register dst, const Operand& src);
750 void cmpb(Register dst, Immediate src) {
751 immediate_arithmetic_op_8(0x7, dst, src);
754 void cmpb_al(Immediate src);
756 void cmpb(Register dst, Register src) {
757 arithmetic_op_8(0x3A, dst, src);
760 void cmpb(Register dst, const Operand& src) {
761 arithmetic_op_8(0x3A, dst, src);
764 void cmpb(const Operand& dst, Register src) {
765 arithmetic_op_8(0x38, src, dst);
768 void cmpb(const Operand& dst, Immediate src) {
769 immediate_arithmetic_op_8(0x7, dst, src);
772 void cmpw(const Operand& dst, Immediate src) {
773 immediate_arithmetic_op_16(0x7, dst, src);
776 void cmpw(Register dst, Immediate src) {
777 immediate_arithmetic_op_16(0x7, dst, src);
780 void cmpw(Register dst, const Operand& src) {
781 arithmetic_op_16(0x3B, dst, src);
784 void cmpw(Register dst, Register src) {
785 arithmetic_op_16(0x3B, dst, src);
788 void cmpw(const Operand& dst, Register src) {
789 arithmetic_op_16(0x39, src, dst);
792 void andb(Register dst, Immediate src) {
793 immediate_arithmetic_op_8(0x4, dst, src);
796 void decb(Register dst);
797 void decb(const Operand& dst);
799 // Sign-extends rax into rdx:rax.
801 // Sign-extends eax into edx:eax.
804 // Multiply rax by src, put the result in rdx:rax.
805 void mul(Register src);
807 #define DECLARE_SHIFT_INSTRUCTION(instruction, subcode) \
808 void instruction##p(Register dst, Immediate imm8) { \
809 shift(dst, imm8, subcode, kPointerSize); \
812 void instruction##l(Register dst, Immediate imm8) { \
813 shift(dst, imm8, subcode, kInt32Size); \
816 void instruction##q(Register dst, Immediate imm8) { \
817 shift(dst, imm8, subcode, kInt64Size); \
820 void instruction##p_cl(Register dst) { \
821 shift(dst, subcode, kPointerSize); \
824 void instruction##l_cl(Register dst) { \
825 shift(dst, subcode, kInt32Size); \
828 void instruction##q_cl(Register dst) { \
829 shift(dst, subcode, kInt64Size); \
831 SHIFT_INSTRUCTION_LIST(DECLARE_SHIFT_INSTRUCTION)
832 #undef DECLARE_SHIFT_INSTRUCTION
834 // Shifts dst:src left by cl bits, affecting only dst.
835 void shld(Register dst, Register src);
837 // Shifts src:dst right by cl bits, affecting only dst.
838 void shrd(Register dst, Register src);
840 void store_rax(void* dst, RelocInfo::Mode mode);
841 void store_rax(ExternalReference ref);
843 void subb(Register dst, Immediate src) {
844 immediate_arithmetic_op_8(0x5, dst, src);
847 void testb(Register dst, Register src);
848 void testb(Register reg, Immediate mask);
849 void testb(const Operand& op, Immediate mask);
850 void testb(const Operand& op, Register reg);
853 void bt(const Operand& dst, Register src);
854 void bts(const Operand& dst, Register src);
855 void bsrl(Register dst, Register src);
865 void setcc(Condition cc, Register reg);
867 // Label operations & relative jumps (PPUM Appendix D)
869 // Takes a branch opcode (cc) and a label (L) and generates
870 // either a backward branch or a forward branch and links it
871 // to the label fixup chain. Usage:
873 // Label L; // unbound label
874 // j(cc, &L); // forward branch to unbound label
875 // bind(&L); // bind label to the current pc
876 // j(cc, &L); // backward branch to bound label
877 // bind(&L); // illegal: a label may be bound only once
879 // Note: The same Label can be used for forward and backward branches
880 // but it may be bound only once.
882 void bind(Label* L); // binds an unbound label L to the current code position
885 // Call near relative 32-bit displacement, relative to next instruction.
887 void call(Address entry, RelocInfo::Mode rmode);
888 void call(Handle<Code> target,
889 RelocInfo::Mode rmode = RelocInfo::CODE_TARGET,
890 TypeFeedbackId ast_id = TypeFeedbackId::None());
892 // Calls directly to the given address using a relative offset.
893 // Should only ever be used in Code objects for calls within the
894 // same Code object. Should not be used when generating new code (use labels),
895 // but only when patching existing code.
896 void call(Address target);
898 // Call near absolute indirect, address in register
899 void call(Register adr);
902 // Jump short or near relative.
903 // Use a 32-bit signed displacement.
904 // Unconditional jump to L
905 void jmp(Label* L, Label::Distance distance = Label::kFar);
906 void jmp(Address entry, RelocInfo::Mode rmode);
907 void jmp(Handle<Code> target, RelocInfo::Mode rmode);
909 // Jump near absolute indirect (r64)
910 void jmp(Register adr);
915 Label::Distance distance = Label::kFar);
916 void j(Condition cc, Address entry, RelocInfo::Mode rmode);
917 void j(Condition cc, Handle<Code> target, RelocInfo::Mode rmode);
919 // Floating-point operations
927 void fld_s(const Operand& adr);
928 void fld_d(const Operand& adr);
930 void fstp_s(const Operand& adr);
931 void fstp_d(const Operand& adr);
932 void fstp(int index);
934 void fild_s(const Operand& adr);
935 void fild_d(const Operand& adr);
937 void fist_s(const Operand& adr);
939 void fistp_s(const Operand& adr);
940 void fistp_d(const Operand& adr);
942 void fisttp_s(const Operand& adr);
943 void fisttp_d(const Operand& adr);
953 void fisub_s(const Operand& adr);
955 void faddp(int i = 1);
956 void fsubp(int i = 1);
957 void fsubrp(int i = 1);
958 void fmulp(int i = 1);
959 void fdivp(int i = 1);
963 void fxch(int i = 1);
965 void ffree(int i = 0);
991 void movaps(XMMRegister dst, XMMRegister src);
992 void movss(XMMRegister dst, const Operand& src);
993 void movss(const Operand& dst, XMMRegister src);
994 void shufps(XMMRegister dst, XMMRegister src, byte imm8);
996 void cvttss2si(Register dst, const Operand& src);
997 void cvttss2si(Register dst, XMMRegister src);
998 void cvtlsi2ss(XMMRegister dst, Register src);
1000 void andps(XMMRegister dst, XMMRegister src);
1001 void andps(XMMRegister dst, const Operand& src);
1002 void orps(XMMRegister dst, XMMRegister src);
1003 void orps(XMMRegister dst, const Operand& src);
1004 void xorps(XMMRegister dst, XMMRegister src);
1005 void xorps(XMMRegister dst, const Operand& src);
1007 void addps(XMMRegister dst, XMMRegister src);
1008 void addps(XMMRegister dst, const Operand& src);
1009 void subps(XMMRegister dst, XMMRegister src);
1010 void subps(XMMRegister dst, const Operand& src);
1011 void mulps(XMMRegister dst, XMMRegister src);
1012 void mulps(XMMRegister dst, const Operand& src);
1013 void divps(XMMRegister dst, XMMRegister src);
1014 void divps(XMMRegister dst, const Operand& src);
1016 void movmskps(Register dst, XMMRegister src);
1018 // SSE2 instructions
1019 void movd(XMMRegister dst, Register src);
1020 void movd(Register dst, XMMRegister src);
1021 void movq(XMMRegister dst, Register src);
1022 void movq(Register dst, XMMRegister src);
1023 void movq(XMMRegister dst, XMMRegister src);
1025 // Don't use this unless it's important to keep the
1026 // top half of the destination register unchanged.
1027 // Used movaps when moving double values and movq for integer
1028 // values in xmm registers.
1029 void movsd(XMMRegister dst, XMMRegister src);
1031 void movsd(const Operand& dst, XMMRegister src);
1032 void movsd(XMMRegister dst, const Operand& src);
1034 void movdqa(const Operand& dst, XMMRegister src);
1035 void movdqa(XMMRegister dst, const Operand& src);
1037 void movdqu(const Operand& dst, XMMRegister src);
1038 void movdqu(XMMRegister dst, const Operand& src);
1040 void movapd(XMMRegister dst, XMMRegister src);
1042 void psllq(XMMRegister reg, byte imm8);
1044 void cvttsd2si(Register dst, const Operand& src);
1045 void cvttsd2si(Register dst, XMMRegister src);
1046 void cvttsd2siq(Register dst, XMMRegister src);
1048 void cvtlsi2sd(XMMRegister dst, const Operand& src);
1049 void cvtlsi2sd(XMMRegister dst, Register src);
1050 void cvtqsi2sd(XMMRegister dst, const Operand& src);
1051 void cvtqsi2sd(XMMRegister dst, Register src);
1054 void cvtss2sd(XMMRegister dst, XMMRegister src);
1055 void cvtss2sd(XMMRegister dst, const Operand& src);
1056 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1058 void cvtsd2si(Register dst, XMMRegister src);
1059 void cvtsd2siq(Register dst, XMMRegister src);
1061 void addsd(XMMRegister dst, XMMRegister src);
1062 void addsd(XMMRegister dst, const Operand& src);
1063 void subsd(XMMRegister dst, XMMRegister src);
1064 void mulsd(XMMRegister dst, XMMRegister src);
1065 void mulsd(XMMRegister dst, const Operand& src);
1066 void divsd(XMMRegister dst, XMMRegister src);
1068 void andpd(XMMRegister dst, XMMRegister src);
1069 void orpd(XMMRegister dst, XMMRegister src);
1070 void xorpd(XMMRegister dst, XMMRegister src);
1071 void sqrtsd(XMMRegister dst, XMMRegister src);
1072 void sqrtsd(XMMRegister dst, const Operand& src);
1074 void ucomisd(XMMRegister dst, XMMRegister src);
1075 void ucomisd(XMMRegister dst, const Operand& src);
1076 void cmpltsd(XMMRegister dst, XMMRegister src);
1078 void movmskpd(Register dst, XMMRegister src);
1080 // SSE 4.1 instruction
1081 void extractps(Register dst, XMMRegister src, byte imm8);
1084 kRoundToNearest = 0x0,
1090 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
1095 // Check the code size generated from label to here.
1096 int SizeOfCodeGeneratedSince(Label* label) {
1097 return pc_offset() - label->pos();
1100 // Mark address of the ExitJSFrame code.
1101 void RecordJSReturn();
1103 // Mark address of a debug break slot.
1104 void RecordDebugBreakSlot();
1106 // Record a comment relocation entry that can be used by a disassembler.
1107 // Use --code-comments to enable.
1108 void RecordComment(const char* msg, bool force = false);
1110 // Allocate a constant pool of the correct size for the generated code.
1111 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
1113 // Generate the constant pool for the generated code.
1114 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1116 // Writes a single word of data in the code stream.
1117 // Used for inline tables, e.g., jump-tables.
1118 void db(uint8_t data);
1119 void dd(uint32_t data);
1121 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1123 // Check if there is less than kGap bytes available in the buffer.
1124 // If this is the case, we need to grow the buffer before emitting
1125 // an instruction or relocation information.
1126 inline bool buffer_overflow() const {
1127 return pc_ >= reloc_info_writer.pos() - kGap;
1130 // Get the number of bytes available in the buffer.
1131 inline int available_space() const {
1132 return static_cast<int>(reloc_info_writer.pos() - pc_);
1135 static bool IsNop(Address addr);
1137 // Avoid overflows for displacements etc.
1138 static const int kMaximalBufferSize = 512*MB;
1140 byte byte_at(int pos) { return buffer_[pos]; }
1141 void set_byte_at(int pos, byte value) { buffer_[pos] = value; }
1144 // Call near indirect
1145 void call(const Operand& operand);
1147 // Jump near absolute indirect (m64)
1148 void jmp(const Operand& src);
1151 byte* addr_at(int pos) { return buffer_ + pos; }
1152 uint32_t long_at(int pos) {
1153 return *reinterpret_cast<uint32_t*>(addr_at(pos));
1155 void long_at_put(int pos, uint32_t x) {
1156 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
1162 void emit(byte x) { *pc_++ = x; }
1163 inline void emitl(uint32_t x);
1164 inline void emitp(void* x, RelocInfo::Mode rmode);
1165 inline void emitq(uint64_t x);
1166 inline void emitw(uint16_t x);
1167 inline void emit_code_target(Handle<Code> target,
1168 RelocInfo::Mode rmode,
1169 TypeFeedbackId ast_id = TypeFeedbackId::None());
1170 inline void emit_runtime_entry(Address entry, RelocInfo::Mode rmode);
1171 void emit(Immediate x) { emitl(x.value_); }
1173 // Emits a REX prefix that encodes a 64-bit operand size and
1174 // the top bit of both register codes.
1175 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1177 inline void emit_rex_64(XMMRegister reg, Register rm_reg);
1178 inline void emit_rex_64(Register reg, XMMRegister rm_reg);
1179 inline void emit_rex_64(Register reg, Register rm_reg);
1181 // Emits a REX prefix that encodes a 64-bit operand size and
1182 // the top bit of the destination, index, and base register codes.
1183 // The high bit of reg is used for REX.R, the high bit of op's base
1184 // register is used for REX.B, and the high bit of op's index register
1185 // is used for REX.X. REX.W is set.
1186 inline void emit_rex_64(Register reg, const Operand& op);
1187 inline void emit_rex_64(XMMRegister reg, const Operand& op);
1189 // Emits a REX prefix that encodes a 64-bit operand size and
1190 // the top bit of the register code.
1191 // The high bit of register is used for REX.B.
1192 // REX.W is set and REX.R and REX.X are clear.
1193 inline void emit_rex_64(Register rm_reg);
1195 // Emits a REX prefix that encodes a 64-bit operand size and
1196 // the top bit of the index and base register codes.
1197 // The high bit of op's base register is used for REX.B, and the high
1198 // bit of op's index register is used for REX.X.
1199 // REX.W is set and REX.R clear.
1200 inline void emit_rex_64(const Operand& op);
1202 // Emit a REX prefix that only sets REX.W to choose a 64-bit operand size.
1203 void emit_rex_64() { emit(0x48); }
1205 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1207 inline void emit_rex_32(Register reg, Register rm_reg);
1209 // The high bit of reg is used for REX.R, the high bit of op's base
1210 // register is used for REX.B, and the high bit of op's index register
1211 // is used for REX.X. REX.W is cleared.
1212 inline void emit_rex_32(Register reg, const Operand& op);
1214 // High bit of rm_reg goes to REX.B.
1215 // REX.W, REX.R and REX.X are clear.
1216 inline void emit_rex_32(Register rm_reg);
1218 // High bit of base goes to REX.B and high bit of index to REX.X.
1219 // REX.W and REX.R are clear.
1220 inline void emit_rex_32(const Operand& op);
1222 // High bit of reg goes to REX.R, high bit of rm_reg goes to REX.B.
1223 // REX.W is cleared. If no REX bits are set, no byte is emitted.
1224 inline void emit_optional_rex_32(Register reg, Register rm_reg);
1226 // The high bit of reg is used for REX.R, the high bit of op's base
1227 // register is used for REX.B, and the high bit of op's index register
1228 // is used for REX.X. REX.W is cleared. If no REX bits are set, nothing
1230 inline void emit_optional_rex_32(Register reg, const Operand& op);
1232 // As for emit_optional_rex_32(Register, Register), except that
1233 // the registers are XMM registers.
1234 inline void emit_optional_rex_32(XMMRegister reg, XMMRegister base);
1236 // As for emit_optional_rex_32(Register, Register), except that
1237 // one of the registers is an XMM registers.
1238 inline void emit_optional_rex_32(XMMRegister reg, Register base);
1240 // As for emit_optional_rex_32(Register, Register), except that
1241 // one of the registers is an XMM registers.
1242 inline void emit_optional_rex_32(Register reg, XMMRegister base);
1244 // As for emit_optional_rex_32(Register, const Operand&), except that
1245 // the register is an XMM register.
1246 inline void emit_optional_rex_32(XMMRegister reg, const Operand& op);
1248 // Optionally do as emit_rex_32(Register) if the register number has
1249 // the high bit set.
1250 inline void emit_optional_rex_32(Register rm_reg);
1252 // Optionally do as emit_rex_32(const Operand&) if the operand register
1253 // numbers have a high bit set.
1254 inline void emit_optional_rex_32(const Operand& op);
1256 void emit_rex(int size) {
1257 if (size == kInt64Size) {
1260 ASSERT(size == kInt32Size);
1265 void emit_rex(P1 p1, int size) {
1266 if (size == kInt64Size) {
1269 ASSERT(size == kInt32Size);
1270 emit_optional_rex_32(p1);
1274 template<class P1, class P2>
1275 void emit_rex(P1 p1, P2 p2, int size) {
1276 if (size == kInt64Size) {
1277 emit_rex_64(p1, p2);
1279 ASSERT(size == kInt32Size);
1280 emit_optional_rex_32(p1, p2);
1284 // Emit the ModR/M byte, and optionally the SIB byte and
1285 // 1- or 4-byte offset for a memory operand. Also encodes
1286 // the second operand of the operation, a register or operation
1287 // subcode, into the reg field of the ModR/M byte.
1288 void emit_operand(Register reg, const Operand& adr) {
1289 emit_operand(reg.low_bits(), adr);
1292 // Emit the ModR/M byte, and optionally the SIB byte and
1293 // 1- or 4-byte offset for a memory operand. Also used to encode
1294 // a three-bit opcode extension into the ModR/M byte.
1295 void emit_operand(int rm, const Operand& adr);
1297 // Emit a ModR/M byte with registers coded in the reg and rm_reg fields.
1298 void emit_modrm(Register reg, Register rm_reg) {
1299 emit(0xC0 | reg.low_bits() << 3 | rm_reg.low_bits());
1302 // Emit a ModR/M byte with an operation subcode in the reg field and
1303 // a register in the rm_reg field.
1304 void emit_modrm(int code, Register rm_reg) {
1305 ASSERT(is_uint3(code));
1306 emit(0xC0 | code << 3 | rm_reg.low_bits());
1309 // Emit the code-object-relative offset of the label's position
1310 inline void emit_code_relative_offset(Label* label);
1312 // The first argument is the reg field, the second argument is the r/m field.
1313 void emit_sse_operand(XMMRegister dst, XMMRegister src);
1314 void emit_sse_operand(XMMRegister reg, const Operand& adr);
1315 void emit_sse_operand(XMMRegister dst, Register src);
1316 void emit_sse_operand(Register dst, XMMRegister src);
1318 // Emit machine code for one of the operations ADD, ADC, SUB, SBC,
1319 // AND, OR, XOR, or CMP. The encodings of these operations are all
1320 // similar, differing just in the opcode or in the reg field of the
1322 void arithmetic_op_8(byte opcode, Register reg, Register rm_reg);
1323 void arithmetic_op_8(byte opcode, Register reg, const Operand& rm_reg);
1324 void arithmetic_op_16(byte opcode, Register reg, Register rm_reg);
1325 void arithmetic_op_16(byte opcode, Register reg, const Operand& rm_reg);
1326 // Operate on operands/registers with pointer size, 32-bit or 64-bit size.
1327 void arithmetic_op(byte opcode, Register reg, Register rm_reg, int size);
1328 void arithmetic_op(byte opcode,
1330 const Operand& rm_reg,
1332 // Operate on a byte in memory or register.
1333 void immediate_arithmetic_op_8(byte subcode,
1336 void immediate_arithmetic_op_8(byte subcode,
1339 // Operate on a word in memory or register.
1340 void immediate_arithmetic_op_16(byte subcode,
1343 void immediate_arithmetic_op_16(byte subcode,
1346 // Operate on operands/registers with pointer size, 32-bit or 64-bit size.
1347 void immediate_arithmetic_op(byte subcode,
1351 void immediate_arithmetic_op(byte subcode,
1356 // Emit machine code for a shift operation.
1357 void shift(Register dst, Immediate shift_amount, int subcode, int size);
1358 // Shift dst by cl % 64 bits.
1359 void shift(Register dst, int subcode, int size);
1361 void emit_farith(int b1, int b2, int i);
1364 // void print(Label* L);
1365 void bind_to(Label* L, int pos);
1367 // record reloc info for current pc_
1368 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1371 void emit_add(Register dst, Register src, int size) {
1372 arithmetic_op(0x03, dst, src, size);
1375 void emit_add(Register dst, Immediate src, int size) {
1376 immediate_arithmetic_op(0x0, dst, src, size);
1379 void emit_add(Register dst, const Operand& src, int size) {
1380 arithmetic_op(0x03, dst, src, size);
1383 void emit_add(const Operand& dst, Register src, int size) {
1384 arithmetic_op(0x1, src, dst, size);
1387 void emit_add(const Operand& dst, Immediate src, int size) {
1388 immediate_arithmetic_op(0x0, dst, src, size);
1391 void emit_and(Register dst, Register src, int size) {
1392 arithmetic_op(0x23, dst, src, size);
1395 void emit_and(Register dst, const Operand& src, int size) {
1396 arithmetic_op(0x23, dst, src, size);
1399 void emit_and(const Operand& dst, Register src, int size) {
1400 arithmetic_op(0x21, src, dst, size);
1403 void emit_and(Register dst, Immediate src, int size) {
1404 immediate_arithmetic_op(0x4, dst, src, size);
1407 void emit_and(const Operand& dst, Immediate src, int size) {
1408 immediate_arithmetic_op(0x4, dst, src, size);
1411 void emit_cmp(Register dst, Register src, int size) {
1412 arithmetic_op(0x3B, dst, src, size);
1415 void emit_cmp(Register dst, const Operand& src, int size) {
1416 arithmetic_op(0x3B, dst, src, size);
1419 void emit_cmp(const Operand& dst, Register src, int size) {
1420 arithmetic_op(0x39, src, dst, size);
1423 void emit_cmp(Register dst, Immediate src, int size) {
1424 immediate_arithmetic_op(0x7, dst, src, size);
1427 void emit_cmp(const Operand& dst, Immediate src, int size) {
1428 immediate_arithmetic_op(0x7, dst, src, size);
1431 void emit_dec(Register dst, int size);
1432 void emit_dec(const Operand& dst, int size);
1434 // Divide rdx:rax by src. Quotient in rax, remainder in rdx when size is 64.
1435 // Divide edx:eax by lower 32 bits of src. Quotient in eax, remainder in edx
1437 void emit_idiv(Register src, int size);
1439 // Signed multiply instructions.
1440 // rdx:rax = rax * src when size is 64 or edx:eax = eax * src when size is 32.
1441 void emit_imul(Register src, int size);
1442 void emit_imul(Register dst, Register src, int size);
1443 void emit_imul(Register dst, const Operand& src, int size);
1444 void emit_imul(Register dst, Register src, Immediate imm, int size);
1446 void emit_inc(Register dst, int size);
1447 void emit_inc(const Operand& dst, int size);
1449 void emit_lea(Register dst, const Operand& src, int size);
1451 void emit_mov(Register dst, const Operand& src, int size);
1452 void emit_mov(Register dst, Register src, int size);
1453 void emit_mov(const Operand& dst, Register src, int size);
1454 void emit_mov(Register dst, Immediate value, int size);
1455 void emit_mov(const Operand& dst, Immediate value, int size);
1457 void emit_movzxb(Register dst, const Operand& src, int size);
1458 void emit_movzxw(Register dst, const Operand& src, int size);
1459 void emit_movzxw(Register dst, Register src, int size);
1461 void emit_neg(Register dst, int size);
1462 void emit_neg(const Operand& dst, int size);
1464 void emit_not(Register dst, int size);
1465 void emit_not(const Operand& dst, int size);
1467 void emit_or(Register dst, Register src, int size) {
1468 arithmetic_op(0x0B, dst, src, size);
1471 void emit_or(Register dst, const Operand& src, int size) {
1472 arithmetic_op(0x0B, dst, src, size);
1475 void emit_or(const Operand& dst, Register src, int size) {
1476 arithmetic_op(0x9, src, dst, size);
1479 void emit_or(Register dst, Immediate src, int size) {
1480 immediate_arithmetic_op(0x1, dst, src, size);
1483 void emit_or(const Operand& dst, Immediate src, int size) {
1484 immediate_arithmetic_op(0x1, dst, src, size);
1487 void emit_repmovs(int size);
1489 void emit_sbb(Register dst, Register src, int size) {
1490 arithmetic_op(0x1b, dst, src, size);
1493 void emit_sub(Register dst, Register src, int size) {
1494 arithmetic_op(0x2B, dst, src, size);
1497 void emit_sub(Register dst, Immediate src, int size) {
1498 immediate_arithmetic_op(0x5, dst, src, size);
1501 void emit_sub(Register dst, const Operand& src, int size) {
1502 arithmetic_op(0x2B, dst, src, size);
1505 void emit_sub(const Operand& dst, Register src, int size) {
1506 arithmetic_op(0x29, src, dst, size);
1509 void emit_sub(const Operand& dst, Immediate src, int size) {
1510 immediate_arithmetic_op(0x5, dst, src, size);
1513 void emit_test(Register dst, Register src, int size);
1514 void emit_test(Register reg, Immediate mask, int size);
1515 void emit_test(const Operand& op, Register reg, int size);
1516 void emit_test(const Operand& op, Immediate mask, int size);
1518 // Exchange two registers
1519 void emit_xchg(Register dst, Register src, int size);
1521 void emit_xor(Register dst, Register src, int size) {
1522 if (size == kInt64Size && dst.code() == src.code()) {
1523 // 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
1524 // there is no need to make this a 64 bit operation.
1525 arithmetic_op(0x33, dst, src, kInt32Size);
1527 arithmetic_op(0x33, dst, src, size);
1531 void emit_xor(Register dst, const Operand& src, int size) {
1532 arithmetic_op(0x33, dst, src, size);
1535 void emit_xor(Register dst, Immediate src, int size) {
1536 immediate_arithmetic_op(0x6, dst, src, size);
1539 void emit_xor(const Operand& dst, Immediate src, int size) {
1540 immediate_arithmetic_op(0x6, dst, src, size);
1543 void emit_xor(const Operand& dst, Register src, int size) {
1544 arithmetic_op(0x31, src, dst, size);
1547 friend class CodePatcher;
1548 friend class EnsureSpace;
1549 friend class RegExpMacroAssemblerX64;
1552 RelocInfoWriter reloc_info_writer;
1554 List< Handle<Code> > code_targets_;
1556 PositionsRecorder positions_recorder_;
1557 friend class PositionsRecorder;
1561 // Helper class that ensures that there is enough space for generating
1562 // instructions and relocation information. The constructor makes
1563 // sure that there is enough space and (in debug mode) the destructor
1564 // checks that we did not generate too much.
1565 class EnsureSpace BASE_EMBEDDED {
1567 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
1568 if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
1570 space_before_ = assembler_->available_space();
1576 int bytes_generated = space_before_ - assembler_->available_space();
1577 ASSERT(bytes_generated < assembler_->kGap);
1582 Assembler* assembler_;
1588 } } // namespace v8::internal
1590 #endif // V8_X64_ASSEMBLER_X64_H_