1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
5 // A Disassembler object is used to disassemble a block of code instruction by
6 // instruction. The default implementation of the NameConverter object can be
7 // overriden to modify register names or to do symbol lookup on addresses.
9 // The example below will disassemble a block of code and print it to stdout.
11 // NameConverter converter;
12 // Disassembler d(converter);
13 // for (byte* pc = begin; pc < end;) {
14 // v8::internal::EmbeddedVector<char, 256> buffer;
15 // byte* prev_pc = pc;
16 // pc += d.InstructionDecode(buffer, pc);
17 // printf("%p %08x %s\n",
18 // prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer);
21 // The Disassembler class also has a convenience method to disassemble a block
22 // of code into a FILE*, meaning that the above functionality could also be
23 // achieved by just calling Disassembler::Disassemble(stdout, begin, end);
33 #if V8_TARGET_ARCH_MIPS
35 #include "src/base/platform/platform.h"
36 #include "src/disasm.h"
37 #include "src/macro-assembler.h"
38 #include "src/mips/constants-mips.h"
43 //------------------------------------------------------------------------------
45 // Decoder decodes and disassembles instructions into an output buffer.
46 // It uses the converter to convert register names and call destinations into
47 // more informative description.
50 Decoder(const disasm::NameConverter& converter,
51 v8::internal::Vector<char> out_buffer)
52 : converter_(converter),
53 out_buffer_(out_buffer),
55 out_buffer_[out_buffer_pos_] = '\0';
60 // Writes one disassembled instruction into 'buffer' (0-terminated).
61 // Returns the length of the disassembled machine instruction in bytes.
62 int InstructionDecode(byte* instruction);
65 // Bottleneck functions to print into the out_buffer.
66 void PrintChar(const char ch);
67 void Print(const char* str);
69 // Printing of common values.
70 void PrintRegister(int reg);
71 void PrintFPURegister(int freg);
72 void PrintRs(Instruction* instr);
73 void PrintRt(Instruction* instr);
74 void PrintRd(Instruction* instr);
75 void PrintFs(Instruction* instr);
76 void PrintFt(Instruction* instr);
77 void PrintFd(Instruction* instr);
78 void PrintSa(Instruction* instr);
79 void PrintSd(Instruction* instr);
80 void PrintSs1(Instruction* instr);
81 void PrintSs2(Instruction* instr);
82 void PrintBc(Instruction* instr);
83 void PrintCc(Instruction* instr);
84 void PrintFunction(Instruction* instr);
85 void PrintSecondaryField(Instruction* instr);
86 void PrintUImm16(Instruction* instr);
87 void PrintSImm16(Instruction* instr);
88 void PrintXImm16(Instruction* instr);
89 void PrintXImm26(Instruction* instr);
90 void PrintCode(Instruction* instr); // For break and trap instructions.
91 // Printing of instruction name.
92 void PrintInstructionName(Instruction* instr);
94 // Handle formatting of instructions and their options.
95 int FormatRegister(Instruction* instr, const char* option);
96 int FormatFPURegister(Instruction* instr, const char* option);
97 int FormatOption(Instruction* instr, const char* option);
98 void Format(Instruction* instr, const char* format);
99 void Unknown(Instruction* instr);
101 // Each of these functions decodes one particular instruction type.
102 void DecodeTypeRegister(Instruction* instr);
103 void DecodeTypeImmediate(Instruction* instr);
104 void DecodeTypeJump(Instruction* instr);
106 const disasm::NameConverter& converter_;
107 v8::internal::Vector<char> out_buffer_;
110 DISALLOW_COPY_AND_ASSIGN(Decoder);
114 // Support for assertions in the Decoder formatting functions.
115 #define STRING_STARTS_WITH(string, compare_string) \
116 (strncmp(string, compare_string, strlen(compare_string)) == 0)
119 // Append the ch to the output buffer.
120 void Decoder::PrintChar(const char ch) {
121 out_buffer_[out_buffer_pos_++] = ch;
125 // Append the str to the output buffer.
126 void Decoder::Print(const char* str) {
128 while (cur != '\0' && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
132 out_buffer_[out_buffer_pos_] = 0;
136 // Print the register name according to the active name converter.
137 void Decoder::PrintRegister(int reg) {
138 Print(converter_.NameOfCPURegister(reg));
142 void Decoder::PrintRs(Instruction* instr) {
143 int reg = instr->RsValue();
148 void Decoder::PrintRt(Instruction* instr) {
149 int reg = instr->RtValue();
154 void Decoder::PrintRd(Instruction* instr) {
155 int reg = instr->RdValue();
160 // Print the FPUregister name according to the active name converter.
161 void Decoder::PrintFPURegister(int freg) {
162 Print(converter_.NameOfXMMRegister(freg));
166 void Decoder::PrintFs(Instruction* instr) {
167 int freg = instr->RsValue();
168 PrintFPURegister(freg);
172 void Decoder::PrintFt(Instruction* instr) {
173 int freg = instr->RtValue();
174 PrintFPURegister(freg);
178 void Decoder::PrintFd(Instruction* instr) {
179 int freg = instr->RdValue();
180 PrintFPURegister(freg);
184 // Print the integer value of the sa field.
185 void Decoder::PrintSa(Instruction* instr) {
186 int sa = instr->SaValue();
187 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sa);
191 // Print the integer value of the rd field, when it is not used as reg.
192 void Decoder::PrintSd(Instruction* instr) {
193 int sd = instr->RdValue();
194 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", sd);
198 // Print the integer value of the rd field, when used as 'ext' size.
199 void Decoder::PrintSs1(Instruction* instr) {
200 int ss = instr->RdValue();
201 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", ss + 1);
205 // Print the integer value of the rd field, when used as 'ins' size.
206 void Decoder::PrintSs2(Instruction* instr) {
207 int ss = instr->RdValue();
208 int pos = instr->SaValue();
210 SNPrintF(out_buffer_ + out_buffer_pos_, "%d", ss - pos + 1);
214 // Print the integer value of the cc field for the bc1t/f instructions.
215 void Decoder::PrintBc(Instruction* instr) {
216 int cc = instr->FBccValue();
217 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", cc);
221 // Print the integer value of the cc field for the FP compare instructions.
222 void Decoder::PrintCc(Instruction* instr) {
223 int cc = instr->FCccValue();
224 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "cc(%d)", cc);
228 // Print 16-bit unsigned immediate value.
229 void Decoder::PrintUImm16(Instruction* instr) {
230 int32_t imm = instr->Imm16Value();
231 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%u", imm);
235 // Print 16-bit signed immediate value.
236 void Decoder::PrintSImm16(Instruction* instr) {
237 int32_t imm = ((instr->Imm16Value()) << 16) >> 16;
238 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
242 // Print 16-bit hexa immediate value.
243 void Decoder::PrintXImm16(Instruction* instr) {
244 int32_t imm = instr->Imm16Value();
245 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
249 // Print 26-bit immediate value.
250 void Decoder::PrintXImm26(Instruction* instr) {
251 uint32_t imm = instr->Imm26Value() << kImmFieldShift;
252 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
256 // Print 26-bit immediate value.
257 void Decoder::PrintCode(Instruction* instr) {
258 if (instr->OpcodeFieldRaw() != SPECIAL)
259 return; // Not a break or trap instruction.
260 switch (instr->FunctionFieldRaw()) {
262 int32_t code = instr->Bits(25, 6);
263 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
264 "0x%05x (%d)", code, code);
273 int32_t code = instr->Bits(15, 6);
275 SNPrintF(out_buffer_ + out_buffer_pos_, "0x%03x", code);
278 default: // Not a break or trap instruction.
284 // Printing of instruction name.
285 void Decoder::PrintInstructionName(Instruction* instr) {
289 // Handle all register based formatting in this function to reduce the
290 // complexity of FormatOption.
291 int Decoder::FormatRegister(Instruction* instr, const char* format) {
292 DCHECK(format[0] == 'r');
293 if (format[1] == 's') { // 'rs: Rs register.
294 int reg = instr->RsValue();
297 } else if (format[1] == 't') { // 'rt: rt register.
298 int reg = instr->RtValue();
301 } else if (format[1] == 'd') { // 'rd: rd register.
302 int reg = instr->RdValue();
311 // Handle all FPUregister based formatting in this function to reduce the
312 // complexity of FormatOption.
313 int Decoder::FormatFPURegister(Instruction* instr, const char* format) {
314 DCHECK(format[0] == 'f');
315 if (format[1] == 's') { // 'fs: fs register.
316 int reg = instr->FsValue();
317 PrintFPURegister(reg);
319 } else if (format[1] == 't') { // 'ft: ft register.
320 int reg = instr->FtValue();
321 PrintFPURegister(reg);
323 } else if (format[1] == 'd') { // 'fd: fd register.
324 int reg = instr->FdValue();
325 PrintFPURegister(reg);
327 } else if (format[1] == 'r') { // 'fr: fr register.
328 int reg = instr->FrValue();
329 PrintFPURegister(reg);
337 // FormatOption takes a formatting string and interprets it based on
338 // the current instructions. The format string points to the first
339 // character of the option string (the option escape has already been
340 // consumed by the caller.) FormatOption returns the number of
341 // characters that were consumed from the formatting string.
342 int Decoder::FormatOption(Instruction* instr, const char* format) {
344 case 'c': { // 'code for break or trap instructions.
345 DCHECK(STRING_STARTS_WITH(format, "code"));
349 case 'i': { // 'imm16u or 'imm26.
350 if (format[3] == '1') {
351 DCHECK(STRING_STARTS_WITH(format, "imm16"));
352 if (format[5] == 's') {
353 DCHECK(STRING_STARTS_WITH(format, "imm16s"));
355 } else if (format[5] == 'u') {
356 DCHECK(STRING_STARTS_WITH(format, "imm16u"));
359 DCHECK(STRING_STARTS_WITH(format, "imm16x"));
364 DCHECK(STRING_STARTS_WITH(format, "imm26x"));
369 case 'r': { // 'r: registers.
370 return FormatRegister(instr, format);
372 case 'f': { // 'f: FPUregisters.
373 return FormatFPURegister(instr, format);
378 DCHECK(STRING_STARTS_WITH(format, "sa"));
383 DCHECK(STRING_STARTS_WITH(format, "sd"));
388 if (format[2] == '1') {
389 DCHECK(STRING_STARTS_WITH(format, "ss1")); /* ext size */
393 DCHECK(STRING_STARTS_WITH(format, "ss2")); /* ins size */
400 case 'b': { // 'bc - Special for bc1 cc field.
401 DCHECK(STRING_STARTS_WITH(format, "bc"));
405 case 'C': { // 'Cc - Special for c.xx.d cc field.
406 DCHECK(STRING_STARTS_WITH(format, "Cc"));
416 // Format takes a formatting string for a whole instruction and prints it into
417 // the output buffer. All escaped options are handed to FormatOption to be
419 void Decoder::Format(Instruction* instr, const char* format) {
420 char cur = *format++;
421 while ((cur != 0) && (out_buffer_pos_ < (out_buffer_.length() - 1))) {
422 if (cur == '\'') { // Single quote is used as the formatting escape.
423 format += FormatOption(instr, format);
425 out_buffer_[out_buffer_pos_++] = cur;
429 out_buffer_[out_buffer_pos_] = '\0';
433 // For currently unimplemented decodings the disassembler calls Unknown(instr)
434 // which will just print "unknown" of the instruction bits.
435 void Decoder::Unknown(Instruction* instr) {
436 Format(instr, "unknown");
440 void Decoder::DecodeTypeRegister(Instruction* instr) {
441 switch (instr->OpcodeFieldRaw()) {
442 case COP1: // Coprocessor instructions.
443 switch (instr->RsFieldRaw()) {
444 case BC1: // bc1 handled in DecodeTypeImmediate.
448 Format(instr, "mfc1 'rt, 'fs");
451 Format(instr, "mfhc1 'rt, 'fs");
454 Format(instr, "mtc1 'rt, 'fs");
456 // These are called "fs" too, although they are not FPU registers.
458 Format(instr, "ctc1 'rt, 'fs");
461 Format(instr, "cfc1 'rt, 'fs");
464 Format(instr, "mthc1 'rt, 'fs");
467 switch (instr->FunctionFieldRaw()) {
469 Format(instr, "add.d 'fd, 'fs, 'ft");
472 Format(instr, "sub.d 'fd, 'fs, 'ft");
475 Format(instr, "mul.d 'fd, 'fs, 'ft");
478 Format(instr, "div.d 'fd, 'fs, 'ft");
481 Format(instr, "abs.d 'fd, 'fs");
484 Format(instr, "mov.d 'fd, 'fs");
487 Format(instr, "neg.d 'fd, 'fs");
490 Format(instr, "sqrt.d 'fd, 'fs");
493 Format(instr, "cvt.w.d 'fd, 'fs");
496 if (kArchVariant == kMips32r2) {
497 Format(instr, "cvt.l.d 'fd, 'fs");
504 Format(instr, "trunc.w.d 'fd, 'fs");
507 if (kArchVariant == kMips32r2) {
508 Format(instr, "trunc.l.d 'fd, 'fs");
515 Format(instr, "round.w.d 'fd, 'fs");
518 Format(instr, "floor.w.d 'fd, 'fs");
521 Format(instr, "ceil.w.d 'fd, 'fs");
524 Format(instr, "cvt.s.d 'fd, 'fs");
527 Format(instr, "c.f.d 'fs, 'ft, 'Cc");
530 Format(instr, "c.un.d 'fs, 'ft, 'Cc");
533 Format(instr, "c.eq.d 'fs, 'ft, 'Cc");
536 Format(instr, "c.ueq.d 'fs, 'ft, 'Cc");
539 Format(instr, "c.olt.d 'fs, 'ft, 'Cc");
542 Format(instr, "c.ult.d 'fs, 'ft, 'Cc");
545 Format(instr, "c.ole.d 'fs, 'ft, 'Cc");
548 Format(instr, "c.ule.d 'fs, 'ft, 'Cc");
551 Format(instr, "unknown.cop1.d");
556 UNIMPLEMENTED_MIPS();
559 switch (instr->FunctionFieldRaw()) {
560 case CVT_S_W: // Convert word to float (single).
561 Format(instr, "cvt.s.w 'fd, 'fs");
563 case CVT_D_W: // Convert word to double.
564 Format(instr, "cvt.d.w 'fd, 'fs");
571 switch (instr->FunctionFieldRaw()) {
573 if (kArchVariant == kMips32r2) {
574 Format(instr, "cvt.d.l 'fd, 'fs");
581 if (kArchVariant == kMips32r2) {
582 Format(instr, "cvt.s.l 'fd, 'fs");
593 UNIMPLEMENTED_MIPS();
600 switch (instr->FunctionFieldRaw()) {
602 Format(instr, "madd.d 'fd, 'fr, 'fs, 'ft");
609 switch (instr->FunctionFieldRaw()) {
611 Format(instr, "jr 'rs");
614 Format(instr, "jalr 'rs");
617 if ( 0x0 == static_cast<int>(instr->InstructionBits()))
618 Format(instr, "nop");
620 Format(instr, "sll 'rd, 'rt, 'sa");
623 if (instr->RsValue() == 0) {
624 Format(instr, "srl 'rd, 'rt, 'sa");
626 if (kArchVariant == kMips32r2) {
627 Format(instr, "rotr 'rd, 'rt, 'sa");
634 Format(instr, "sra 'rd, 'rt, 'sa");
637 Format(instr, "sllv 'rd, 'rt, 'rs");
640 if (instr->SaValue() == 0) {
641 Format(instr, "srlv 'rd, 'rt, 'rs");
643 if (kArchVariant == kMips32r2) {
644 Format(instr, "rotrv 'rd, 'rt, 'rs");
651 Format(instr, "srav 'rd, 'rt, 'rs");
654 Format(instr, "mfhi 'rd");
657 Format(instr, "mflo 'rd");
660 Format(instr, "mult 'rs, 'rt");
663 Format(instr, "multu 'rs, 'rt");
666 Format(instr, "div 'rs, 'rt");
669 Format(instr, "divu 'rs, 'rt");
672 Format(instr, "add 'rd, 'rs, 'rt");
675 Format(instr, "addu 'rd, 'rs, 'rt");
678 Format(instr, "sub 'rd, 'rs, 'rt");
681 Format(instr, "subu 'rd, 'rs, 'rt");
684 Format(instr, "and 'rd, 'rs, 'rt");
687 if (0 == instr->RsValue()) {
688 Format(instr, "mov 'rd, 'rt");
689 } else if (0 == instr->RtValue()) {
690 Format(instr, "mov 'rd, 'rs");
692 Format(instr, "or 'rd, 'rs, 'rt");
696 Format(instr, "xor 'rd, 'rs, 'rt");
699 Format(instr, "nor 'rd, 'rs, 'rt");
702 Format(instr, "slt 'rd, 'rs, 'rt");
705 Format(instr, "sltu 'rd, 'rs, 'rt");
708 Format(instr, "break, code: 'code");
711 Format(instr, "tge 'rs, 'rt, code: 'code");
714 Format(instr, "tgeu 'rs, 'rt, code: 'code");
717 Format(instr, "tlt 'rs, 'rt, code: 'code");
720 Format(instr, "tltu 'rs, 'rt, code: 'code");
723 Format(instr, "teq 'rs, 'rt, code: 'code");
726 Format(instr, "tne 'rs, 'rt, code: 'code");
729 Format(instr, "movz 'rd, 'rs, 'rt");
732 Format(instr, "movn 'rd, 'rs, 'rt");
735 if (instr->Bit(16)) {
736 Format(instr, "movt 'rd, 'rs, 'bc");
738 Format(instr, "movf 'rd, 'rs, 'bc");
746 switch (instr->FunctionFieldRaw()) {
748 Format(instr, "mul 'rd, 'rs, 'rt");
751 Format(instr, "clz 'rd, 'rs");
758 switch (instr->FunctionFieldRaw()) {
760 if (kArchVariant == kMips32r2) {
761 Format(instr, "ins 'rt, 'rs, 'sa, 'ss2");
768 if (kArchVariant == kMips32r2) {
769 Format(instr, "ext 'rt, 'rs, 'sa, 'ss1");
785 void Decoder::DecodeTypeImmediate(Instruction* instr) {
786 switch (instr->OpcodeFieldRaw()) {
787 // ------------- REGIMM class.
789 switch (instr->RsFieldRaw()) {
791 if (instr->FBtrueValue()) {
792 Format(instr, "bc1t 'bc, 'imm16u");
794 Format(instr, "bc1f 'bc, 'imm16u");
802 switch (instr->RtFieldRaw()) {
804 Format(instr, "bltz 'rs, 'imm16u");
807 Format(instr, "bltzal 'rs, 'imm16u");
810 Format(instr, "bgez 'rs, 'imm16u");
813 Format(instr, "bgezal 'rs, 'imm16u");
818 break; // Case REGIMM.
819 // ------------- Branch instructions.
821 Format(instr, "beq 'rs, 'rt, 'imm16u");
824 Format(instr, "bne 'rs, 'rt, 'imm16u");
827 Format(instr, "blez 'rs, 'imm16u");
830 Format(instr, "bgtz 'rs, 'imm16u");
832 // ------------- Arithmetic instructions.
834 Format(instr, "addi 'rt, 'rs, 'imm16s");
837 Format(instr, "addiu 'rt, 'rs, 'imm16s");
840 Format(instr, "slti 'rt, 'rs, 'imm16s");
843 Format(instr, "sltiu 'rt, 'rs, 'imm16u");
846 Format(instr, "andi 'rt, 'rs, 'imm16x");
849 Format(instr, "ori 'rt, 'rs, 'imm16x");
852 Format(instr, "xori 'rt, 'rs, 'imm16x");
855 Format(instr, "lui 'rt, 'imm16x");
857 // ------------- Memory instructions.
859 Format(instr, "lb 'rt, 'imm16s('rs)");
862 Format(instr, "lh 'rt, 'imm16s('rs)");
865 Format(instr, "lwl 'rt, 'imm16s('rs)");
868 Format(instr, "lw 'rt, 'imm16s('rs)");
871 Format(instr, "lbu 'rt, 'imm16s('rs)");
874 Format(instr, "lhu 'rt, 'imm16s('rs)");
877 Format(instr, "lwr 'rt, 'imm16s('rs)");
880 Format(instr, "pref 'rt, 'imm16s('rs)");
883 Format(instr, "sb 'rt, 'imm16s('rs)");
886 Format(instr, "sh 'rt, 'imm16s('rs)");
889 Format(instr, "swl 'rt, 'imm16s('rs)");
892 Format(instr, "sw 'rt, 'imm16s('rs)");
895 Format(instr, "swr 'rt, 'imm16s('rs)");
898 Format(instr, "lwc1 'ft, 'imm16s('rs)");
901 Format(instr, "ldc1 'ft, 'imm16s('rs)");
904 Format(instr, "swc1 'ft, 'imm16s('rs)");
907 Format(instr, "sdc1 'ft, 'imm16s('rs)");
916 void Decoder::DecodeTypeJump(Instruction* instr) {
917 switch (instr->OpcodeFieldRaw()) {
919 Format(instr, "j 'imm26x");
922 Format(instr, "jal 'imm26x");
930 // Disassemble the instruction at *instr_ptr into the output buffer.
931 int Decoder::InstructionDecode(byte* instr_ptr) {
932 Instruction* instr = Instruction::At(instr_ptr);
933 // Print raw instruction bytes.
934 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
936 instr->InstructionBits());
937 switch (instr->InstructionType()) {
938 case Instruction::kRegisterType: {
939 DecodeTypeRegister(instr);
942 case Instruction::kImmediateType: {
943 DecodeTypeImmediate(instr);
946 case Instruction::kJumpType: {
947 DecodeTypeJump(instr);
951 Format(instr, "UNSUPPORTED");
955 return Instruction::kInstrSize;
959 } } // namespace v8::internal
963 //------------------------------------------------------------------------------
967 const char* NameConverter::NameOfAddress(byte* addr) const {
968 v8::internal::SNPrintF(tmp_buffer_, "%p", addr);
969 return tmp_buffer_.start();
973 const char* NameConverter::NameOfConstant(byte* addr) const {
974 return NameOfAddress(addr);
978 const char* NameConverter::NameOfCPURegister(int reg) const {
979 return v8::internal::Registers::Name(reg);
983 const char* NameConverter::NameOfXMMRegister(int reg) const {
984 return v8::internal::FPURegisters::Name(reg);
988 const char* NameConverter::NameOfByteCPURegister(int reg) const {
989 UNREACHABLE(); // MIPS does not have the concept of a byte register.
994 const char* NameConverter::NameInCode(byte* addr) const {
995 // The default name converter is called for unknown code. So we will not try
996 // to access any memory.
1001 //------------------------------------------------------------------------------
1003 Disassembler::Disassembler(const NameConverter& converter)
1004 : converter_(converter) {}
1007 Disassembler::~Disassembler() {}
1010 int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
1011 byte* instruction) {
1012 v8::internal::Decoder d(converter_, buffer);
1013 return d.InstructionDecode(instruction);
1017 // The MIPS assembler does not currently use constant pools.
1018 int Disassembler::ConstantPoolSizeAt(byte* instruction) {
1023 void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) {
1024 NameConverter converter;
1025 Disassembler d(converter);
1026 for (byte* pc = begin; pc < end;) {
1027 v8::internal::EmbeddedVector<char, 128> buffer;
1030 pc += d.InstructionDecode(buffer, pc);
1031 v8::internal::PrintF(f, "%p %08x %s\n",
1032 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
1039 } // namespace disasm
1041 #endif // V8_TARGET_ARCH_MIPS