1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the distribution.
15 // - Neither the name of Sun Microsystems or the names of contributors may
16 // be used to endorse or promote products derived from this software without
17 // specific prior written permission.
19 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
20 // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2012 the V8 project authors. All rights reserved.
36 #ifndef V8_MIPS_ASSEMBLER_MIPS_H_
37 #define V8_MIPS_ASSEMBLER_MIPS_H_
41 #include "src/assembler.h"
42 #include "src/mips/constants-mips.h"
43 #include "src/serialize.h"
50 // 1) We would prefer to use an enum, but enum values are assignment-
51 // compatible with int, which has caused code-generation bugs.
53 // 2) We would prefer to use a class instead of a struct but we don't like
54 // the register initialization to depend on the particular initialization
55 // order (which appears to be different on OS X, Linux, and Windows for the
56 // installed versions of C++ we tried). Using a struct permits C-style
57 // "initialization". Also, the Register objects cannot be const as this
58 // forces initialization stubs in MSVC, making us dependent on initialization
61 // 3) By not using an enum, we are possibly preventing the compiler from
62 // doing certain constant folds, which may significantly reduce the
63 // code generated for some assembly instructions (because they boil down
64 // to a few constants). If this is a problem, we could change the code
65 // such that we use an enum in optimized mode, and the struct in debug
66 // mode. This way we get the compile-time error checking in debug mode
67 // and best performance in optimized code.
70 // -----------------------------------------------------------------------------
71 // Implementation of Register and FPURegister.
75 static const int kNumRegisters = v8::internal::kNumRegisters;
76 static const int kMaxNumAllocatableRegisters = 14; // v0 through t6 and cp.
77 static const int kSizeInBytes = 4;
78 static const int kCpRegister = 23; // cp (s7) is the 23rd register.
80 #if defined(V8_TARGET_LITTLE_ENDIAN)
81 static const int kMantissaOffset = 0;
82 static const int kExponentOffset = 4;
83 #elif defined(V8_TARGET_BIG_ENDIAN)
84 static const int kMantissaOffset = 4;
85 static const int kExponentOffset = 0;
87 #error Unknown endianness
90 inline static int NumAllocatableRegisters();
92 static int ToAllocationIndex(Register reg) {
93 DCHECK((reg.code() - 2) < (kMaxNumAllocatableRegisters - 1) ||
94 reg.is(from_code(kCpRegister)));
95 return reg.is(from_code(kCpRegister)) ?
96 kMaxNumAllocatableRegisters - 1 : // Return last index for 'cp'.
97 reg.code() - 2; // zero_reg and 'at' are skipped.
100 static Register FromAllocationIndex(int index) {
101 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
102 return index == kMaxNumAllocatableRegisters - 1 ?
103 from_code(kCpRegister) : // Last index is always the 'cp' register.
104 from_code(index + 2); // zero_reg and 'at' are skipped.
107 static const char* AllocationIndexToString(int index) {
108 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
109 const char* const names[] = {
128 static Register from_code(int code) {
129 Register r = { code };
133 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
134 bool is(Register reg) const { return code_ == reg.code_; }
144 // Unfortunately we can't make this private in a struct.
148 #define REGISTER(N, C) \
149 const int kRegister_ ## N ## _Code = C; \
150 const Register N = { C }
152 REGISTER(no_reg, -1);
154 REGISTER(zero_reg, 0);
155 // at: Reserved for synthetic instructions.
157 // v0, v1: Used when returning multiple values from subroutines.
160 // a0 - a4: Used to pass non-FP parameters.
165 // t0 - t9: Can be used without reservation, act as temporary registers and are
166 // allowed to be destroyed by subroutines.
175 // s0 - s7: Subroutine register variables. Subroutines that write to these
176 // registers must restore their values before exiting so that the caller can
177 // expect the values to be preserved.
188 // k0, k1: Reserved for system calls and interrupt handlers.
193 // sp: Stack pointer.
195 // fp: Frame pointer.
197 // ra: Return address pointer.
203 int ToNumber(Register reg);
205 Register ToRegister(int num);
207 // Coprocessor register.
209 static const int kMaxNumRegisters = v8::internal::kNumFPURegisters;
211 // TODO(plind): Warning, inconsistent numbering here. kNumFPURegisters refers
212 // to number of 32-bit FPU regs, but kNumAllocatableRegisters refers to
213 // number of Double regs (64-bit regs, or FPU-reg-pairs).
215 // A few double registers are reserved: one as a scratch register and one to
218 // f30: scratch register.
219 static const int kNumReservedRegisters = 2;
220 static const int kMaxNumAllocatableRegisters = kMaxNumRegisters / 2 -
221 kNumReservedRegisters;
223 inline static int NumRegisters();
224 inline static int NumAllocatableRegisters();
226 // TODO(turbofan): Proper support for float32.
227 inline static int NumAllocatableAliasedRegisters();
229 inline static int ToAllocationIndex(FPURegister reg);
230 static const char* AllocationIndexToString(int index);
232 static FPURegister FromAllocationIndex(int index) {
233 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
234 return from_code(index * 2);
237 static FPURegister from_code(int code) {
238 FPURegister r = { code };
242 bool is_valid() const { return 0 <= code_ && code_ < kMaxNumRegisters ; }
243 bool is(FPURegister creg) const { return code_ == creg.code_; }
244 FPURegister low() const {
245 // Find low reg of a Double-reg pair, which is the reg itself.
246 DCHECK(code_ % 2 == 0); // Specified Double reg must be even.
249 DCHECK(reg.is_valid());
252 FPURegister high() const {
253 // Find high reg of a Doubel-reg pair, which is reg + 1.
254 DCHECK(code_ % 2 == 0); // Specified Double reg must be even.
256 reg.code_ = code_ + 1;
257 DCHECK(reg.is_valid());
269 void setcode(int f) {
273 // Unfortunately we can't make this private in a struct.
277 // V8 now supports the O32 ABI, and the FPU Registers are organized as 32
278 // 32-bit registers, f0 through f31. When used as 'double' they are used
279 // in pairs, starting with the even numbered register. So a double operation
280 // on f0 really uses f0 and f1.
281 // (Modern mips hardware also supports 32 64-bit registers, via setting
282 // (priviledged) Status Register FR bit to 1. This is used by the N32 ABI,
283 // but it is not in common use. Someday we will want to support this in v8.)
285 // For O32 ABI, Floats and Doubles refer to same set of 32 32-bit registers.
286 typedef FPURegister DoubleRegister;
287 typedef FPURegister FloatRegister;
289 const FPURegister no_freg = { -1 };
291 const FPURegister f0 = { 0 }; // Return value in hard float mode.
292 const FPURegister f1 = { 1 };
293 const FPURegister f2 = { 2 };
294 const FPURegister f3 = { 3 };
295 const FPURegister f4 = { 4 };
296 const FPURegister f5 = { 5 };
297 const FPURegister f6 = { 6 };
298 const FPURegister f7 = { 7 };
299 const FPURegister f8 = { 8 };
300 const FPURegister f9 = { 9 };
301 const FPURegister f10 = { 10 };
302 const FPURegister f11 = { 11 };
303 const FPURegister f12 = { 12 }; // Arg 0 in hard float mode.
304 const FPURegister f13 = { 13 };
305 const FPURegister f14 = { 14 }; // Arg 1 in hard float mode.
306 const FPURegister f15 = { 15 };
307 const FPURegister f16 = { 16 };
308 const FPURegister f17 = { 17 };
309 const FPURegister f18 = { 18 };
310 const FPURegister f19 = { 19 };
311 const FPURegister f20 = { 20 };
312 const FPURegister f21 = { 21 };
313 const FPURegister f22 = { 22 };
314 const FPURegister f23 = { 23 };
315 const FPURegister f24 = { 24 };
316 const FPURegister f25 = { 25 };
317 const FPURegister f26 = { 26 };
318 const FPURegister f27 = { 27 };
319 const FPURegister f28 = { 28 };
320 const FPURegister f29 = { 29 };
321 const FPURegister f30 = { 30 };
322 const FPURegister f31 = { 31 };
325 // cp is assumed to be a callee saved register.
326 // Defined using #define instead of "static const Register&" because Clang
327 // complains otherwise when a compilation unit that includes this header
328 // doesn't use the variables.
329 #define kRootRegister s6
331 #define kLithiumScratchReg s3
332 #define kLithiumScratchReg2 s4
333 #define kLithiumScratchDouble f30
334 #define kDoubleRegZero f28
335 // Used on mips32r6 for compare operations.
336 #define kDoubleCompareReg f31
338 // FPU (coprocessor 1) control registers.
339 // Currently only FCSR (#31) is implemented.
340 struct FPUControlRegister {
341 bool is_valid() const { return code_ == kFCSRRegister; }
342 bool is(FPUControlRegister creg) const { return code_ == creg.code_; }
351 void setcode(int f) {
355 // Unfortunately we can't make this private in a struct.
359 const FPUControlRegister no_fpucreg = { kInvalidFPUControlRegister };
360 const FPUControlRegister FCSR = { kFCSRRegister };
362 struct SIMD128Register {
363 static const int kMaxNumRegisters = 0;
365 static int ToAllocationIndex(SIMD128Register reg) {
370 static const char* AllocationIndexToString(int index) {
376 // -----------------------------------------------------------------------------
377 // Machine instruction Operands.
379 // Class Operand represents a shifter operand in data processing instructions.
380 class Operand BASE_EMBEDDED {
383 INLINE(explicit Operand(int32_t immediate,
384 RelocInfo::Mode rmode = RelocInfo::NONE32));
385 INLINE(explicit Operand(const ExternalReference& f));
386 INLINE(explicit Operand(const char* s));
387 INLINE(explicit Operand(Object** opp));
388 INLINE(explicit Operand(Context** cpp));
389 explicit Operand(Handle<Object> handle);
390 INLINE(explicit Operand(Smi* value));
393 INLINE(explicit Operand(Register rm));
395 // Return true if this is a register operand.
396 INLINE(bool is_reg() const);
398 inline int32_t immediate() const {
403 Register rm() const { return rm_; }
407 int32_t imm32_; // Valid if rm_ == no_reg.
408 RelocInfo::Mode rmode_;
410 friend class Assembler;
411 friend class MacroAssembler;
415 // On MIPS we have only one adressing mode with base_reg + offset.
416 // Class MemOperand represents a memory operand in load and store instructions.
417 class MemOperand : public Operand {
419 // Immediate value attached to offset.
421 offset_minus_one = -1,
425 explicit MemOperand(Register rn, int32_t offset = 0);
426 explicit MemOperand(Register rn, int32_t unit, int32_t multiplier,
427 OffsetAddend offset_addend = offset_zero);
428 int32_t offset() const { return offset_; }
430 bool OffsetIsInt16Encodable() const {
431 return is_int16(offset_);
437 friend class Assembler;
441 class Assembler : public AssemblerBase {
443 // Create an assembler. Instructions and relocation information are emitted
444 // into a buffer, with the instructions starting from the beginning and the
445 // relocation information starting from the end of the buffer. See CodeDesc
446 // for a detailed comment on the layout (globals.h).
448 // If the provided buffer is NULL, the assembler allocates and grows its own
449 // buffer, and buffer_size determines the initial buffer size. The buffer is
450 // owned by the assembler and deallocated upon destruction of the assembler.
452 // If the provided buffer is not NULL, the assembler uses the provided buffer
453 // for code generation and assumes its size to be buffer_size. If the buffer
454 // is too small, a fatal error occurs. No deallocation of the buffer is done
455 // upon destruction of the assembler.
456 Assembler(Isolate* isolate, void* buffer, int buffer_size);
457 virtual ~Assembler() { }
459 // GetCode emits any pending (non-emitted) code and fills the descriptor
460 // desc. GetCode() is idempotent; it returns the same result if no other
461 // Assembler functions are invoked in between GetCode() calls.
462 void GetCode(CodeDesc* desc);
464 // Label operations & relative jumps (PPUM Appendix D).
466 // Takes a branch opcode (cc) and a label (L) and generates
467 // either a backward branch or a forward branch and links it
468 // to the label fixup chain. Usage:
470 // Label L; // unbound label
471 // j(cc, &L); // forward branch to unbound label
472 // bind(&L); // bind label to the current pc
473 // j(cc, &L); // backward branch to bound label
474 // bind(&L); // illegal: a label may be bound only once
476 // Note: The same Label can be used for forward and backward branches
477 // but it may be bound only once.
478 void bind(Label* L); // Binds an unbound label L to current code position.
479 // Determines if Label is bound and near enough so that branch instruction
480 // can be used to reach it, instead of jump instruction.
481 bool is_near(Label* L);
483 // Returns the branch offset to the given label from the current code
484 // position. Links the label to the current position if it is still unbound.
485 // Manages the jump elimination optimization if the second parameter is true.
486 int32_t branch_offset(Label* L, bool jump_elimination_allowed);
487 int32_t branch_offset_compact(Label* L, bool jump_elimination_allowed);
488 int32_t branch_offset21(Label* L, bool jump_elimination_allowed);
489 int32_t branch_offset21_compact(Label* L, bool jump_elimination_allowed);
490 int32_t shifted_branch_offset(Label* L, bool jump_elimination_allowed) {
491 int32_t o = branch_offset(L, jump_elimination_allowed);
492 DCHECK((o & 3) == 0); // Assert the offset is aligned.
495 int32_t shifted_branch_offset_compact(Label* L,
496 bool jump_elimination_allowed) {
497 int32_t o = branch_offset_compact(L, jump_elimination_allowed);
498 DCHECK((o & 3) == 0); // Assert the offset is aligned.
501 uint32_t jump_address(Label* L);
503 // Puts a labels target address at the given position.
504 // The high 8 bits are set to zero.
505 void label_at_put(Label* L, int at_offset);
507 // Read/Modify the code target address in the branch/call instruction at pc.
508 static Address target_address_at(Address pc);
509 static void set_target_address_at(Address pc,
511 ICacheFlushMode icache_flush_mode =
512 FLUSH_ICACHE_IF_NEEDED);
513 // On MIPS there is no Constant Pool so we skip that parameter.
514 INLINE(static Address target_address_at(Address pc,
515 ConstantPoolArray* constant_pool)) {
516 return target_address_at(pc);
518 INLINE(static void set_target_address_at(Address pc,
519 ConstantPoolArray* constant_pool,
521 ICacheFlushMode icache_flush_mode =
522 FLUSH_ICACHE_IF_NEEDED)) {
523 set_target_address_at(pc, target, icache_flush_mode);
525 INLINE(static Address target_address_at(Address pc, Code* code)) {
526 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
527 return target_address_at(pc, constant_pool);
529 INLINE(static void set_target_address_at(Address pc,
532 ICacheFlushMode icache_flush_mode =
533 FLUSH_ICACHE_IF_NEEDED)) {
534 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
535 set_target_address_at(pc, constant_pool, target, icache_flush_mode);
538 // Return the code target address at a call site from the return address
539 // of that call in the instruction stream.
540 inline static Address target_address_from_return_address(Address pc);
542 // Return the code target address of the patch debug break slot
543 inline static Address break_address_from_return_address(Address pc);
545 static void JumpLabelToJumpRegister(Address pc);
547 static void QuietNaN(HeapObject* nan);
549 // This sets the branch destination (which gets loaded at the call address).
550 // This is for calls and branches within generated code. The serializer
551 // has already deserialized the lui/ori instructions etc.
552 inline static void deserialization_set_special_target_at(
553 Address instruction_payload, Code* code, Address target) {
554 set_target_address_at(
555 instruction_payload - kInstructionsFor32BitConstant * kInstrSize,
560 // Size of an instruction.
561 static const int kInstrSize = sizeof(Instr);
563 // Difference between address of current opcode and target address offset.
564 static const int kBranchPCOffset = 4;
566 // Here we are patching the address in the LUI/ORI instruction pair.
567 // These values are used in the serialization process and must be zero for
568 // MIPS platform, as Code, Embedded Object or External-reference pointers
569 // are split across two consecutive instructions and don't exist separately
570 // in the code, so the serializer should not step forwards in memory after
571 // a target is resolved and written.
572 static const int kSpecialTargetSize = 0;
574 // Number of consecutive instructions used to store 32bit constant.
575 // Before jump-optimizations, this constant was used in
576 // RelocInfo::target_address_address() function to tell serializer address of
577 // the instruction that follows LUI/ORI instruction pair. Now, with new jump
578 // optimization, where jump-through-register instruction that usually
579 // follows LUI/ORI pair is substituted with J/JAL, this constant equals
580 // to 3 instructions (LUI+ORI+J/JAL/JR/JALR).
581 static const int kInstructionsFor32BitConstant = 3;
583 // Distance between the instruction referring to the address of the call
584 // target and the return address.
585 static const int kCallTargetAddressOffset = 4 * kInstrSize;
587 // Distance between start of patched return sequence and the emitted address
589 static const int kPatchReturnSequenceAddressOffset = 0;
591 // Distance between start of patched debug break slot and the emitted address
593 static const int kPatchDebugBreakSlotAddressOffset = 0 * kInstrSize;
595 // Difference between address of current opcode and value read from pc
597 static const int kPcLoadDelta = 4;
599 static const int kPatchDebugBreakSlotReturnOffset = 4 * kInstrSize;
601 // Number of instructions used for the JS return sequence. The constant is
602 // used by the debugger to patch the JS return sequence.
603 static const int kJSReturnSequenceInstructions = 7;
604 static const int kDebugBreakSlotInstructions = 4;
605 static const int kDebugBreakSlotLength =
606 kDebugBreakSlotInstructions * kInstrSize;
609 // ---------------------------------------------------------------------------
612 // Insert the smallest number of nop instructions
613 // possible to align the pc offset to a multiple
614 // of m. m must be a power of 2 (>= 4).
616 // Aligns code to something that's optimal for a jump target for the platform.
617 void CodeTargetAlign();
619 // Different nop operations are used by the code generator to detect certain
620 // states of the generated code.
621 enum NopMarkerTypes {
625 PROPERTY_ACCESS_INLINED,
626 PROPERTY_ACCESS_INLINED_CONTEXT,
627 PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE,
630 FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED,
632 CODE_AGE_MARKER_NOP = 6,
633 CODE_AGE_SEQUENCE_NOP
636 // Type == 0 is the default non-marking nop. For mips this is a
637 // sll(zero_reg, zero_reg, 0). We use rt_reg == at for non-zero
638 // marking, to avoid conflict with ssnop and ehb instructions.
639 void nop(unsigned int type = 0) {
641 Register nop_rt_reg = (type == 0) ? zero_reg : at;
642 sll(zero_reg, nop_rt_reg, type, true);
646 // --------Branch-and-jump-instructions----------
647 // We don't use likely variant of instructions.
648 void b(int16_t offset);
649 void b(Label* L) { b(branch_offset(L, false)>>2); }
650 void bal(int16_t offset);
651 void bal(Label* L) { bal(branch_offset(L, false)>>2); }
653 void beq(Register rs, Register rt, int16_t offset);
654 void beq(Register rs, Register rt, Label* L) {
655 beq(rs, rt, branch_offset(L, false) >> 2);
657 void bgez(Register rs, int16_t offset);
658 void bgezc(Register rt, int16_t offset);
659 void bgezc(Register rt, Label* L) {
660 bgezc(rt, branch_offset_compact(L, false)>>2);
662 void bgeuc(Register rs, Register rt, int16_t offset);
663 void bgeuc(Register rs, Register rt, Label* L) {
664 bgeuc(rs, rt, branch_offset_compact(L, false)>>2);
666 void bgec(Register rs, Register rt, int16_t offset);
667 void bgec(Register rs, Register rt, Label* L) {
668 bgec(rs, rt, branch_offset_compact(L, false)>>2);
670 void bgezal(Register rs, int16_t offset);
671 void bgezalc(Register rt, int16_t offset);
672 void bgezalc(Register rt, Label* L) {
673 bgezalc(rt, branch_offset_compact(L, false)>>2);
675 void bgezall(Register rs, int16_t offset);
676 void bgezall(Register rs, Label* L) {
677 bgezall(rs, branch_offset(L, false)>>2);
679 void bgtz(Register rs, int16_t offset);
680 void bgtzc(Register rt, int16_t offset);
681 void bgtzc(Register rt, Label* L) {
682 bgtzc(rt, branch_offset_compact(L, false)>>2);
684 void blez(Register rs, int16_t offset);
685 void blezc(Register rt, int16_t offset);
686 void blezc(Register rt, Label* L) {
687 blezc(rt, branch_offset_compact(L, false)>>2);
689 void bltz(Register rs, int16_t offset);
690 void bltzc(Register rt, int16_t offset);
691 void bltzc(Register rt, Label* L) {
692 bltzc(rt, branch_offset_compact(L, false)>>2);
694 void bltuc(Register rs, Register rt, int16_t offset);
695 void bltuc(Register rs, Register rt, Label* L) {
696 bltuc(rs, rt, branch_offset_compact(L, false)>>2);
698 void bltc(Register rs, Register rt, int16_t offset);
699 void bltc(Register rs, Register rt, Label* L) {
700 bltc(rs, rt, branch_offset_compact(L, false)>>2);
702 void bltzal(Register rs, int16_t offset);
703 void blezalc(Register rt, int16_t offset);
704 void blezalc(Register rt, Label* L) {
705 blezalc(rt, branch_offset_compact(L, false)>>2);
707 void bltzalc(Register rt, int16_t offset);
708 void bltzalc(Register rt, Label* L) {
709 bltzalc(rt, branch_offset_compact(L, false)>>2);
711 void bgtzalc(Register rt, int16_t offset);
712 void bgtzalc(Register rt, Label* L) {
713 bgtzalc(rt, branch_offset_compact(L, false)>>2);
715 void beqzalc(Register rt, int16_t offset);
716 void beqzalc(Register rt, Label* L) {
717 beqzalc(rt, branch_offset_compact(L, false)>>2);
719 void beqc(Register rs, Register rt, int16_t offset);
720 void beqc(Register rs, Register rt, Label* L) {
721 beqc(rs, rt, branch_offset_compact(L, false)>>2);
723 void beqzc(Register rs, int32_t offset);
724 void beqzc(Register rs, Label* L) {
725 beqzc(rs, branch_offset21_compact(L, false)>>2);
727 void bnezalc(Register rt, int16_t offset);
728 void bnezalc(Register rt, Label* L) {
729 bnezalc(rt, branch_offset_compact(L, false)>>2);
731 void bnec(Register rs, Register rt, int16_t offset);
732 void bnec(Register rs, Register rt, Label* L) {
733 bnec(rs, rt, branch_offset_compact(L, false)>>2);
735 void bnezc(Register rt, int32_t offset);
736 void bnezc(Register rt, Label* L) {
737 bnezc(rt, branch_offset21_compact(L, false)>>2);
739 void bne(Register rs, Register rt, int16_t offset);
740 void bne(Register rs, Register rt, Label* L) {
741 bne(rs, rt, branch_offset(L, false)>>2);
743 void bovc(Register rs, Register rt, int16_t offset);
744 void bovc(Register rs, Register rt, Label* L) {
745 bovc(rs, rt, branch_offset_compact(L, false)>>2);
747 void bnvc(Register rs, Register rt, int16_t offset);
748 void bnvc(Register rs, Register rt, Label* L) {
749 bnvc(rs, rt, branch_offset_compact(L, false)>>2);
752 // Never use the int16_t b(l)cond version with a branch offset
753 // instead of using the Label* version.
755 // Jump targets must be in the current 256 MB-aligned region. i.e. 28 bits.
756 void j(int32_t target);
757 void jal(int32_t target);
758 void jalr(Register rs, Register rd = ra);
759 void jr(Register target);
760 void j_or_jr(int32_t target, Register rs);
761 void jal_or_jalr(int32_t target, Register rs);
764 // -------Data-processing-instructions---------
767 void addu(Register rd, Register rs, Register rt);
768 void subu(Register rd, Register rs, Register rt);
769 void mult(Register rs, Register rt);
770 void multu(Register rs, Register rt);
771 void div(Register rs, Register rt);
772 void divu(Register rs, Register rt);
773 void div(Register rd, Register rs, Register rt);
774 void divu(Register rd, Register rs, Register rt);
775 void mod(Register rd, Register rs, Register rt);
776 void modu(Register rd, Register rs, Register rt);
777 void mul(Register rd, Register rs, Register rt);
778 void muh(Register rd, Register rs, Register rt);
779 void mulu(Register rd, Register rs, Register rt);
780 void muhu(Register rd, Register rs, Register rt);
782 void addiu(Register rd, Register rs, int32_t j);
785 void and_(Register rd, Register rs, Register rt);
786 void or_(Register rd, Register rs, Register rt);
787 void xor_(Register rd, Register rs, Register rt);
788 void nor(Register rd, Register rs, Register rt);
790 void andi(Register rd, Register rs, int32_t j);
791 void ori(Register rd, Register rs, int32_t j);
792 void xori(Register rd, Register rs, int32_t j);
793 void lui(Register rd, int32_t j);
794 void aui(Register rs, Register rt, int32_t j);
797 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop
798 // and may cause problems in normal code. coming_from_nop makes sure this
800 void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false);
801 void sllv(Register rd, Register rt, Register rs);
802 void srl(Register rd, Register rt, uint16_t sa);
803 void srlv(Register rd, Register rt, Register rs);
804 void sra(Register rt, Register rd, uint16_t sa);
805 void srav(Register rt, Register rd, Register rs);
806 void rotr(Register rd, Register rt, uint16_t sa);
807 void rotrv(Register rd, Register rt, Register rs);
810 // ------------Memory-instructions-------------
812 void lb(Register rd, const MemOperand& rs);
813 void lbu(Register rd, const MemOperand& rs);
814 void lh(Register rd, const MemOperand& rs);
815 void lhu(Register rd, const MemOperand& rs);
816 void lw(Register rd, const MemOperand& rs);
817 void lwl(Register rd, const MemOperand& rs);
818 void lwr(Register rd, const MemOperand& rs);
819 void sb(Register rd, const MemOperand& rs);
820 void sh(Register rd, const MemOperand& rs);
821 void sw(Register rd, const MemOperand& rs);
822 void swl(Register rd, const MemOperand& rs);
823 void swr(Register rd, const MemOperand& rs);
826 // ----------------Prefetch--------------------
828 void pref(int32_t hint, const MemOperand& rs);
831 // -------------Misc-instructions--------------
833 // Break / Trap instructions.
834 void break_(uint32_t code, bool break_as_stop = false);
835 void stop(const char* msg, uint32_t code = kMaxStopCode);
836 void tge(Register rs, Register rt, uint16_t code);
837 void tgeu(Register rs, Register rt, uint16_t code);
838 void tlt(Register rs, Register rt, uint16_t code);
839 void tltu(Register rs, Register rt, uint16_t code);
840 void teq(Register rs, Register rt, uint16_t code);
841 void tne(Register rs, Register rt, uint16_t code);
843 // Move from HI/LO register.
844 void mfhi(Register rd);
845 void mflo(Register rd);
848 void slt(Register rd, Register rs, Register rt);
849 void sltu(Register rd, Register rs, Register rt);
850 void slti(Register rd, Register rs, int32_t j);
851 void sltiu(Register rd, Register rs, int32_t j);
854 void movz(Register rd, Register rs, Register rt);
855 void movn(Register rd, Register rs, Register rt);
856 void movt(Register rd, Register rs, uint16_t cc = 0);
857 void movf(Register rd, Register rs, uint16_t cc = 0);
859 void sel(SecondaryField fmt, FPURegister fd, FPURegister ft,
860 FPURegister fs, uint8_t sel);
861 void seleqz(Register rs, Register rt, Register rd);
862 void seleqz(SecondaryField fmt, FPURegister fd, FPURegister ft,
864 void selnez(Register rs, Register rt, Register rd);
865 void selnez(SecondaryField fmt, FPURegister fd, FPURegister ft,
869 void clz(Register rd, Register rs);
870 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size);
871 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size);
873 // --------Coprocessor-instructions----------------
875 // Load, store, and move.
876 void lwc1(FPURegister fd, const MemOperand& src);
877 void ldc1(FPURegister fd, const MemOperand& src);
879 void swc1(FPURegister fs, const MemOperand& dst);
880 void sdc1(FPURegister fs, const MemOperand& dst);
882 void mtc1(Register rt, FPURegister fs);
883 void mthc1(Register rt, FPURegister fs);
885 void mfc1(Register rt, FPURegister fs);
886 void mfhc1(Register rt, FPURegister fs);
888 void ctc1(Register rt, FPUControlRegister fs);
889 void cfc1(Register rt, FPUControlRegister fs);
892 void add_d(FPURegister fd, FPURegister fs, FPURegister ft);
893 void sub_d(FPURegister fd, FPURegister fs, FPURegister ft);
894 void mul_d(FPURegister fd, FPURegister fs, FPURegister ft);
895 void madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft);
896 void div_d(FPURegister fd, FPURegister fs, FPURegister ft);
897 void abs_d(FPURegister fd, FPURegister fs);
898 void mov_d(FPURegister fd, FPURegister fs);
899 void neg_d(FPURegister fd, FPURegister fs);
900 void sqrt_d(FPURegister fd, FPURegister fs);
903 void cvt_w_s(FPURegister fd, FPURegister fs);
904 void cvt_w_d(FPURegister fd, FPURegister fs);
905 void trunc_w_s(FPURegister fd, FPURegister fs);
906 void trunc_w_d(FPURegister fd, FPURegister fs);
907 void round_w_s(FPURegister fd, FPURegister fs);
908 void round_w_d(FPURegister fd, FPURegister fs);
909 void floor_w_s(FPURegister fd, FPURegister fs);
910 void floor_w_d(FPURegister fd, FPURegister fs);
911 void ceil_w_s(FPURegister fd, FPURegister fs);
912 void ceil_w_d(FPURegister fd, FPURegister fs);
914 void cvt_l_s(FPURegister fd, FPURegister fs);
915 void cvt_l_d(FPURegister fd, FPURegister fs);
916 void trunc_l_s(FPURegister fd, FPURegister fs);
917 void trunc_l_d(FPURegister fd, FPURegister fs);
918 void round_l_s(FPURegister fd, FPURegister fs);
919 void round_l_d(FPURegister fd, FPURegister fs);
920 void floor_l_s(FPURegister fd, FPURegister fs);
921 void floor_l_d(FPURegister fd, FPURegister fs);
922 void ceil_l_s(FPURegister fd, FPURegister fs);
923 void ceil_l_d(FPURegister fd, FPURegister fs);
925 void min(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs);
926 void mina(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs);
927 void max(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs);
928 void maxa(SecondaryField fmt, FPURegister fd, FPURegister ft, FPURegister fs);
930 void cvt_s_w(FPURegister fd, FPURegister fs);
931 void cvt_s_l(FPURegister fd, FPURegister fs);
932 void cvt_s_d(FPURegister fd, FPURegister fs);
934 void cvt_d_w(FPURegister fd, FPURegister fs);
935 void cvt_d_l(FPURegister fd, FPURegister fs);
936 void cvt_d_s(FPURegister fd, FPURegister fs);
938 // Conditions and branches for MIPSr6.
939 void cmp(FPUCondition cond, SecondaryField fmt,
940 FPURegister fd, FPURegister ft, FPURegister fs);
942 void bc1eqz(int16_t offset, FPURegister ft);
943 void bc1eqz(Label* L, FPURegister ft) {
944 bc1eqz(branch_offset(L, false)>>2, ft);
946 void bc1nez(int16_t offset, FPURegister ft);
947 void bc1nez(Label* L, FPURegister ft) {
948 bc1nez(branch_offset(L, false)>>2, ft);
951 // Conditions and branches for non MIPSr6.
952 void c(FPUCondition cond, SecondaryField fmt,
953 FPURegister ft, FPURegister fs, uint16_t cc = 0);
955 void bc1f(int16_t offset, uint16_t cc = 0);
956 void bc1f(Label* L, uint16_t cc = 0) { bc1f(branch_offset(L, false)>>2, cc); }
957 void bc1t(int16_t offset, uint16_t cc = 0);
958 void bc1t(Label* L, uint16_t cc = 0) { bc1t(branch_offset(L, false)>>2, cc); }
959 void fcmp(FPURegister src1, const double src2, FPUCondition cond);
961 // Check the code size generated from label to here.
962 int SizeOfCodeGeneratedSince(Label* label) {
963 return pc_offset() - label->pos();
966 // Check the number of instructions generated from label to here.
967 int InstructionsGeneratedSince(Label* label) {
968 return SizeOfCodeGeneratedSince(label) / kInstrSize;
971 // Class for scoping postponing the trampoline pool generation.
972 class BlockTrampolinePoolScope {
974 explicit BlockTrampolinePoolScope(Assembler* assem) : assem_(assem) {
975 assem_->StartBlockTrampolinePool();
977 ~BlockTrampolinePoolScope() {
978 assem_->EndBlockTrampolinePool();
984 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockTrampolinePoolScope);
987 // Class for postponing the assembly buffer growth. Typically used for
988 // sequences of instructions that must be emitted as a unit, before
989 // buffer growth (and relocation) can occur.
990 // This blocking scope is not nestable.
991 class BlockGrowBufferScope {
993 explicit BlockGrowBufferScope(Assembler* assem) : assem_(assem) {
994 assem_->StartBlockGrowBuffer();
996 ~BlockGrowBufferScope() {
997 assem_->EndBlockGrowBuffer();
1003 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockGrowBufferScope);
1008 // Mark address of the ExitJSFrame code.
1009 void RecordJSReturn();
1011 // Mark address of a debug break slot.
1012 void RecordDebugBreakSlot();
1014 // Record the AST id of the CallIC being compiled, so that it can be placed
1015 // in the relocation information.
1016 void SetRecordedAstId(TypeFeedbackId ast_id) {
1017 DCHECK(recorded_ast_id_.IsNone());
1018 recorded_ast_id_ = ast_id;
1021 TypeFeedbackId RecordedAstId() {
1022 DCHECK(!recorded_ast_id_.IsNone());
1023 return recorded_ast_id_;
1026 void ClearRecordedAstId() { recorded_ast_id_ = TypeFeedbackId::None(); }
1028 // Record a comment relocation entry that can be used by a disassembler.
1029 // Use --code-comments to enable.
1030 void RecordComment(const char* msg);
1032 static int RelocateInternalReference(byte* pc, intptr_t pc_delta);
1034 // Writes a single byte or word of data in the code stream. Used for
1035 // inline tables, e.g., jump-tables.
1036 void db(uint8_t data);
1037 void dd(uint32_t data);
1039 // Emits the address of the code stub's first instruction.
1040 void emit_code_stub_address(Code* stub);
1042 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1044 // Postpone the generation of the trampoline pool for the specified number of
1046 void BlockTrampolinePoolFor(int instructions);
1048 // Check if there is less than kGap bytes available in the buffer.
1049 // If this is the case, we need to grow the buffer before emitting
1050 // an instruction or relocation information.
1051 inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; }
1053 // Get the number of bytes available in the buffer.
1054 inline int available_space() const { return reloc_info_writer.pos() - pc_; }
1056 // Read/patch instructions.
1057 static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); }
1058 static void instr_at_put(byte* pc, Instr instr) {
1059 *reinterpret_cast<Instr*>(pc) = instr;
1061 Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); }
1062 void instr_at_put(int pos, Instr instr) {
1063 *reinterpret_cast<Instr*>(buffer_ + pos) = instr;
1066 // Check if an instruction is a branch of some kind.
1067 static bool IsBranch(Instr instr);
1068 static bool IsBeq(Instr instr);
1069 static bool IsBne(Instr instr);
1071 static bool IsJump(Instr instr);
1072 static bool IsJ(Instr instr);
1073 static bool IsLui(Instr instr);
1074 static bool IsOri(Instr instr);
1076 static bool IsJal(Instr instr);
1077 static bool IsJr(Instr instr);
1078 static bool IsJalr(Instr instr);
1080 static bool IsNop(Instr instr, unsigned int type);
1081 static bool IsPop(Instr instr);
1082 static bool IsPush(Instr instr);
1083 static bool IsLwRegFpOffset(Instr instr);
1084 static bool IsSwRegFpOffset(Instr instr);
1085 static bool IsLwRegFpNegOffset(Instr instr);
1086 static bool IsSwRegFpNegOffset(Instr instr);
1088 static Register GetRtReg(Instr instr);
1089 static Register GetRsReg(Instr instr);
1090 static Register GetRdReg(Instr instr);
1092 static uint32_t GetRt(Instr instr);
1093 static uint32_t GetRtField(Instr instr);
1094 static uint32_t GetRs(Instr instr);
1095 static uint32_t GetRsField(Instr instr);
1096 static uint32_t GetRd(Instr instr);
1097 static uint32_t GetRdField(Instr instr);
1098 static uint32_t GetSa(Instr instr);
1099 static uint32_t GetSaField(Instr instr);
1100 static uint32_t GetOpcodeField(Instr instr);
1101 static uint32_t GetFunction(Instr instr);
1102 static uint32_t GetFunctionField(Instr instr);
1103 static uint32_t GetImmediate16(Instr instr);
1104 static uint32_t GetLabelConst(Instr instr);
1106 static int32_t GetBranchOffset(Instr instr);
1107 static bool IsLw(Instr instr);
1108 static int16_t GetLwOffset(Instr instr);
1109 static Instr SetLwOffset(Instr instr, int16_t offset);
1111 static bool IsSw(Instr instr);
1112 static Instr SetSwOffset(Instr instr, int16_t offset);
1113 static bool IsAddImmediate(Instr instr);
1114 static Instr SetAddImmediateOffset(Instr instr, int16_t offset);
1116 static bool IsAndImmediate(Instr instr);
1117 static bool IsEmittedConstant(Instr instr);
1119 void CheckTrampolinePool();
1121 // Allocate a constant pool of the correct size for the generated code.
1122 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
1124 // Generate the constant pool for the generated code.
1125 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1128 // Relocation for a type-recording IC has the AST id added to it. This
1129 // member variable is a way to pass the information from the call site to
1130 // the relocation info.
1131 TypeFeedbackId recorded_ast_id_;
1133 int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; }
1135 // Decode branch instruction at pos and return branch target pos.
1136 int target_at(int32_t pos);
1138 // Patch branch instruction at pos to branch to given branch target pos.
1139 void target_at_put(int32_t pos, int32_t target_pos);
1141 // Say if we need to relocate with this mode.
1142 bool MustUseReg(RelocInfo::Mode rmode);
1144 // Record reloc info for current pc_.
1145 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1147 // Block the emission of the trampoline pool before pc_offset.
1148 void BlockTrampolinePoolBefore(int pc_offset) {
1149 if (no_trampoline_pool_before_ < pc_offset)
1150 no_trampoline_pool_before_ = pc_offset;
1153 void StartBlockTrampolinePool() {
1154 trampoline_pool_blocked_nesting_++;
1157 void EndBlockTrampolinePool() {
1158 trampoline_pool_blocked_nesting_--;
1161 bool is_trampoline_pool_blocked() const {
1162 return trampoline_pool_blocked_nesting_ > 0;
1165 bool has_exception() const {
1166 return internal_trampoline_exception_;
1169 void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi);
1171 bool is_trampoline_emitted() const {
1172 return trampoline_emitted_;
1175 // Temporarily block automatic assembly buffer growth.
1176 void StartBlockGrowBuffer() {
1177 DCHECK(!block_buffer_growth_);
1178 block_buffer_growth_ = true;
1181 void EndBlockGrowBuffer() {
1182 DCHECK(block_buffer_growth_);
1183 block_buffer_growth_ = false;
1186 bool is_buffer_growth_blocked() const {
1187 return block_buffer_growth_;
1191 // Buffer size and constant pool distance are checked together at regular
1192 // intervals of kBufferCheckInterval emitted bytes.
1193 static const int kBufferCheckInterval = 1*KB/2;
1196 // The relocation writer's position is at least kGap bytes below the end of
1197 // the generated instructions. This is so that multi-instruction sequences do
1198 // not have to check for overflow. The same is true for writes of large
1199 // relocation info entries.
1200 static const int kGap = 32;
1203 // Repeated checking whether the trampoline pool should be emitted is rather
1204 // expensive. By default we only check again once a number of instructions
1205 // has been generated.
1206 static const int kCheckConstIntervalInst = 32;
1207 static const int kCheckConstInterval = kCheckConstIntervalInst * kInstrSize;
1209 int next_buffer_check_; // pc offset of next buffer check.
1211 // Emission of the trampoline pool may be blocked in some code sequences.
1212 int trampoline_pool_blocked_nesting_; // Block emission if this is not zero.
1213 int no_trampoline_pool_before_; // Block emission before this pc offset.
1215 // Keep track of the last emitted pool to guarantee a maximal distance.
1216 int last_trampoline_pool_end_; // pc offset of the end of the last pool.
1218 // Automatic growth of the assembly buffer may be blocked for some sequences.
1219 bool block_buffer_growth_; // Block growth when true.
1221 // Relocation information generation.
1222 // Each relocation is encoded as a variable size value.
1223 static const int kMaxRelocSize = RelocInfoWriter::kMaxSize;
1224 RelocInfoWriter reloc_info_writer;
1226 // The bound position, before this we cannot do instruction elimination.
1227 int last_bound_pos_;
1230 inline void CheckBuffer();
1232 inline void emit(Instr x);
1233 inline void CheckTrampolinePoolQuick();
1235 // Instruction generation.
1236 // We have 3 different kind of encoding layout on MIPS.
1237 // However due to many different types of objects encoded in the same fields
1238 // we have quite a few aliases for each mode.
1239 // Using the same structure to refer to Register and FPURegister would spare a
1240 // few aliases, but mixing both does not look clean to me.
1241 // Anyway we could surely implement this differently.
1243 void GenInstrRegister(Opcode opcode,
1248 SecondaryField func = NULLSF);
1250 void GenInstrRegister(Opcode opcode,
1255 SecondaryField func);
1257 void GenInstrRegister(Opcode opcode,
1262 SecondaryField func = NULLSF);
1264 void GenInstrRegister(Opcode opcode,
1269 SecondaryField func = NULLSF);
1271 void GenInstrRegister(Opcode opcode,
1276 SecondaryField func = NULLSF);
1278 void GenInstrRegister(Opcode opcode,
1281 FPUControlRegister fs,
1282 SecondaryField func = NULLSF);
1285 void GenInstrImmediate(Opcode opcode,
1289 void GenInstrImmediate(Opcode opcode,
1293 void GenInstrImmediate(Opcode opcode,
1299 void GenInstrJump(Opcode opcode,
1303 void LoadRegPlusOffsetToAt(const MemOperand& src);
1306 void print(Label* L);
1307 void bind_to(Label* L, int pos);
1308 void next(Label* L);
1310 // One trampoline consists of:
1311 // - space for trampoline slots,
1312 // - space for labels.
1314 // Space for trampoline slots is equal to slot_count * 2 * kInstrSize.
1315 // Space for trampoline slots preceeds space for labels. Each label is of one
1316 // instruction size, so total amount for labels is equal to
1317 // label_count * kInstrSize.
1323 free_slot_count_ = 0;
1326 Trampoline(int start, int slot_count) {
1329 free_slot_count_ = slot_count;
1330 end_ = start + slot_count * kTrampolineSlotsSize;
1339 int trampoline_slot = kInvalidSlotPos;
1340 if (free_slot_count_ <= 0) {
1341 // We have run out of space on trampolines.
1342 // Make sure we fail in debug mode, so we become aware of each case
1343 // when this happens.
1345 // Internal exception will be caught.
1347 trampoline_slot = next_slot_;
1349 next_slot_ += kTrampolineSlotsSize;
1351 return trampoline_slot;
1358 int free_slot_count_;
1361 int32_t get_trampoline_entry(int32_t pos);
1362 int unbound_labels_count_;
1363 // If trampoline is emitted, generated code is becoming large. As this is
1364 // already a slow case which can possibly break our code generation for the
1365 // extreme case, we use this information to trigger different mode of
1366 // branch instruction generation, where we use jump instructions rather
1367 // than regular branch instructions.
1368 bool trampoline_emitted_;
1369 static const int kTrampolineSlotsSize = 4 * kInstrSize;
1370 static const int kMaxBranchOffset = (1 << (18 - 1)) - 1;
1371 static const int kInvalidSlotPos = -1;
1373 Trampoline trampoline_;
1374 bool internal_trampoline_exception_;
1376 friend class RegExpMacroAssemblerMIPS;
1377 friend class RelocInfo;
1378 friend class CodePatcher;
1379 friend class BlockTrampolinePoolScope;
1381 PositionsRecorder positions_recorder_;
1382 friend class PositionsRecorder;
1383 friend class EnsureSpace;
1387 class EnsureSpace BASE_EMBEDDED {
1389 explicit EnsureSpace(Assembler* assembler) {
1390 assembler->CheckBuffer();
1394 } } // namespace v8::internal
1396 #endif // V8_ARM_ASSEMBLER_MIPS_H_