1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
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29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2012 the V8 project authors. All rights reserved.
36 #ifndef V8_MIPS_ASSEMBLER_MIPS_H_
37 #define V8_MIPS_ASSEMBLER_MIPS_H_
41 #include "src/assembler.h"
42 #include "src/mips/constants-mips.h"
43 #include "src/serialize.h"
50 // 1) We would prefer to use an enum, but enum values are assignment-
51 // compatible with int, which has caused code-generation bugs.
53 // 2) We would prefer to use a class instead of a struct but we don't like
54 // the register initialization to depend on the particular initialization
55 // order (which appears to be different on OS X, Linux, and Windows for the
56 // installed versions of C++ we tried). Using a struct permits C-style
57 // "initialization". Also, the Register objects cannot be const as this
58 // forces initialization stubs in MSVC, making us dependent on initialization
61 // 3) By not using an enum, we are possibly preventing the compiler from
62 // doing certain constant folds, which may significantly reduce the
63 // code generated for some assembly instructions (because they boil down
64 // to a few constants). If this is a problem, we could change the code
65 // such that we use an enum in optimized mode, and the struct in debug
66 // mode. This way we get the compile-time error checking in debug mode
67 // and best performance in optimized code.
70 // -----------------------------------------------------------------------------
71 // Implementation of Register and FPURegister.
75 static const int kNumRegisters = v8::internal::kNumRegisters;
76 static const int kMaxNumAllocatableRegisters = 14; // v0 through t6 and cp.
77 static const int kSizeInBytes = 4;
78 static const int kCpRegister = 23; // cp (s7) is the 23rd register.
80 #if defined(V8_TARGET_LITTLE_ENDIAN)
81 static const int kMantissaOffset = 0;
82 static const int kExponentOffset = 4;
83 #elif defined(V8_TARGET_BIG_ENDIAN)
84 static const int kMantissaOffset = 4;
85 static const int kExponentOffset = 0;
87 #error Unknown endianness
90 inline static int NumAllocatableRegisters();
92 static int ToAllocationIndex(Register reg) {
93 DCHECK((reg.code() - 2) < (kMaxNumAllocatableRegisters - 1) ||
94 reg.is(from_code(kCpRegister)));
95 return reg.is(from_code(kCpRegister)) ?
96 kMaxNumAllocatableRegisters - 1 : // Return last index for 'cp'.
97 reg.code() - 2; // zero_reg and 'at' are skipped.
100 static Register FromAllocationIndex(int index) {
101 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
102 return index == kMaxNumAllocatableRegisters - 1 ?
103 from_code(kCpRegister) : // Last index is always the 'cp' register.
104 from_code(index + 2); // zero_reg and 'at' are skipped.
107 static const char* AllocationIndexToString(int index) {
108 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
109 const char* const names[] = {
128 static Register from_code(int code) {
129 Register r = { code };
133 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
134 bool is(Register reg) const { return code_ == reg.code_; }
144 // Unfortunately we can't make this private in a struct.
148 #define REGISTER(N, C) \
149 const int kRegister_ ## N ## _Code = C; \
150 const Register N = { C }
152 REGISTER(no_reg, -1);
154 REGISTER(zero_reg, 0);
155 // at: Reserved for synthetic instructions.
157 // v0, v1: Used when returning multiple values from subroutines.
160 // a0 - a4: Used to pass non-FP parameters.
165 // t0 - t9: Can be used without reservation, act as temporary registers and are
166 // allowed to be destroyed by subroutines.
175 // s0 - s7: Subroutine register variables. Subroutines that write to these
176 // registers must restore their values before exiting so that the caller can
177 // expect the values to be preserved.
188 // k0, k1: Reserved for system calls and interrupt handlers.
193 // sp: Stack pointer.
195 // fp: Frame pointer.
197 // ra: Return address pointer.
203 int ToNumber(Register reg);
205 Register ToRegister(int num);
207 // Coprocessor register.
209 static const int kMaxNumRegisters = v8::internal::kNumFPURegisters;
211 // TODO(plind): Warning, inconsistent numbering here. kNumFPURegisters refers
212 // to number of 32-bit FPU regs, but kNumAllocatableRegisters refers to
213 // number of Double regs (64-bit regs, or FPU-reg-pairs).
215 // A few double registers are reserved: one as a scratch register and one to
218 // f30: scratch register.
219 static const int kNumReservedRegisters = 2;
220 static const int kMaxNumAllocatableRegisters = kMaxNumRegisters / 2 -
221 kNumReservedRegisters;
223 inline static int NumRegisters();
224 inline static int NumAllocatableRegisters();
225 inline static int ToAllocationIndex(FPURegister reg);
226 static const char* AllocationIndexToString(int index);
228 static FPURegister FromAllocationIndex(int index) {
229 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
230 return from_code(index * 2);
233 static FPURegister from_code(int code) {
234 FPURegister r = { code };
238 bool is_valid() const { return 0 <= code_ && code_ < kMaxNumRegisters ; }
239 bool is(FPURegister creg) const { return code_ == creg.code_; }
240 FPURegister low() const {
241 // Find low reg of a Double-reg pair, which is the reg itself.
242 DCHECK(code_ % 2 == 0); // Specified Double reg must be even.
245 DCHECK(reg.is_valid());
248 FPURegister high() const {
249 // Find high reg of a Doubel-reg pair, which is reg + 1.
250 DCHECK(code_ % 2 == 0); // Specified Double reg must be even.
252 reg.code_ = code_ + 1;
253 DCHECK(reg.is_valid());
265 void setcode(int f) {
269 // Unfortunately we can't make this private in a struct.
273 // V8 now supports the O32 ABI, and the FPU Registers are organized as 32
274 // 32-bit registers, f0 through f31. When used as 'double' they are used
275 // in pairs, starting with the even numbered register. So a double operation
276 // on f0 really uses f0 and f1.
277 // (Modern mips hardware also supports 32 64-bit registers, via setting
278 // (priviledged) Status Register FR bit to 1. This is used by the N32 ABI,
279 // but it is not in common use. Someday we will want to support this in v8.)
281 // For O32 ABI, Floats and Doubles refer to same set of 32 32-bit registers.
282 typedef FPURegister DoubleRegister;
283 typedef FPURegister FloatRegister;
285 const FPURegister no_freg = { -1 };
287 const FPURegister f0 = { 0 }; // Return value in hard float mode.
288 const FPURegister f1 = { 1 };
289 const FPURegister f2 = { 2 };
290 const FPURegister f3 = { 3 };
291 const FPURegister f4 = { 4 };
292 const FPURegister f5 = { 5 };
293 const FPURegister f6 = { 6 };
294 const FPURegister f7 = { 7 };
295 const FPURegister f8 = { 8 };
296 const FPURegister f9 = { 9 };
297 const FPURegister f10 = { 10 };
298 const FPURegister f11 = { 11 };
299 const FPURegister f12 = { 12 }; // Arg 0 in hard float mode.
300 const FPURegister f13 = { 13 };
301 const FPURegister f14 = { 14 }; // Arg 1 in hard float mode.
302 const FPURegister f15 = { 15 };
303 const FPURegister f16 = { 16 };
304 const FPURegister f17 = { 17 };
305 const FPURegister f18 = { 18 };
306 const FPURegister f19 = { 19 };
307 const FPURegister f20 = { 20 };
308 const FPURegister f21 = { 21 };
309 const FPURegister f22 = { 22 };
310 const FPURegister f23 = { 23 };
311 const FPURegister f24 = { 24 };
312 const FPURegister f25 = { 25 };
313 const FPURegister f26 = { 26 };
314 const FPURegister f27 = { 27 };
315 const FPURegister f28 = { 28 };
316 const FPURegister f29 = { 29 };
317 const FPURegister f30 = { 30 };
318 const FPURegister f31 = { 31 };
321 // cp is assumed to be a callee saved register.
322 // Defined using #define instead of "static const Register&" because Clang
323 // complains otherwise when a compilation unit that includes this header
324 // doesn't use the variables.
325 #define kRootRegister s6
327 #define kLithiumScratchReg s3
328 #define kLithiumScratchReg2 s4
329 #define kLithiumScratchDouble f30
330 #define kDoubleRegZero f28
332 // FPU (coprocessor 1) control registers.
333 // Currently only FCSR (#31) is implemented.
334 struct FPUControlRegister {
335 bool is_valid() const { return code_ == kFCSRRegister; }
336 bool is(FPUControlRegister creg) const { return code_ == creg.code_; }
345 void setcode(int f) {
349 // Unfortunately we can't make this private in a struct.
353 const FPUControlRegister no_fpucreg = { kInvalidFPUControlRegister };
354 const FPUControlRegister FCSR = { kFCSRRegister };
357 // -----------------------------------------------------------------------------
358 // Machine instruction Operands.
360 // Class Operand represents a shifter operand in data processing instructions.
361 class Operand BASE_EMBEDDED {
364 INLINE(explicit Operand(int32_t immediate,
365 RelocInfo::Mode rmode = RelocInfo::NONE32));
366 INLINE(explicit Operand(const ExternalReference& f));
367 INLINE(explicit Operand(const char* s));
368 INLINE(explicit Operand(Object** opp));
369 INLINE(explicit Operand(Context** cpp));
370 explicit Operand(Handle<Object> handle);
371 INLINE(explicit Operand(Smi* value));
374 INLINE(explicit Operand(Register rm));
376 // Return true if this is a register operand.
377 INLINE(bool is_reg() const);
379 inline int32_t immediate() const {
384 Register rm() const { return rm_; }
388 int32_t imm32_; // Valid if rm_ == no_reg.
389 RelocInfo::Mode rmode_;
391 friend class Assembler;
392 friend class MacroAssembler;
396 // On MIPS we have only one adressing mode with base_reg + offset.
397 // Class MemOperand represents a memory operand in load and store instructions.
398 class MemOperand : public Operand {
400 // Immediate value attached to offset.
402 offset_minus_one = -1,
406 explicit MemOperand(Register rn, int32_t offset = 0);
407 explicit MemOperand(Register rn, int32_t unit, int32_t multiplier,
408 OffsetAddend offset_addend = offset_zero);
409 int32_t offset() const { return offset_; }
411 bool OffsetIsInt16Encodable() const {
412 return is_int16(offset_);
418 friend class Assembler;
422 class Assembler : public AssemblerBase {
424 // Create an assembler. Instructions and relocation information are emitted
425 // into a buffer, with the instructions starting from the beginning and the
426 // relocation information starting from the end of the buffer. See CodeDesc
427 // for a detailed comment on the layout (globals.h).
429 // If the provided buffer is NULL, the assembler allocates and grows its own
430 // buffer, and buffer_size determines the initial buffer size. The buffer is
431 // owned by the assembler and deallocated upon destruction of the assembler.
433 // If the provided buffer is not NULL, the assembler uses the provided buffer
434 // for code generation and assumes its size to be buffer_size. If the buffer
435 // is too small, a fatal error occurs. No deallocation of the buffer is done
436 // upon destruction of the assembler.
437 Assembler(Isolate* isolate, void* buffer, int buffer_size);
438 virtual ~Assembler() { }
440 // GetCode emits any pending (non-emitted) code and fills the descriptor
441 // desc. GetCode() is idempotent; it returns the same result if no other
442 // Assembler functions are invoked in between GetCode() calls.
443 void GetCode(CodeDesc* desc);
445 // Label operations & relative jumps (PPUM Appendix D).
447 // Takes a branch opcode (cc) and a label (L) and generates
448 // either a backward branch or a forward branch and links it
449 // to the label fixup chain. Usage:
451 // Label L; // unbound label
452 // j(cc, &L); // forward branch to unbound label
453 // bind(&L); // bind label to the current pc
454 // j(cc, &L); // backward branch to bound label
455 // bind(&L); // illegal: a label may be bound only once
457 // Note: The same Label can be used for forward and backward branches
458 // but it may be bound only once.
459 void bind(Label* L); // Binds an unbound label L to current code position.
460 // Determines if Label is bound and near enough so that branch instruction
461 // can be used to reach it, instead of jump instruction.
462 bool is_near(Label* L);
464 // Returns the branch offset to the given label from the current code
465 // position. Links the label to the current position if it is still unbound.
466 // Manages the jump elimination optimization if the second parameter is true.
467 int32_t branch_offset(Label* L, bool jump_elimination_allowed);
468 int32_t shifted_branch_offset(Label* L, bool jump_elimination_allowed) {
469 int32_t o = branch_offset(L, jump_elimination_allowed);
470 DCHECK((o & 3) == 0); // Assert the offset is aligned.
473 uint32_t jump_address(Label* L);
475 // Puts a labels target address at the given position.
476 // The high 8 bits are set to zero.
477 void label_at_put(Label* L, int at_offset);
479 // Read/Modify the code target address in the branch/call instruction at pc.
480 static Address target_address_at(Address pc);
481 static void set_target_address_at(Address pc,
483 ICacheFlushMode icache_flush_mode =
484 FLUSH_ICACHE_IF_NEEDED);
485 // On MIPS there is no Constant Pool so we skip that parameter.
486 INLINE(static Address target_address_at(Address pc,
487 ConstantPoolArray* constant_pool)) {
488 return target_address_at(pc);
490 INLINE(static void set_target_address_at(Address pc,
491 ConstantPoolArray* constant_pool,
493 ICacheFlushMode icache_flush_mode =
494 FLUSH_ICACHE_IF_NEEDED)) {
495 set_target_address_at(pc, target, icache_flush_mode);
497 INLINE(static Address target_address_at(Address pc, Code* code)) {
498 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
499 return target_address_at(pc, constant_pool);
501 INLINE(static void set_target_address_at(Address pc,
504 ICacheFlushMode icache_flush_mode =
505 FLUSH_ICACHE_IF_NEEDED)) {
506 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
507 set_target_address_at(pc, constant_pool, target, icache_flush_mode);
510 // Return the code target address at a call site from the return address
511 // of that call in the instruction stream.
512 inline static Address target_address_from_return_address(Address pc);
514 // Return the code target address of the patch debug break slot
515 inline static Address break_address_from_return_address(Address pc);
517 static void JumpLabelToJumpRegister(Address pc);
519 static void QuietNaN(HeapObject* nan);
521 // This sets the branch destination (which gets loaded at the call address).
522 // This is for calls and branches within generated code. The serializer
523 // has already deserialized the lui/ori instructions etc.
524 inline static void deserialization_set_special_target_at(
525 Address instruction_payload, Code* code, Address target) {
526 set_target_address_at(
527 instruction_payload - kInstructionsFor32BitConstant * kInstrSize,
532 // Size of an instruction.
533 static const int kInstrSize = sizeof(Instr);
535 // Difference between address of current opcode and target address offset.
536 static const int kBranchPCOffset = 4;
538 // Here we are patching the address in the LUI/ORI instruction pair.
539 // These values are used in the serialization process and must be zero for
540 // MIPS platform, as Code, Embedded Object or External-reference pointers
541 // are split across two consecutive instructions and don't exist separately
542 // in the code, so the serializer should not step forwards in memory after
543 // a target is resolved and written.
544 static const int kSpecialTargetSize = 0;
546 // Number of consecutive instructions used to store 32bit constant.
547 // Before jump-optimizations, this constant was used in
548 // RelocInfo::target_address_address() function to tell serializer address of
549 // the instruction that follows LUI/ORI instruction pair. Now, with new jump
550 // optimization, where jump-through-register instruction that usually
551 // follows LUI/ORI pair is substituted with J/JAL, this constant equals
552 // to 3 instructions (LUI+ORI+J/JAL/JR/JALR).
553 static const int kInstructionsFor32BitConstant = 3;
555 // Distance between the instruction referring to the address of the call
556 // target and the return address.
557 static const int kCallTargetAddressOffset = 4 * kInstrSize;
559 // Distance between start of patched return sequence and the emitted address
561 static const int kPatchReturnSequenceAddressOffset = 0;
563 // Distance between start of patched debug break slot and the emitted address
565 static const int kPatchDebugBreakSlotAddressOffset = 0 * kInstrSize;
567 // Difference between address of current opcode and value read from pc
569 static const int kPcLoadDelta = 4;
571 static const int kPatchDebugBreakSlotReturnOffset = 4 * kInstrSize;
573 // Number of instructions used for the JS return sequence. The constant is
574 // used by the debugger to patch the JS return sequence.
575 static const int kJSReturnSequenceInstructions = 7;
576 static const int kDebugBreakSlotInstructions = 4;
577 static const int kDebugBreakSlotLength =
578 kDebugBreakSlotInstructions * kInstrSize;
581 // ---------------------------------------------------------------------------
584 // Insert the smallest number of nop instructions
585 // possible to align the pc offset to a multiple
586 // of m. m must be a power of 2 (>= 4).
588 // Aligns code to something that's optimal for a jump target for the platform.
589 void CodeTargetAlign();
591 // Different nop operations are used by the code generator to detect certain
592 // states of the generated code.
593 enum NopMarkerTypes {
597 PROPERTY_ACCESS_INLINED,
598 PROPERTY_ACCESS_INLINED_CONTEXT,
599 PROPERTY_ACCESS_INLINED_CONTEXT_DONT_DELETE,
602 FIRST_IC_MARKER = PROPERTY_ACCESS_INLINED,
604 CODE_AGE_MARKER_NOP = 6,
605 CODE_AGE_SEQUENCE_NOP
608 // Type == 0 is the default non-marking nop. For mips this is a
609 // sll(zero_reg, zero_reg, 0). We use rt_reg == at for non-zero
610 // marking, to avoid conflict with ssnop and ehb instructions.
611 void nop(unsigned int type = 0) {
613 Register nop_rt_reg = (type == 0) ? zero_reg : at;
614 sll(zero_reg, nop_rt_reg, type, true);
618 // --------Branch-and-jump-instructions----------
619 // We don't use likely variant of instructions.
620 void b(int16_t offset);
621 void b(Label* L) { b(branch_offset(L, false)>>2); }
622 void bal(int16_t offset);
623 void bal(Label* L) { bal(branch_offset(L, false)>>2); }
625 void beq(Register rs, Register rt, int16_t offset);
626 void beq(Register rs, Register rt, Label* L) {
627 beq(rs, rt, branch_offset(L, false) >> 2);
629 void bgez(Register rs, int16_t offset);
630 void bgezal(Register rs, int16_t offset);
631 void bgtz(Register rs, int16_t offset);
632 void blez(Register rs, int16_t offset);
633 void bltz(Register rs, int16_t offset);
634 void bltzal(Register rs, int16_t offset);
635 void bne(Register rs, Register rt, int16_t offset);
636 void bne(Register rs, Register rt, Label* L) {
637 bne(rs, rt, branch_offset(L, false)>>2);
640 // Never use the int16_t b(l)cond version with a branch offset
641 // instead of using the Label* version.
643 // Jump targets must be in the current 256 MB-aligned region. i.e. 28 bits.
644 void j(int32_t target);
645 void jal(int32_t target);
646 void jalr(Register rs, Register rd = ra);
647 void jr(Register target);
648 void j_or_jr(int32_t target, Register rs);
649 void jal_or_jalr(int32_t target, Register rs);
652 // -------Data-processing-instructions---------
655 void addu(Register rd, Register rs, Register rt);
656 void subu(Register rd, Register rs, Register rt);
657 void mult(Register rs, Register rt);
658 void multu(Register rs, Register rt);
659 void div(Register rs, Register rt);
660 void divu(Register rs, Register rt);
661 void mul(Register rd, Register rs, Register rt);
663 void addiu(Register rd, Register rs, int32_t j);
666 void and_(Register rd, Register rs, Register rt);
667 void or_(Register rd, Register rs, Register rt);
668 void xor_(Register rd, Register rs, Register rt);
669 void nor(Register rd, Register rs, Register rt);
671 void andi(Register rd, Register rs, int32_t j);
672 void ori(Register rd, Register rs, int32_t j);
673 void xori(Register rd, Register rs, int32_t j);
674 void lui(Register rd, int32_t j);
677 // Please note: sll(zero_reg, zero_reg, x) instructions are reserved as nop
678 // and may cause problems in normal code. coming_from_nop makes sure this
680 void sll(Register rd, Register rt, uint16_t sa, bool coming_from_nop = false);
681 void sllv(Register rd, Register rt, Register rs);
682 void srl(Register rd, Register rt, uint16_t sa);
683 void srlv(Register rd, Register rt, Register rs);
684 void sra(Register rt, Register rd, uint16_t sa);
685 void srav(Register rt, Register rd, Register rs);
686 void rotr(Register rd, Register rt, uint16_t sa);
687 void rotrv(Register rd, Register rt, Register rs);
690 // ------------Memory-instructions-------------
692 void lb(Register rd, const MemOperand& rs);
693 void lbu(Register rd, const MemOperand& rs);
694 void lh(Register rd, const MemOperand& rs);
695 void lhu(Register rd, const MemOperand& rs);
696 void lw(Register rd, const MemOperand& rs);
697 void lwl(Register rd, const MemOperand& rs);
698 void lwr(Register rd, const MemOperand& rs);
699 void sb(Register rd, const MemOperand& rs);
700 void sh(Register rd, const MemOperand& rs);
701 void sw(Register rd, const MemOperand& rs);
702 void swl(Register rd, const MemOperand& rs);
703 void swr(Register rd, const MemOperand& rs);
706 // ----------------Prefetch--------------------
708 void pref(int32_t hint, const MemOperand& rs);
711 // -------------Misc-instructions--------------
713 // Break / Trap instructions.
714 void break_(uint32_t code, bool break_as_stop = false);
715 void stop(const char* msg, uint32_t code = kMaxStopCode);
716 void tge(Register rs, Register rt, uint16_t code);
717 void tgeu(Register rs, Register rt, uint16_t code);
718 void tlt(Register rs, Register rt, uint16_t code);
719 void tltu(Register rs, Register rt, uint16_t code);
720 void teq(Register rs, Register rt, uint16_t code);
721 void tne(Register rs, Register rt, uint16_t code);
723 // Move from HI/LO register.
724 void mfhi(Register rd);
725 void mflo(Register rd);
728 void slt(Register rd, Register rs, Register rt);
729 void sltu(Register rd, Register rs, Register rt);
730 void slti(Register rd, Register rs, int32_t j);
731 void sltiu(Register rd, Register rs, int32_t j);
734 void movz(Register rd, Register rs, Register rt);
735 void movn(Register rd, Register rs, Register rt);
736 void movt(Register rd, Register rs, uint16_t cc = 0);
737 void movf(Register rd, Register rs, uint16_t cc = 0);
740 void clz(Register rd, Register rs);
741 void ins_(Register rt, Register rs, uint16_t pos, uint16_t size);
742 void ext_(Register rt, Register rs, uint16_t pos, uint16_t size);
744 // --------Coprocessor-instructions----------------
746 // Load, store, and move.
747 void lwc1(FPURegister fd, const MemOperand& src);
748 void ldc1(FPURegister fd, const MemOperand& src);
750 void swc1(FPURegister fs, const MemOperand& dst);
751 void sdc1(FPURegister fs, const MemOperand& dst);
753 void mtc1(Register rt, FPURegister fs);
754 void mfc1(Register rt, FPURegister fs);
756 void ctc1(Register rt, FPUControlRegister fs);
757 void cfc1(Register rt, FPUControlRegister fs);
760 void add_d(FPURegister fd, FPURegister fs, FPURegister ft);
761 void sub_d(FPURegister fd, FPURegister fs, FPURegister ft);
762 void mul_d(FPURegister fd, FPURegister fs, FPURegister ft);
763 void madd_d(FPURegister fd, FPURegister fr, FPURegister fs, FPURegister ft);
764 void div_d(FPURegister fd, FPURegister fs, FPURegister ft);
765 void abs_d(FPURegister fd, FPURegister fs);
766 void mov_d(FPURegister fd, FPURegister fs);
767 void neg_d(FPURegister fd, FPURegister fs);
768 void sqrt_d(FPURegister fd, FPURegister fs);
771 void cvt_w_s(FPURegister fd, FPURegister fs);
772 void cvt_w_d(FPURegister fd, FPURegister fs);
773 void trunc_w_s(FPURegister fd, FPURegister fs);
774 void trunc_w_d(FPURegister fd, FPURegister fs);
775 void round_w_s(FPURegister fd, FPURegister fs);
776 void round_w_d(FPURegister fd, FPURegister fs);
777 void floor_w_s(FPURegister fd, FPURegister fs);
778 void floor_w_d(FPURegister fd, FPURegister fs);
779 void ceil_w_s(FPURegister fd, FPURegister fs);
780 void ceil_w_d(FPURegister fd, FPURegister fs);
782 void cvt_l_s(FPURegister fd, FPURegister fs);
783 void cvt_l_d(FPURegister fd, FPURegister fs);
784 void trunc_l_s(FPURegister fd, FPURegister fs);
785 void trunc_l_d(FPURegister fd, FPURegister fs);
786 void round_l_s(FPURegister fd, FPURegister fs);
787 void round_l_d(FPURegister fd, FPURegister fs);
788 void floor_l_s(FPURegister fd, FPURegister fs);
789 void floor_l_d(FPURegister fd, FPURegister fs);
790 void ceil_l_s(FPURegister fd, FPURegister fs);
791 void ceil_l_d(FPURegister fd, FPURegister fs);
793 void cvt_s_w(FPURegister fd, FPURegister fs);
794 void cvt_s_l(FPURegister fd, FPURegister fs);
795 void cvt_s_d(FPURegister fd, FPURegister fs);
797 void cvt_d_w(FPURegister fd, FPURegister fs);
798 void cvt_d_l(FPURegister fd, FPURegister fs);
799 void cvt_d_s(FPURegister fd, FPURegister fs);
801 // Conditions and branches.
802 void c(FPUCondition cond, SecondaryField fmt,
803 FPURegister ft, FPURegister fs, uint16_t cc = 0);
805 void bc1f(int16_t offset, uint16_t cc = 0);
806 void bc1f(Label* L, uint16_t cc = 0) { bc1f(branch_offset(L, false)>>2, cc); }
807 void bc1t(int16_t offset, uint16_t cc = 0);
808 void bc1t(Label* L, uint16_t cc = 0) { bc1t(branch_offset(L, false)>>2, cc); }
809 void fcmp(FPURegister src1, const double src2, FPUCondition cond);
811 // Check the code size generated from label to here.
812 int SizeOfCodeGeneratedSince(Label* label) {
813 return pc_offset() - label->pos();
816 // Check the number of instructions generated from label to here.
817 int InstructionsGeneratedSince(Label* label) {
818 return SizeOfCodeGeneratedSince(label) / kInstrSize;
821 // Class for scoping postponing the trampoline pool generation.
822 class BlockTrampolinePoolScope {
824 explicit BlockTrampolinePoolScope(Assembler* assem) : assem_(assem) {
825 assem_->StartBlockTrampolinePool();
827 ~BlockTrampolinePoolScope() {
828 assem_->EndBlockTrampolinePool();
834 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockTrampolinePoolScope);
837 // Class for postponing the assembly buffer growth. Typically used for
838 // sequences of instructions that must be emitted as a unit, before
839 // buffer growth (and relocation) can occur.
840 // This blocking scope is not nestable.
841 class BlockGrowBufferScope {
843 explicit BlockGrowBufferScope(Assembler* assem) : assem_(assem) {
844 assem_->StartBlockGrowBuffer();
846 ~BlockGrowBufferScope() {
847 assem_->EndBlockGrowBuffer();
853 DISALLOW_IMPLICIT_CONSTRUCTORS(BlockGrowBufferScope);
858 // Mark address of the ExitJSFrame code.
859 void RecordJSReturn();
861 // Mark address of a debug break slot.
862 void RecordDebugBreakSlot();
864 // Record the AST id of the CallIC being compiled, so that it can be placed
865 // in the relocation information.
866 void SetRecordedAstId(TypeFeedbackId ast_id) {
867 DCHECK(recorded_ast_id_.IsNone());
868 recorded_ast_id_ = ast_id;
871 TypeFeedbackId RecordedAstId() {
872 DCHECK(!recorded_ast_id_.IsNone());
873 return recorded_ast_id_;
876 void ClearRecordedAstId() { recorded_ast_id_ = TypeFeedbackId::None(); }
878 // Record a comment relocation entry that can be used by a disassembler.
879 // Use --code-comments to enable.
880 void RecordComment(const char* msg);
882 static int RelocateInternalReference(byte* pc, intptr_t pc_delta);
884 // Writes a single byte or word of data in the code stream. Used for
885 // inline tables, e.g., jump-tables.
886 void db(uint8_t data);
887 void dd(uint32_t data);
889 // Emits the address of the code stub's first instruction.
890 void emit_code_stub_address(Code* stub);
892 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
894 // Postpone the generation of the trampoline pool for the specified number of
896 void BlockTrampolinePoolFor(int instructions);
898 // Check if there is less than kGap bytes available in the buffer.
899 // If this is the case, we need to grow the buffer before emitting
900 // an instruction or relocation information.
901 inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; }
903 // Get the number of bytes available in the buffer.
904 inline int available_space() const { return reloc_info_writer.pos() - pc_; }
906 // Read/patch instructions.
907 static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); }
908 static void instr_at_put(byte* pc, Instr instr) {
909 *reinterpret_cast<Instr*>(pc) = instr;
911 Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); }
912 void instr_at_put(int pos, Instr instr) {
913 *reinterpret_cast<Instr*>(buffer_ + pos) = instr;
916 // Check if an instruction is a branch of some kind.
917 static bool IsBranch(Instr instr);
918 static bool IsBeq(Instr instr);
919 static bool IsBne(Instr instr);
921 static bool IsJump(Instr instr);
922 static bool IsJ(Instr instr);
923 static bool IsLui(Instr instr);
924 static bool IsOri(Instr instr);
926 static bool IsJal(Instr instr);
927 static bool IsJr(Instr instr);
928 static bool IsJalr(Instr instr);
930 static bool IsNop(Instr instr, unsigned int type);
931 static bool IsPop(Instr instr);
932 static bool IsPush(Instr instr);
933 static bool IsLwRegFpOffset(Instr instr);
934 static bool IsSwRegFpOffset(Instr instr);
935 static bool IsLwRegFpNegOffset(Instr instr);
936 static bool IsSwRegFpNegOffset(Instr instr);
938 static Register GetRtReg(Instr instr);
939 static Register GetRsReg(Instr instr);
940 static Register GetRdReg(Instr instr);
942 static uint32_t GetRt(Instr instr);
943 static uint32_t GetRtField(Instr instr);
944 static uint32_t GetRs(Instr instr);
945 static uint32_t GetRsField(Instr instr);
946 static uint32_t GetRd(Instr instr);
947 static uint32_t GetRdField(Instr instr);
948 static uint32_t GetSa(Instr instr);
949 static uint32_t GetSaField(Instr instr);
950 static uint32_t GetOpcodeField(Instr instr);
951 static uint32_t GetFunction(Instr instr);
952 static uint32_t GetFunctionField(Instr instr);
953 static uint32_t GetImmediate16(Instr instr);
954 static uint32_t GetLabelConst(Instr instr);
956 static int32_t GetBranchOffset(Instr instr);
957 static bool IsLw(Instr instr);
958 static int16_t GetLwOffset(Instr instr);
959 static Instr SetLwOffset(Instr instr, int16_t offset);
961 static bool IsSw(Instr instr);
962 static Instr SetSwOffset(Instr instr, int16_t offset);
963 static bool IsAddImmediate(Instr instr);
964 static Instr SetAddImmediateOffset(Instr instr, int16_t offset);
966 static bool IsAndImmediate(Instr instr);
967 static bool IsEmittedConstant(Instr instr);
969 void CheckTrampolinePool();
971 // Allocate a constant pool of the correct size for the generated code.
972 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
974 // Generate the constant pool for the generated code.
975 void PopulateConstantPool(ConstantPoolArray* constant_pool);
978 // Relocation for a type-recording IC has the AST id added to it. This
979 // member variable is a way to pass the information from the call site to
980 // the relocation info.
981 TypeFeedbackId recorded_ast_id_;
983 int32_t buffer_space() const { return reloc_info_writer.pos() - pc_; }
985 // Decode branch instruction at pos and return branch target pos.
986 int target_at(int32_t pos);
988 // Patch branch instruction at pos to branch to given branch target pos.
989 void target_at_put(int32_t pos, int32_t target_pos);
991 // Say if we need to relocate with this mode.
992 bool MustUseReg(RelocInfo::Mode rmode);
994 // Record reloc info for current pc_.
995 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
997 // Block the emission of the trampoline pool before pc_offset.
998 void BlockTrampolinePoolBefore(int pc_offset) {
999 if (no_trampoline_pool_before_ < pc_offset)
1000 no_trampoline_pool_before_ = pc_offset;
1003 void StartBlockTrampolinePool() {
1004 trampoline_pool_blocked_nesting_++;
1007 void EndBlockTrampolinePool() {
1008 trampoline_pool_blocked_nesting_--;
1011 bool is_trampoline_pool_blocked() const {
1012 return trampoline_pool_blocked_nesting_ > 0;
1015 bool has_exception() const {
1016 return internal_trampoline_exception_;
1019 void DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi);
1021 bool is_trampoline_emitted() const {
1022 return trampoline_emitted_;
1025 // Temporarily block automatic assembly buffer growth.
1026 void StartBlockGrowBuffer() {
1027 DCHECK(!block_buffer_growth_);
1028 block_buffer_growth_ = true;
1031 void EndBlockGrowBuffer() {
1032 DCHECK(block_buffer_growth_);
1033 block_buffer_growth_ = false;
1036 bool is_buffer_growth_blocked() const {
1037 return block_buffer_growth_;
1041 // Buffer size and constant pool distance are checked together at regular
1042 // intervals of kBufferCheckInterval emitted bytes.
1043 static const int kBufferCheckInterval = 1*KB/2;
1046 // The relocation writer's position is at least kGap bytes below the end of
1047 // the generated instructions. This is so that multi-instruction sequences do
1048 // not have to check for overflow. The same is true for writes of large
1049 // relocation info entries.
1050 static const int kGap = 32;
1053 // Repeated checking whether the trampoline pool should be emitted is rather
1054 // expensive. By default we only check again once a number of instructions
1055 // has been generated.
1056 static const int kCheckConstIntervalInst = 32;
1057 static const int kCheckConstInterval = kCheckConstIntervalInst * kInstrSize;
1059 int next_buffer_check_; // pc offset of next buffer check.
1061 // Emission of the trampoline pool may be blocked in some code sequences.
1062 int trampoline_pool_blocked_nesting_; // Block emission if this is not zero.
1063 int no_trampoline_pool_before_; // Block emission before this pc offset.
1065 // Keep track of the last emitted pool to guarantee a maximal distance.
1066 int last_trampoline_pool_end_; // pc offset of the end of the last pool.
1068 // Automatic growth of the assembly buffer may be blocked for some sequences.
1069 bool block_buffer_growth_; // Block growth when true.
1071 // Relocation information generation.
1072 // Each relocation is encoded as a variable size value.
1073 static const int kMaxRelocSize = RelocInfoWriter::kMaxSize;
1074 RelocInfoWriter reloc_info_writer;
1076 // The bound position, before this we cannot do instruction elimination.
1077 int last_bound_pos_;
1080 inline void CheckBuffer();
1082 inline void emit(Instr x);
1083 inline void CheckTrampolinePoolQuick();
1085 // Instruction generation.
1086 // We have 3 different kind of encoding layout on MIPS.
1087 // However due to many different types of objects encoded in the same fields
1088 // we have quite a few aliases for each mode.
1089 // Using the same structure to refer to Register and FPURegister would spare a
1090 // few aliases, but mixing both does not look clean to me.
1091 // Anyway we could surely implement this differently.
1093 void GenInstrRegister(Opcode opcode,
1098 SecondaryField func = NULLSF);
1100 void GenInstrRegister(Opcode opcode,
1105 SecondaryField func);
1107 void GenInstrRegister(Opcode opcode,
1112 SecondaryField func = NULLSF);
1114 void GenInstrRegister(Opcode opcode,
1119 SecondaryField func = NULLSF);
1121 void GenInstrRegister(Opcode opcode,
1126 SecondaryField func = NULLSF);
1128 void GenInstrRegister(Opcode opcode,
1131 FPUControlRegister fs,
1132 SecondaryField func = NULLSF);
1135 void GenInstrImmediate(Opcode opcode,
1139 void GenInstrImmediate(Opcode opcode,
1143 void GenInstrImmediate(Opcode opcode,
1149 void GenInstrJump(Opcode opcode,
1153 void LoadRegPlusOffsetToAt(const MemOperand& src);
1156 void print(Label* L);
1157 void bind_to(Label* L, int pos);
1158 void next(Label* L);
1160 // One trampoline consists of:
1161 // - space for trampoline slots,
1162 // - space for labels.
1164 // Space for trampoline slots is equal to slot_count * 2 * kInstrSize.
1165 // Space for trampoline slots preceeds space for labels. Each label is of one
1166 // instruction size, so total amount for labels is equal to
1167 // label_count * kInstrSize.
1173 free_slot_count_ = 0;
1176 Trampoline(int start, int slot_count) {
1179 free_slot_count_ = slot_count;
1180 end_ = start + slot_count * kTrampolineSlotsSize;
1189 int trampoline_slot = kInvalidSlotPos;
1190 if (free_slot_count_ <= 0) {
1191 // We have run out of space on trampolines.
1192 // Make sure we fail in debug mode, so we become aware of each case
1193 // when this happens.
1195 // Internal exception will be caught.
1197 trampoline_slot = next_slot_;
1199 next_slot_ += kTrampolineSlotsSize;
1201 return trampoline_slot;
1208 int free_slot_count_;
1211 int32_t get_trampoline_entry(int32_t pos);
1212 int unbound_labels_count_;
1213 // If trampoline is emitted, generated code is becoming large. As this is
1214 // already a slow case which can possibly break our code generation for the
1215 // extreme case, we use this information to trigger different mode of
1216 // branch instruction generation, where we use jump instructions rather
1217 // than regular branch instructions.
1218 bool trampoline_emitted_;
1219 static const int kTrampolineSlotsSize = 4 * kInstrSize;
1220 static const int kMaxBranchOffset = (1 << (18 - 1)) - 1;
1221 static const int kInvalidSlotPos = -1;
1223 Trampoline trampoline_;
1224 bool internal_trampoline_exception_;
1226 friend class RegExpMacroAssemblerMIPS;
1227 friend class RelocInfo;
1228 friend class CodePatcher;
1229 friend class BlockTrampolinePoolScope;
1231 PositionsRecorder positions_recorder_;
1232 friend class PositionsRecorder;
1233 friend class EnsureSpace;
1237 class EnsureSpace BASE_EMBEDDED {
1239 explicit EnsureSpace(Assembler* assembler) {
1240 assembler->CheckBuffer();
1244 } } // namespace v8::internal
1246 #endif // V8_ARM_ASSEMBLER_MIPS_H_