1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the distribution.
15 // - Neither the name of Sun Microsystems or the names of contributors may
16 // be used to endorse or promote products derived from this software without
17 // specific prior written permission.
19 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
20 // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
26 // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
27 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
28 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2012 the V8 project authors. All rights reserved.
38 #if V8_TARGET_ARCH_MIPS
40 #include "src/base/cpu.h"
41 #include "src/mips/assembler-mips-inl.h"
42 #include "src/serialize.h"
47 // Get the CPU features enabled by the build. For cross compilation the
48 // preprocessor symbols CAN_USE_FPU_INSTRUCTIONS
49 // can be defined to enable FPU instructions when building the
51 static unsigned CpuFeaturesImpliedByCompiler() {
53 #ifdef CAN_USE_FPU_INSTRUCTIONS
55 #endif // def CAN_USE_FPU_INSTRUCTIONS
57 // If the compiler is allowed to use FPU then we can use FPU too in our code
58 // generation even when generating snapshots. This won't work for cross
60 #if defined(__mips__) && defined(__mips_hard_float) && __mips_hard_float != 0
68 const char* DoubleRegister::AllocationIndexToString(int index) {
69 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
70 const char* const names[] = {
90 void CpuFeatures::ProbeImpl(bool cross_compile) {
91 supported_ |= CpuFeaturesImpliedByCompiler();
93 // Only use statically determined features for cross compile (snapshot).
94 if (cross_compile) return;
96 // If the compiler is allowed to use fpu then we can use fpu too in our
99 // For the simulator build, use FPU.
100 supported_ |= 1u << FPU;
102 // Probe for additional features at runtime.
104 if (cpu.has_fpu()) supported_ |= 1u << FPU;
109 void CpuFeatures::PrintTarget() { }
110 void CpuFeatures::PrintFeatures() { }
113 int ToNumber(Register reg) {
114 DCHECK(reg.is_valid());
115 const int kNumbers[] = {
149 return kNumbers[reg.code()];
153 Register ToRegister(int num) {
154 DCHECK(num >= 0 && num < kNumRegisters);
155 const Register kRegisters[] = {
160 t0, t1, t2, t3, t4, t5, t6, t7,
161 s0, s1, s2, s3, s4, s5, s6, s7,
169 return kRegisters[num];
173 // -----------------------------------------------------------------------------
174 // Implementation of RelocInfo.
176 const int RelocInfo::kApplyMask = RelocInfo::kCodeTargetMask |
177 1 << RelocInfo::INTERNAL_REFERENCE;
180 bool RelocInfo::IsCodedSpecially() {
181 // The deserializer needs to know whether a pointer is specially coded. Being
182 // specially coded on MIPS means that it is a lui/ori instruction, and that is
183 // always the case inside code objects.
188 bool RelocInfo::IsInConstantPool() {
193 // Patch the code at the current address with the supplied instructions.
194 void RelocInfo::PatchCode(byte* instructions, int instruction_count) {
195 Instr* pc = reinterpret_cast<Instr*>(pc_);
196 Instr* instr = reinterpret_cast<Instr*>(instructions);
197 for (int i = 0; i < instruction_count; i++) {
198 *(pc + i) = *(instr + i);
201 // Indicate that code has changed.
202 CpuFeatures::FlushICache(pc_, instruction_count * Assembler::kInstrSize);
206 // Patch the code at the current PC with a call to the target address.
207 // Additional guard instructions can be added if required.
208 void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
209 // Patch the code at the current address with a call to the target.
210 UNIMPLEMENTED_MIPS();
214 // -----------------------------------------------------------------------------
215 // Implementation of Operand and MemOperand.
216 // See assembler-mips-inl.h for inlined constructors.
218 Operand::Operand(Handle<Object> handle) {
219 AllowDeferredHandleDereference using_raw_address;
221 // Verify all Objects referred by code are NOT in new space.
222 Object* obj = *handle;
223 if (obj->IsHeapObject()) {
224 DCHECK(!HeapObject::cast(obj)->GetHeap()->InNewSpace(obj));
225 imm32_ = reinterpret_cast<intptr_t>(handle.location());
226 rmode_ = RelocInfo::EMBEDDED_OBJECT;
228 // No relocation needed.
229 imm32_ = reinterpret_cast<intptr_t>(obj);
230 rmode_ = RelocInfo::NONE32;
235 MemOperand::MemOperand(Register rm, int32_t offset) : Operand(rm) {
240 MemOperand::MemOperand(Register rm, int32_t unit, int32_t multiplier,
241 OffsetAddend offset_addend) : Operand(rm) {
242 offset_ = unit * multiplier + offset_addend;
246 // -----------------------------------------------------------------------------
247 // Specific instructions, constants, and masks.
249 static const int kNegOffset = 0x00008000;
250 // addiu(sp, sp, 4) aka Pop() operation or part of Pop(r)
251 // operations as post-increment of sp.
252 const Instr kPopInstruction = ADDIU | (kRegister_sp_Code << kRsShift)
253 | (kRegister_sp_Code << kRtShift)
254 | (kPointerSize & kImm16Mask); // NOLINT
255 // addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp.
256 const Instr kPushInstruction = ADDIU | (kRegister_sp_Code << kRsShift)
257 | (kRegister_sp_Code << kRtShift)
258 | (-kPointerSize & kImm16Mask); // NOLINT
259 // sw(r, MemOperand(sp, 0))
260 const Instr kPushRegPattern = SW | (kRegister_sp_Code << kRsShift)
261 | (0 & kImm16Mask); // NOLINT
262 // lw(r, MemOperand(sp, 0))
263 const Instr kPopRegPattern = LW | (kRegister_sp_Code << kRsShift)
264 | (0 & kImm16Mask); // NOLINT
266 const Instr kLwRegFpOffsetPattern = LW | (kRegister_fp_Code << kRsShift)
267 | (0 & kImm16Mask); // NOLINT
269 const Instr kSwRegFpOffsetPattern = SW | (kRegister_fp_Code << kRsShift)
270 | (0 & kImm16Mask); // NOLINT
272 const Instr kLwRegFpNegOffsetPattern = LW | (kRegister_fp_Code << kRsShift)
273 | (kNegOffset & kImm16Mask); // NOLINT
275 const Instr kSwRegFpNegOffsetPattern = SW | (kRegister_fp_Code << kRsShift)
276 | (kNegOffset & kImm16Mask); // NOLINT
277 // A mask for the Rt register for push, pop, lw, sw instructions.
278 const Instr kRtMask = kRtFieldMask;
279 const Instr kLwSwInstrTypeMask = 0xffe00000;
280 const Instr kLwSwInstrArgumentMask = ~kLwSwInstrTypeMask;
281 const Instr kLwSwOffsetMask = kImm16Mask;
284 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
285 : AssemblerBase(isolate, buffer, buffer_size),
286 recorded_ast_id_(TypeFeedbackId::None()),
287 positions_recorder_(this) {
288 reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
290 last_trampoline_pool_end_ = 0;
291 no_trampoline_pool_before_ = 0;
292 trampoline_pool_blocked_nesting_ = 0;
293 // We leave space (16 * kTrampolineSlotsSize)
294 // for BlockTrampolinePoolScope buffer.
295 next_buffer_check_ = FLAG_force_long_branches
296 ? kMaxInt : kMaxBranchOffset - kTrampolineSlotsSize * 16;
297 internal_trampoline_exception_ = false;
300 trampoline_emitted_ = FLAG_force_long_branches;
301 unbound_labels_count_ = 0;
302 block_buffer_growth_ = false;
304 ClearRecordedAstId();
308 void Assembler::GetCode(CodeDesc* desc) {
309 DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap.
310 // Set up code descriptor.
311 desc->buffer = buffer_;
312 desc->buffer_size = buffer_size_;
313 desc->instr_size = pc_offset();
314 desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
319 void Assembler::Align(int m) {
320 DCHECK(m >= 4 && IsPowerOf2(m));
321 while ((pc_offset() & (m - 1)) != 0) {
327 void Assembler::CodeTargetAlign() {
328 // No advantage to aligning branch/call targets to more than
329 // single instruction, that I am aware of.
334 Register Assembler::GetRtReg(Instr instr) {
336 rt.code_ = (instr & kRtFieldMask) >> kRtShift;
341 Register Assembler::GetRsReg(Instr instr) {
343 rs.code_ = (instr & kRsFieldMask) >> kRsShift;
348 Register Assembler::GetRdReg(Instr instr) {
350 rd.code_ = (instr & kRdFieldMask) >> kRdShift;
355 uint32_t Assembler::GetRt(Instr instr) {
356 return (instr & kRtFieldMask) >> kRtShift;
360 uint32_t Assembler::GetRtField(Instr instr) {
361 return instr & kRtFieldMask;
365 uint32_t Assembler::GetRs(Instr instr) {
366 return (instr & kRsFieldMask) >> kRsShift;
370 uint32_t Assembler::GetRsField(Instr instr) {
371 return instr & kRsFieldMask;
375 uint32_t Assembler::GetRd(Instr instr) {
376 return (instr & kRdFieldMask) >> kRdShift;
380 uint32_t Assembler::GetRdField(Instr instr) {
381 return instr & kRdFieldMask;
385 uint32_t Assembler::GetSa(Instr instr) {
386 return (instr & kSaFieldMask) >> kSaShift;
390 uint32_t Assembler::GetSaField(Instr instr) {
391 return instr & kSaFieldMask;
395 uint32_t Assembler::GetOpcodeField(Instr instr) {
396 return instr & kOpcodeMask;
400 uint32_t Assembler::GetFunction(Instr instr) {
401 return (instr & kFunctionFieldMask) >> kFunctionShift;
405 uint32_t Assembler::GetFunctionField(Instr instr) {
406 return instr & kFunctionFieldMask;
410 uint32_t Assembler::GetImmediate16(Instr instr) {
411 return instr & kImm16Mask;
415 uint32_t Assembler::GetLabelConst(Instr instr) {
416 return instr & ~kImm16Mask;
420 bool Assembler::IsPop(Instr instr) {
421 return (instr & ~kRtMask) == kPopRegPattern;
425 bool Assembler::IsPush(Instr instr) {
426 return (instr & ~kRtMask) == kPushRegPattern;
430 bool Assembler::IsSwRegFpOffset(Instr instr) {
431 return ((instr & kLwSwInstrTypeMask) == kSwRegFpOffsetPattern);
435 bool Assembler::IsLwRegFpOffset(Instr instr) {
436 return ((instr & kLwSwInstrTypeMask) == kLwRegFpOffsetPattern);
440 bool Assembler::IsSwRegFpNegOffset(Instr instr) {
441 return ((instr & (kLwSwInstrTypeMask | kNegOffset)) ==
442 kSwRegFpNegOffsetPattern);
446 bool Assembler::IsLwRegFpNegOffset(Instr instr) {
447 return ((instr & (kLwSwInstrTypeMask | kNegOffset)) ==
448 kLwRegFpNegOffsetPattern);
452 // Labels refer to positions in the (to be) generated code.
453 // There are bound, linked, and unused labels.
455 // Bound labels refer to known positions in the already
456 // generated code. pos() is the position the label refers to.
458 // Linked labels refer to unknown positions in the code
459 // to be generated; pos() is the position of the last
460 // instruction using the label.
462 // The link chain is terminated by a value in the instruction of -1,
463 // which is an otherwise illegal value (branch -1 is inf loop).
464 // The instruction 16-bit offset field addresses 32-bit words, but in
465 // code is conv to an 18-bit value addressing bytes, hence the -4 value.
467 const int kEndOfChain = -4;
468 // Determines the end of the Jump chain (a subset of the label link chain).
469 const int kEndOfJumpChain = 0;
472 bool Assembler::IsBranch(Instr instr) {
473 uint32_t opcode = GetOpcodeField(instr);
474 uint32_t rt_field = GetRtField(instr);
475 uint32_t rs_field = GetRsField(instr);
476 // Checks if the instruction is a branch.
477 return opcode == BEQ ||
485 (opcode == REGIMM && (rt_field == BLTZ || rt_field == BGEZ ||
486 rt_field == BLTZAL || rt_field == BGEZAL)) ||
487 (opcode == COP1 && rs_field == BC1); // Coprocessor branch.
491 bool Assembler::IsEmittedConstant(Instr instr) {
492 uint32_t label_constant = GetLabelConst(instr);
493 return label_constant == 0; // Emitted label const in reg-exp engine.
497 bool Assembler::IsBeq(Instr instr) {
498 return GetOpcodeField(instr) == BEQ;
502 bool Assembler::IsBne(Instr instr) {
503 return GetOpcodeField(instr) == BNE;
507 bool Assembler::IsJump(Instr instr) {
508 uint32_t opcode = GetOpcodeField(instr);
509 uint32_t rt_field = GetRtField(instr);
510 uint32_t rd_field = GetRdField(instr);
511 uint32_t function_field = GetFunctionField(instr);
512 // Checks if the instruction is a jump.
513 return opcode == J || opcode == JAL ||
514 (opcode == SPECIAL && rt_field == 0 &&
515 ((function_field == JALR) || (rd_field == 0 && (function_field == JR))));
519 bool Assembler::IsJ(Instr instr) {
520 uint32_t opcode = GetOpcodeField(instr);
521 // Checks if the instruction is a jump.
526 bool Assembler::IsJal(Instr instr) {
527 return GetOpcodeField(instr) == JAL;
531 bool Assembler::IsJr(Instr instr) {
532 return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JR;
536 bool Assembler::IsJalr(Instr instr) {
537 return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JALR;
541 bool Assembler::IsLui(Instr instr) {
542 uint32_t opcode = GetOpcodeField(instr);
543 // Checks if the instruction is a load upper immediate.
544 return opcode == LUI;
548 bool Assembler::IsOri(Instr instr) {
549 uint32_t opcode = GetOpcodeField(instr);
550 // Checks if the instruction is a load upper immediate.
551 return opcode == ORI;
555 bool Assembler::IsNop(Instr instr, unsigned int type) {
556 // See Assembler::nop(type).
558 uint32_t opcode = GetOpcodeField(instr);
559 uint32_t function = GetFunctionField(instr);
560 uint32_t rt = GetRt(instr);
561 uint32_t rd = GetRd(instr);
562 uint32_t sa = GetSa(instr);
564 // Traditional mips nop == sll(zero_reg, zero_reg, 0)
565 // When marking non-zero type, use sll(zero_reg, at, type)
566 // to avoid use of mips ssnop and ehb special encodings
567 // of the sll instruction.
569 Register nop_rt_reg = (type == 0) ? zero_reg : at;
570 bool ret = (opcode == SPECIAL && function == SLL &&
571 rd == static_cast<uint32_t>(ToNumber(zero_reg)) &&
572 rt == static_cast<uint32_t>(ToNumber(nop_rt_reg)) &&
579 int32_t Assembler::GetBranchOffset(Instr instr) {
580 DCHECK(IsBranch(instr));
581 return (static_cast<int16_t>(instr & kImm16Mask)) << 2;
585 bool Assembler::IsLw(Instr instr) {
586 return ((instr & kOpcodeMask) == LW);
590 int16_t Assembler::GetLwOffset(Instr instr) {
592 return ((instr & kImm16Mask));
596 Instr Assembler::SetLwOffset(Instr instr, int16_t offset) {
599 // We actually create a new lw instruction based on the original one.
600 Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask)
601 | (offset & kImm16Mask);
607 bool Assembler::IsSw(Instr instr) {
608 return ((instr & kOpcodeMask) == SW);
612 Instr Assembler::SetSwOffset(Instr instr, int16_t offset) {
614 return ((instr & ~kImm16Mask) | (offset & kImm16Mask));
618 bool Assembler::IsAddImmediate(Instr instr) {
619 return ((instr & kOpcodeMask) == ADDIU);
623 Instr Assembler::SetAddImmediateOffset(Instr instr, int16_t offset) {
624 DCHECK(IsAddImmediate(instr));
625 return ((instr & ~kImm16Mask) | (offset & kImm16Mask));
629 bool Assembler::IsAndImmediate(Instr instr) {
630 return GetOpcodeField(instr) == ANDI;
634 int Assembler::target_at(int32_t pos) {
635 Instr instr = instr_at(pos);
636 if ((instr & ~kImm16Mask) == 0) {
637 // Emitted label constant, not part of a branch.
641 int32_t imm18 =((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14;
642 return (imm18 + pos);
645 // Check we have a branch or jump instruction.
646 DCHECK(IsBranch(instr) || IsJ(instr) || IsLui(instr));
647 // Do NOT change this to <<2. We rely on arithmetic shifts here, assuming
648 // the compiler uses arithmectic shifts for signed integers.
649 if (IsBranch(instr)) {
650 int32_t imm18 = ((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14;
652 if (imm18 == kEndOfChain) {
653 // EndOfChain sentinel is returned directly, not relative to pc or pos.
656 return pos + kBranchPCOffset + imm18;
658 } else if (IsLui(instr)) {
659 Instr instr_lui = instr_at(pos + 0 * Assembler::kInstrSize);
660 Instr instr_ori = instr_at(pos + 1 * Assembler::kInstrSize);
661 DCHECK(IsOri(instr_ori));
662 int32_t imm = (instr_lui & static_cast<int32_t>(kImm16Mask)) << kLuiShift;
663 imm |= (instr_ori & static_cast<int32_t>(kImm16Mask));
665 if (imm == kEndOfJumpChain) {
666 // EndOfChain sentinel is returned directly, not relative to pc or pos.
669 uint32_t instr_address = reinterpret_cast<int32_t>(buffer_ + pos);
670 int32_t delta = instr_address - imm;
675 int32_t imm28 = (instr & static_cast<int32_t>(kImm26Mask)) << 2;
676 if (imm28 == kEndOfJumpChain) {
677 // EndOfChain sentinel is returned directly, not relative to pc or pos.
680 uint32_t instr_address = reinterpret_cast<int32_t>(buffer_ + pos);
681 instr_address &= kImm28Mask;
682 int32_t delta = instr_address - imm28;
690 void Assembler::target_at_put(int32_t pos, int32_t target_pos) {
691 Instr instr = instr_at(pos);
692 if ((instr & ~kImm16Mask) == 0) {
693 DCHECK(target_pos == kEndOfChain || target_pos >= 0);
694 // Emitted label constant, not part of a branch.
695 // Make label relative to Code* of generated Code object.
696 instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag));
700 DCHECK(IsBranch(instr) || IsJ(instr) || IsLui(instr));
701 if (IsBranch(instr)) {
702 int32_t imm18 = target_pos - (pos + kBranchPCOffset);
703 DCHECK((imm18 & 3) == 0);
705 instr &= ~kImm16Mask;
706 int32_t imm16 = imm18 >> 2;
707 DCHECK(is_int16(imm16));
709 instr_at_put(pos, instr | (imm16 & kImm16Mask));
710 } else if (IsLui(instr)) {
711 Instr instr_lui = instr_at(pos + 0 * Assembler::kInstrSize);
712 Instr instr_ori = instr_at(pos + 1 * Assembler::kInstrSize);
713 DCHECK(IsOri(instr_ori));
714 uint32_t imm = reinterpret_cast<uint32_t>(buffer_) + target_pos;
715 DCHECK((imm & 3) == 0);
717 instr_lui &= ~kImm16Mask;
718 instr_ori &= ~kImm16Mask;
720 instr_at_put(pos + 0 * Assembler::kInstrSize,
721 instr_lui | ((imm & kHiMask) >> kLuiShift));
722 instr_at_put(pos + 1 * Assembler::kInstrSize,
723 instr_ori | (imm & kImm16Mask));
725 uint32_t imm28 = reinterpret_cast<uint32_t>(buffer_) + target_pos;
727 DCHECK((imm28 & 3) == 0);
729 instr &= ~kImm26Mask;
730 uint32_t imm26 = imm28 >> 2;
731 DCHECK(is_uint26(imm26));
733 instr_at_put(pos, instr | (imm26 & kImm26Mask));
738 void Assembler::print(Label* L) {
739 if (L->is_unused()) {
740 PrintF("unused label\n");
741 } else if (L->is_bound()) {
742 PrintF("bound label to %d\n", L->pos());
743 } else if (L->is_linked()) {
745 PrintF("unbound label");
746 while (l.is_linked()) {
747 PrintF("@ %d ", l.pos());
748 Instr instr = instr_at(l.pos());
749 if ((instr & ~kImm16Mask) == 0) {
752 PrintF("%d\n", instr);
757 PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
762 void Assembler::bind_to(Label* L, int pos) {
763 DCHECK(0 <= pos && pos <= pc_offset()); // Must have valid binding position.
764 int32_t trampoline_pos = kInvalidSlotPos;
765 if (L->is_linked() && !trampoline_emitted_) {
766 unbound_labels_count_--;
767 next_buffer_check_ += kTrampolineSlotsSize;
770 while (L->is_linked()) {
771 int32_t fixup_pos = L->pos();
772 int32_t dist = pos - fixup_pos;
773 next(L); // Call next before overwriting link with target at fixup_pos.
774 Instr instr = instr_at(fixup_pos);
775 if (IsBranch(instr)) {
776 if (dist > kMaxBranchOffset) {
777 if (trampoline_pos == kInvalidSlotPos) {
778 trampoline_pos = get_trampoline_entry(fixup_pos);
779 CHECK(trampoline_pos != kInvalidSlotPos);
781 DCHECK((trampoline_pos - fixup_pos) <= kMaxBranchOffset);
782 target_at_put(fixup_pos, trampoline_pos);
783 fixup_pos = trampoline_pos;
784 dist = pos - fixup_pos;
786 target_at_put(fixup_pos, pos);
788 DCHECK(IsJ(instr) || IsLui(instr) || IsEmittedConstant(instr));
789 target_at_put(fixup_pos, pos);
794 // Keep track of the last bound label so we don't eliminate any instructions
795 // before a bound label.
796 if (pos > last_bound_pos_)
797 last_bound_pos_ = pos;
801 void Assembler::bind(Label* L) {
802 DCHECK(!L->is_bound()); // Label can only be bound once.
803 bind_to(L, pc_offset());
807 void Assembler::next(Label* L) {
808 DCHECK(L->is_linked());
809 int link = target_at(L->pos());
810 if (link == kEndOfChain) {
819 bool Assembler::is_near(Label* L) {
821 return ((pc_offset() - L->pos()) < kMaxBranchOffset - 4 * kInstrSize);
827 // We have to use a temporary register for things that can be relocated even
828 // if they can be encoded in the MIPS's 16 bits of immediate-offset instruction
829 // space. There is no guarantee that the relocated location can be similarly
831 bool Assembler::MustUseReg(RelocInfo::Mode rmode) {
832 return !RelocInfo::IsNone(rmode);
835 void Assembler::GenInstrRegister(Opcode opcode,
840 SecondaryField func) {
841 DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa));
842 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
843 | (rd.code() << kRdShift) | (sa << kSaShift) | func;
848 void Assembler::GenInstrRegister(Opcode opcode,
853 SecondaryField func) {
854 DCHECK(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb));
855 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
856 | (msb << kRdShift) | (lsb << kSaShift) | func;
861 void Assembler::GenInstrRegister(Opcode opcode,
866 SecondaryField func) {
867 DCHECK(fd.is_valid() && fs.is_valid() && ft.is_valid());
868 Instr instr = opcode | fmt | (ft.code() << kFtShift) | (fs.code() << kFsShift)
869 | (fd.code() << kFdShift) | func;
874 void Assembler::GenInstrRegister(Opcode opcode,
879 SecondaryField func) {
880 DCHECK(fd.is_valid() && fr.is_valid() && fs.is_valid() && ft.is_valid());
881 Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift)
882 | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
887 void Assembler::GenInstrRegister(Opcode opcode,
892 SecondaryField func) {
893 DCHECK(fd.is_valid() && fs.is_valid() && rt.is_valid());
894 Instr instr = opcode | fmt | (rt.code() << kRtShift)
895 | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func;
900 void Assembler::GenInstrRegister(Opcode opcode,
903 FPUControlRegister fs,
904 SecondaryField func) {
905 DCHECK(fs.is_valid() && rt.is_valid());
907 opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func;
912 // Instructions with immediate value.
913 // Registers are in the order of the instruction encoding, from left to right.
914 void Assembler::GenInstrImmediate(Opcode opcode,
918 DCHECK(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j)));
919 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift)
925 void Assembler::GenInstrImmediate(Opcode opcode,
929 DCHECK(rs.is_valid() && (is_int16(j) || is_uint16(j)));
930 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask);
935 void Assembler::GenInstrImmediate(Opcode opcode,
939 DCHECK(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j)));
940 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift)
946 void Assembler::GenInstrJump(Opcode opcode,
948 BlockTrampolinePoolScope block_trampoline_pool(this);
949 DCHECK(is_uint26(address));
950 Instr instr = opcode | address;
952 BlockTrampolinePoolFor(1); // For associated delay slot.
956 // Returns the next free trampoline entry.
957 int32_t Assembler::get_trampoline_entry(int32_t pos) {
958 int32_t trampoline_entry = kInvalidSlotPos;
960 if (!internal_trampoline_exception_) {
961 if (trampoline_.start() > pos) {
962 trampoline_entry = trampoline_.take_slot();
965 if (kInvalidSlotPos == trampoline_entry) {
966 internal_trampoline_exception_ = true;
969 return trampoline_entry;
973 uint32_t Assembler::jump_address(Label* L) {
977 target_pos = L->pos();
979 if (L->is_linked()) {
980 target_pos = L->pos(); // L's link.
981 L->link_to(pc_offset());
983 L->link_to(pc_offset());
984 return kEndOfJumpChain;
988 uint32_t imm = reinterpret_cast<uint32_t>(buffer_) + target_pos;
989 DCHECK((imm & 3) == 0);
995 int32_t Assembler::branch_offset(Label* L, bool jump_elimination_allowed) {
999 target_pos = L->pos();
1001 if (L->is_linked()) {
1002 target_pos = L->pos();
1003 L->link_to(pc_offset());
1005 L->link_to(pc_offset());
1006 if (!trampoline_emitted_) {
1007 unbound_labels_count_++;
1008 next_buffer_check_ -= kTrampolineSlotsSize;
1014 int32_t offset = target_pos - (pc_offset() + kBranchPCOffset);
1015 DCHECK((offset & 3) == 0);
1016 DCHECK(is_int16(offset >> 2));
1022 void Assembler::label_at_put(Label* L, int at_offset) {
1024 if (L->is_bound()) {
1025 target_pos = L->pos();
1026 instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag));
1028 if (L->is_linked()) {
1029 target_pos = L->pos(); // L's link.
1030 int32_t imm18 = target_pos - at_offset;
1031 DCHECK((imm18 & 3) == 0);
1032 int32_t imm16 = imm18 >> 2;
1033 DCHECK(is_int16(imm16));
1034 instr_at_put(at_offset, (imm16 & kImm16Mask));
1036 target_pos = kEndOfChain;
1037 instr_at_put(at_offset, 0);
1038 if (!trampoline_emitted_) {
1039 unbound_labels_count_++;
1040 next_buffer_check_ -= kTrampolineSlotsSize;
1043 L->link_to(at_offset);
1048 //------- Branch and jump instructions --------
1050 void Assembler::b(int16_t offset) {
1051 beq(zero_reg, zero_reg, offset);
1055 void Assembler::bal(int16_t offset) {
1056 positions_recorder()->WriteRecordedPositions();
1057 bgezal(zero_reg, offset);
1061 void Assembler::beq(Register rs, Register rt, int16_t offset) {
1062 BlockTrampolinePoolScope block_trampoline_pool(this);
1063 GenInstrImmediate(BEQ, rs, rt, offset);
1064 BlockTrampolinePoolFor(1); // For associated delay slot.
1068 void Assembler::bgez(Register rs, int16_t offset) {
1069 BlockTrampolinePoolScope block_trampoline_pool(this);
1070 GenInstrImmediate(REGIMM, rs, BGEZ, offset);
1071 BlockTrampolinePoolFor(1); // For associated delay slot.
1075 void Assembler::bgezal(Register rs, int16_t offset) {
1076 BlockTrampolinePoolScope block_trampoline_pool(this);
1077 positions_recorder()->WriteRecordedPositions();
1078 GenInstrImmediate(REGIMM, rs, BGEZAL, offset);
1079 BlockTrampolinePoolFor(1); // For associated delay slot.
1083 void Assembler::bgtz(Register rs, int16_t offset) {
1084 BlockTrampolinePoolScope block_trampoline_pool(this);
1085 GenInstrImmediate(BGTZ, rs, zero_reg, offset);
1086 BlockTrampolinePoolFor(1); // For associated delay slot.
1090 void Assembler::blez(Register rs, int16_t offset) {
1091 BlockTrampolinePoolScope block_trampoline_pool(this);
1092 GenInstrImmediate(BLEZ, rs, zero_reg, offset);
1093 BlockTrampolinePoolFor(1); // For associated delay slot.
1097 void Assembler::bltz(Register rs, int16_t offset) {
1098 BlockTrampolinePoolScope block_trampoline_pool(this);
1099 GenInstrImmediate(REGIMM, rs, BLTZ, offset);
1100 BlockTrampolinePoolFor(1); // For associated delay slot.
1104 void Assembler::bltzal(Register rs, int16_t offset) {
1105 BlockTrampolinePoolScope block_trampoline_pool(this);
1106 positions_recorder()->WriteRecordedPositions();
1107 GenInstrImmediate(REGIMM, rs, BLTZAL, offset);
1108 BlockTrampolinePoolFor(1); // For associated delay slot.
1112 void Assembler::bne(Register rs, Register rt, int16_t offset) {
1113 BlockTrampolinePoolScope block_trampoline_pool(this);
1114 GenInstrImmediate(BNE, rs, rt, offset);
1115 BlockTrampolinePoolFor(1); // For associated delay slot.
1119 void Assembler::j(int32_t target) {
1121 // Get pc of delay slot.
1122 uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize);
1123 bool in_range = (ipc ^ static_cast<uint32_t>(target) >>
1124 (kImm26Bits + kImmFieldShift)) == 0;
1125 DCHECK(in_range && ((target & 3) == 0));
1127 GenInstrJump(J, target >> 2);
1131 void Assembler::jr(Register rs) {
1132 BlockTrampolinePoolScope block_trampoline_pool(this);
1134 positions_recorder()->WriteRecordedPositions();
1136 GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR);
1137 BlockTrampolinePoolFor(1); // For associated delay slot.
1141 void Assembler::jal(int32_t target) {
1143 // Get pc of delay slot.
1144 uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize);
1145 bool in_range = (ipc ^ static_cast<uint32_t>(target) >>
1146 (kImm26Bits + kImmFieldShift)) == 0;
1147 DCHECK(in_range && ((target & 3) == 0));
1149 positions_recorder()->WriteRecordedPositions();
1150 GenInstrJump(JAL, target >> 2);
1154 void Assembler::jalr(Register rs, Register rd) {
1155 BlockTrampolinePoolScope block_trampoline_pool(this);
1156 positions_recorder()->WriteRecordedPositions();
1157 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR);
1158 BlockTrampolinePoolFor(1); // For associated delay slot.
1162 void Assembler::j_or_jr(int32_t target, Register rs) {
1163 // Get pc of delay slot.
1164 uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize);
1165 bool in_range = (ipc ^ static_cast<uint32_t>(target) >>
1166 (kImm26Bits + kImmFieldShift)) == 0;
1175 void Assembler::jal_or_jalr(int32_t target, Register rs) {
1176 // Get pc of delay slot.
1177 uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize);
1178 bool in_range = (ipc ^ static_cast<uint32_t>(target) >>
1179 (kImm26Bits+kImmFieldShift)) == 0;
1188 // -------Data-processing-instructions---------
1192 void Assembler::addu(Register rd, Register rs, Register rt) {
1193 GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU);
1197 void Assembler::addiu(Register rd, Register rs, int32_t j) {
1198 GenInstrImmediate(ADDIU, rs, rd, j);
1202 void Assembler::subu(Register rd, Register rs, Register rt) {
1203 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU);
1207 void Assembler::mul(Register rd, Register rs, Register rt) {
1208 GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL);
1212 void Assembler::mult(Register rs, Register rt) {
1213 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULT);
1217 void Assembler::multu(Register rs, Register rt) {
1218 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU);
1222 void Assembler::div(Register rs, Register rt) {
1223 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIV);
1227 void Assembler::divu(Register rs, Register rt) {
1228 GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU);
1234 void Assembler::and_(Register rd, Register rs, Register rt) {
1235 GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND);
1239 void Assembler::andi(Register rt, Register rs, int32_t j) {
1240 DCHECK(is_uint16(j));
1241 GenInstrImmediate(ANDI, rs, rt, j);
1245 void Assembler::or_(Register rd, Register rs, Register rt) {
1246 GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR);
1250 void Assembler::ori(Register rt, Register rs, int32_t j) {
1251 DCHECK(is_uint16(j));
1252 GenInstrImmediate(ORI, rs, rt, j);
1256 void Assembler::xor_(Register rd, Register rs, Register rt) {
1257 GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR);
1261 void Assembler::xori(Register rt, Register rs, int32_t j) {
1262 DCHECK(is_uint16(j));
1263 GenInstrImmediate(XORI, rs, rt, j);
1267 void Assembler::nor(Register rd, Register rs, Register rt) {
1268 GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR);
1273 void Assembler::sll(Register rd,
1276 bool coming_from_nop) {
1277 // Don't allow nop instructions in the form sll zero_reg, zero_reg to be
1278 // generated using the sll instruction. They must be generated using
1279 // nop(int/NopMarkerTypes) or MarkCode(int/NopMarkerTypes) pseudo
1281 DCHECK(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg)));
1282 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL);
1286 void Assembler::sllv(Register rd, Register rt, Register rs) {
1287 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV);
1291 void Assembler::srl(Register rd, Register rt, uint16_t sa) {
1292 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRL);
1296 void Assembler::srlv(Register rd, Register rt, Register rs) {
1297 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV);
1301 void Assembler::sra(Register rd, Register rt, uint16_t sa) {
1302 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRA);
1306 void Assembler::srav(Register rd, Register rt, Register rs) {
1307 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV);
1311 void Assembler::rotr(Register rd, Register rt, uint16_t sa) {
1312 // Should be called via MacroAssembler::Ror.
1313 DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa));
1314 DCHECK(kArchVariant == kMips32r2);
1315 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift)
1316 | (rd.code() << kRdShift) | (sa << kSaShift) | SRL;
1321 void Assembler::rotrv(Register rd, Register rt, Register rs) {
1322 // Should be called via MacroAssembler::Ror.
1323 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() );
1324 DCHECK(kArchVariant == kMips32r2);
1325 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift)
1326 | (rd.code() << kRdShift) | (1 << kSaShift) | SRLV;
1331 // ------------Memory-instructions-------------
1333 // Helper for base-reg + offset, when offset is larger than int16.
1334 void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) {
1335 DCHECK(!src.rm().is(at));
1336 lui(at, (src.offset_ >> kLuiShift) & kImm16Mask);
1337 ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset.
1338 addu(at, at, src.rm()); // Add base register.
1342 void Assembler::lb(Register rd, const MemOperand& rs) {
1343 if (is_int16(rs.offset_)) {
1344 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_);
1345 } else { // Offset > 16 bits, use multiple instructions to load.
1346 LoadRegPlusOffsetToAt(rs);
1347 GenInstrImmediate(LB, at, rd, 0); // Equiv to lb(rd, MemOperand(at, 0));
1352 void Assembler::lbu(Register rd, const MemOperand& rs) {
1353 if (is_int16(rs.offset_)) {
1354 GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_);
1355 } else { // Offset > 16 bits, use multiple instructions to load.
1356 LoadRegPlusOffsetToAt(rs);
1357 GenInstrImmediate(LBU, at, rd, 0); // Equiv to lbu(rd, MemOperand(at, 0));
1362 void Assembler::lh(Register rd, const MemOperand& rs) {
1363 if (is_int16(rs.offset_)) {
1364 GenInstrImmediate(LH, rs.rm(), rd, rs.offset_);
1365 } else { // Offset > 16 bits, use multiple instructions to load.
1366 LoadRegPlusOffsetToAt(rs);
1367 GenInstrImmediate(LH, at, rd, 0); // Equiv to lh(rd, MemOperand(at, 0));
1372 void Assembler::lhu(Register rd, const MemOperand& rs) {
1373 if (is_int16(rs.offset_)) {
1374 GenInstrImmediate(LHU, rs.rm(), rd, rs.offset_);
1375 } else { // Offset > 16 bits, use multiple instructions to load.
1376 LoadRegPlusOffsetToAt(rs);
1377 GenInstrImmediate(LHU, at, rd, 0); // Equiv to lhu(rd, MemOperand(at, 0));
1382 void Assembler::lw(Register rd, const MemOperand& rs) {
1383 if (is_int16(rs.offset_)) {
1384 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_);
1385 } else { // Offset > 16 bits, use multiple instructions to load.
1386 LoadRegPlusOffsetToAt(rs);
1387 GenInstrImmediate(LW, at, rd, 0); // Equiv to lw(rd, MemOperand(at, 0));
1392 void Assembler::lwl(Register rd, const MemOperand& rs) {
1393 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_);
1397 void Assembler::lwr(Register rd, const MemOperand& rs) {
1398 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_);
1402 void Assembler::sb(Register rd, const MemOperand& rs) {
1403 if (is_int16(rs.offset_)) {
1404 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_);
1405 } else { // Offset > 16 bits, use multiple instructions to store.
1406 LoadRegPlusOffsetToAt(rs);
1407 GenInstrImmediate(SB, at, rd, 0); // Equiv to sb(rd, MemOperand(at, 0));
1412 void Assembler::sh(Register rd, const MemOperand& rs) {
1413 if (is_int16(rs.offset_)) {
1414 GenInstrImmediate(SH, rs.rm(), rd, rs.offset_);
1415 } else { // Offset > 16 bits, use multiple instructions to store.
1416 LoadRegPlusOffsetToAt(rs);
1417 GenInstrImmediate(SH, at, rd, 0); // Equiv to sh(rd, MemOperand(at, 0));
1422 void Assembler::sw(Register rd, const MemOperand& rs) {
1423 if (is_int16(rs.offset_)) {
1424 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_);
1425 } else { // Offset > 16 bits, use multiple instructions to store.
1426 LoadRegPlusOffsetToAt(rs);
1427 GenInstrImmediate(SW, at, rd, 0); // Equiv to sw(rd, MemOperand(at, 0));
1432 void Assembler::swl(Register rd, const MemOperand& rs) {
1433 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_);
1437 void Assembler::swr(Register rd, const MemOperand& rs) {
1438 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_);
1442 void Assembler::lui(Register rd, int32_t j) {
1443 DCHECK(is_uint16(j));
1444 GenInstrImmediate(LUI, zero_reg, rd, j);
1448 // -------------Misc-instructions--------------
1450 // Break / Trap instructions.
1451 void Assembler::break_(uint32_t code, bool break_as_stop) {
1452 DCHECK((code & ~0xfffff) == 0);
1453 // We need to invalidate breaks that could be stops as well because the
1454 // simulator expects a char pointer after the stop instruction.
1455 // See constants-mips.h for explanation.
1456 DCHECK((break_as_stop &&
1457 code <= kMaxStopCode &&
1458 code > kMaxWatchpointCode) ||
1460 (code > kMaxStopCode ||
1461 code <= kMaxWatchpointCode)));
1462 Instr break_instr = SPECIAL | BREAK | (code << 6);
1467 void Assembler::stop(const char* msg, uint32_t code) {
1468 DCHECK(code > kMaxWatchpointCode);
1469 DCHECK(code <= kMaxStopCode);
1470 #if V8_HOST_ARCH_MIPS
1472 #else // V8_HOST_ARCH_MIPS
1473 BlockTrampolinePoolFor(2);
1474 // The Simulator will handle the stop instruction and get the message address.
1475 // On MIPS stop() is just a special kind of break_().
1477 emit(reinterpret_cast<Instr>(msg));
1482 void Assembler::tge(Register rs, Register rt, uint16_t code) {
1483 DCHECK(is_uint10(code));
1484 Instr instr = SPECIAL | TGE | rs.code() << kRsShift
1485 | rt.code() << kRtShift | code << 6;
1490 void Assembler::tgeu(Register rs, Register rt, uint16_t code) {
1491 DCHECK(is_uint10(code));
1492 Instr instr = SPECIAL | TGEU | rs.code() << kRsShift
1493 | rt.code() << kRtShift | code << 6;
1498 void Assembler::tlt(Register rs, Register rt, uint16_t code) {
1499 DCHECK(is_uint10(code));
1501 SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
1506 void Assembler::tltu(Register rs, Register rt, uint16_t code) {
1507 DCHECK(is_uint10(code));
1509 SPECIAL | TLTU | rs.code() << kRsShift
1510 | rt.code() << kRtShift | code << 6;
1515 void Assembler::teq(Register rs, Register rt, uint16_t code) {
1516 DCHECK(is_uint10(code));
1518 SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
1523 void Assembler::tne(Register rs, Register rt, uint16_t code) {
1524 DCHECK(is_uint10(code));
1526 SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6;
1531 // Move from HI/LO register.
1533 void Assembler::mfhi(Register rd) {
1534 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI);
1538 void Assembler::mflo(Register rd) {
1539 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO);
1543 // Set on less than instructions.
1544 void Assembler::slt(Register rd, Register rs, Register rt) {
1545 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT);
1549 void Assembler::sltu(Register rd, Register rs, Register rt) {
1550 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU);
1554 void Assembler::slti(Register rt, Register rs, int32_t j) {
1555 GenInstrImmediate(SLTI, rs, rt, j);
1559 void Assembler::sltiu(Register rt, Register rs, int32_t j) {
1560 GenInstrImmediate(SLTIU, rs, rt, j);
1564 // Conditional move.
1565 void Assembler::movz(Register rd, Register rs, Register rt) {
1566 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ);
1570 void Assembler::movn(Register rd, Register rs, Register rt) {
1571 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN);
1575 void Assembler::movt(Register rd, Register rs, uint16_t cc) {
1577 rt.code_ = (cc & 0x0007) << 2 | 1;
1578 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
1582 void Assembler::movf(Register rd, Register rs, uint16_t cc) {
1584 rt.code_ = (cc & 0x0007) << 2 | 0;
1585 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI);
1590 void Assembler::clz(Register rd, Register rs) {
1591 // Clz instr requires same GPR number in 'rd' and 'rt' fields.
1592 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ);
1596 void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) {
1597 // Should be called via MacroAssembler::Ins.
1598 // Ins instr has 'rt' field as dest, and two uint5: msb, lsb.
1599 DCHECK(kArchVariant == kMips32r2);
1600 GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS);
1604 void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) {
1605 // Should be called via MacroAssembler::Ext.
1606 // Ext instr has 'rt' field as dest, and two uint5: msb, lsb.
1607 DCHECK(kArchVariant == kMips32r2);
1608 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT);
1612 void Assembler::pref(int32_t hint, const MemOperand& rs) {
1613 DCHECK(kArchVariant != kLoongson);
1614 DCHECK(is_uint5(hint) && is_uint16(rs.offset_));
1615 Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift)
1621 // --------Coprocessor-instructions----------------
1623 // Load, store, move.
1624 void Assembler::lwc1(FPURegister fd, const MemOperand& src) {
1625 GenInstrImmediate(LWC1, src.rm(), fd, src.offset_);
1629 void Assembler::ldc1(FPURegister fd, const MemOperand& src) {
1630 // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
1631 // load to two 32-bit loads.
1632 GenInstrImmediate(LWC1, src.rm(), fd, src.offset_ +
1633 Register::kMantissaOffset);
1634 FPURegister nextfpreg;
1635 nextfpreg.setcode(fd.code() + 1);
1636 GenInstrImmediate(LWC1, src.rm(), nextfpreg, src.offset_ +
1637 Register::kExponentOffset);
1641 void Assembler::swc1(FPURegister fd, const MemOperand& src) {
1642 GenInstrImmediate(SWC1, src.rm(), fd, src.offset_);
1646 void Assembler::sdc1(FPURegister fd, const MemOperand& src) {
1647 // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
1648 // store to two 32-bit stores.
1649 GenInstrImmediate(SWC1, src.rm(), fd, src.offset_ +
1650 Register::kMantissaOffset);
1651 FPURegister nextfpreg;
1652 nextfpreg.setcode(fd.code() + 1);
1653 GenInstrImmediate(SWC1, src.rm(), nextfpreg, src.offset_ +
1654 Register::kExponentOffset);
1658 void Assembler::mtc1(Register rt, FPURegister fs) {
1659 GenInstrRegister(COP1, MTC1, rt, fs, f0);
1663 void Assembler::mfc1(Register rt, FPURegister fs) {
1664 GenInstrRegister(COP1, MFC1, rt, fs, f0);
1668 void Assembler::ctc1(Register rt, FPUControlRegister fs) {
1669 GenInstrRegister(COP1, CTC1, rt, fs);
1673 void Assembler::cfc1(Register rt, FPUControlRegister fs) {
1674 GenInstrRegister(COP1, CFC1, rt, fs);
1678 void Assembler::DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi) {
1682 *lo = i & 0xffffffff;
1689 void Assembler::add_d(FPURegister fd, FPURegister fs, FPURegister ft) {
1690 GenInstrRegister(COP1, D, ft, fs, fd, ADD_D);
1694 void Assembler::sub_d(FPURegister fd, FPURegister fs, FPURegister ft) {
1695 GenInstrRegister(COP1, D, ft, fs, fd, SUB_D);
1699 void Assembler::mul_d(FPURegister fd, FPURegister fs, FPURegister ft) {
1700 GenInstrRegister(COP1, D, ft, fs, fd, MUL_D);
1704 void Assembler::madd_d(FPURegister fd, FPURegister fr, FPURegister fs,
1706 GenInstrRegister(COP1X, fr, ft, fs, fd, MADD_D);
1710 void Assembler::div_d(FPURegister fd, FPURegister fs, FPURegister ft) {
1711 GenInstrRegister(COP1, D, ft, fs, fd, DIV_D);
1715 void Assembler::abs_d(FPURegister fd, FPURegister fs) {
1716 GenInstrRegister(COP1, D, f0, fs, fd, ABS_D);
1720 void Assembler::mov_d(FPURegister fd, FPURegister fs) {
1721 GenInstrRegister(COP1, D, f0, fs, fd, MOV_D);
1725 void Assembler::neg_d(FPURegister fd, FPURegister fs) {
1726 GenInstrRegister(COP1, D, f0, fs, fd, NEG_D);
1730 void Assembler::sqrt_d(FPURegister fd, FPURegister fs) {
1731 GenInstrRegister(COP1, D, f0, fs, fd, SQRT_D);
1737 void Assembler::cvt_w_s(FPURegister fd, FPURegister fs) {
1738 GenInstrRegister(COP1, S, f0, fs, fd, CVT_W_S);
1742 void Assembler::cvt_w_d(FPURegister fd, FPURegister fs) {
1743 GenInstrRegister(COP1, D, f0, fs, fd, CVT_W_D);
1747 void Assembler::trunc_w_s(FPURegister fd, FPURegister fs) {
1748 GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_W_S);
1752 void Assembler::trunc_w_d(FPURegister fd, FPURegister fs) {
1753 GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_W_D);
1757 void Assembler::round_w_s(FPURegister fd, FPURegister fs) {
1758 GenInstrRegister(COP1, S, f0, fs, fd, ROUND_W_S);
1762 void Assembler::round_w_d(FPURegister fd, FPURegister fs) {
1763 GenInstrRegister(COP1, D, f0, fs, fd, ROUND_W_D);
1767 void Assembler::floor_w_s(FPURegister fd, FPURegister fs) {
1768 GenInstrRegister(COP1, S, f0, fs, fd, FLOOR_W_S);
1772 void Assembler::floor_w_d(FPURegister fd, FPURegister fs) {
1773 GenInstrRegister(COP1, D, f0, fs, fd, FLOOR_W_D);
1777 void Assembler::ceil_w_s(FPURegister fd, FPURegister fs) {
1778 GenInstrRegister(COP1, S, f0, fs, fd, CEIL_W_S);
1782 void Assembler::ceil_w_d(FPURegister fd, FPURegister fs) {
1783 GenInstrRegister(COP1, D, f0, fs, fd, CEIL_W_D);
1787 void Assembler::cvt_l_s(FPURegister fd, FPURegister fs) {
1788 DCHECK(kArchVariant == kMips32r2);
1789 GenInstrRegister(COP1, S, f0, fs, fd, CVT_L_S);
1793 void Assembler::cvt_l_d(FPURegister fd, FPURegister fs) {
1794 DCHECK(kArchVariant == kMips32r2);
1795 GenInstrRegister(COP1, D, f0, fs, fd, CVT_L_D);
1799 void Assembler::trunc_l_s(FPURegister fd, FPURegister fs) {
1800 DCHECK(kArchVariant == kMips32r2);
1801 GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_L_S);
1805 void Assembler::trunc_l_d(FPURegister fd, FPURegister fs) {
1806 DCHECK(kArchVariant == kMips32r2);
1807 GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_L_D);
1811 void Assembler::round_l_s(FPURegister fd, FPURegister fs) {
1812 GenInstrRegister(COP1, S, f0, fs, fd, ROUND_L_S);
1816 void Assembler::round_l_d(FPURegister fd, FPURegister fs) {
1817 GenInstrRegister(COP1, D, f0, fs, fd, ROUND_L_D);
1821 void Assembler::floor_l_s(FPURegister fd, FPURegister fs) {
1822 GenInstrRegister(COP1, S, f0, fs, fd, FLOOR_L_S);
1826 void Assembler::floor_l_d(FPURegister fd, FPURegister fs) {
1827 GenInstrRegister(COP1, D, f0, fs, fd, FLOOR_L_D);
1831 void Assembler::ceil_l_s(FPURegister fd, FPURegister fs) {
1832 GenInstrRegister(COP1, S, f0, fs, fd, CEIL_L_S);
1836 void Assembler::ceil_l_d(FPURegister fd, FPURegister fs) {
1837 GenInstrRegister(COP1, D, f0, fs, fd, CEIL_L_D);
1841 void Assembler::cvt_s_w(FPURegister fd, FPURegister fs) {
1842 GenInstrRegister(COP1, W, f0, fs, fd, CVT_S_W);
1846 void Assembler::cvt_s_l(FPURegister fd, FPURegister fs) {
1847 DCHECK(kArchVariant == kMips32r2);
1848 GenInstrRegister(COP1, L, f0, fs, fd, CVT_S_L);
1852 void Assembler::cvt_s_d(FPURegister fd, FPURegister fs) {
1853 GenInstrRegister(COP1, D, f0, fs, fd, CVT_S_D);
1857 void Assembler::cvt_d_w(FPURegister fd, FPURegister fs) {
1858 GenInstrRegister(COP1, W, f0, fs, fd, CVT_D_W);
1862 void Assembler::cvt_d_l(FPURegister fd, FPURegister fs) {
1863 DCHECK(kArchVariant == kMips32r2);
1864 GenInstrRegister(COP1, L, f0, fs, fd, CVT_D_L);
1868 void Assembler::cvt_d_s(FPURegister fd, FPURegister fs) {
1869 GenInstrRegister(COP1, S, f0, fs, fd, CVT_D_S);
1874 void Assembler::c(FPUCondition cond, SecondaryField fmt,
1875 FPURegister fs, FPURegister ft, uint16_t cc) {
1876 DCHECK(is_uint3(cc));
1877 DCHECK((fmt & ~(31 << kRsShift)) == 0);
1878 Instr instr = COP1 | fmt | ft.code() << 16 | fs.code() << kFsShift
1879 | cc << 8 | 3 << 4 | cond;
1884 void Assembler::fcmp(FPURegister src1, const double src2,
1885 FPUCondition cond) {
1886 DCHECK(src2 == 0.0);
1887 mtc1(zero_reg, f14);
1889 c(cond, D, src1, f14, 0);
1893 void Assembler::bc1f(int16_t offset, uint16_t cc) {
1894 DCHECK(is_uint3(cc));
1895 Instr instr = COP1 | BC1 | cc << 18 | 0 << 16 | (offset & kImm16Mask);
1900 void Assembler::bc1t(int16_t offset, uint16_t cc) {
1901 DCHECK(is_uint3(cc));
1902 Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask);
1908 void Assembler::RecordJSReturn() {
1909 positions_recorder()->WriteRecordedPositions();
1911 RecordRelocInfo(RelocInfo::JS_RETURN);
1915 void Assembler::RecordDebugBreakSlot() {
1916 positions_recorder()->WriteRecordedPositions();
1918 RecordRelocInfo(RelocInfo::DEBUG_BREAK_SLOT);
1922 void Assembler::RecordComment(const char* msg) {
1923 if (FLAG_code_comments) {
1925 RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg));
1930 int Assembler::RelocateInternalReference(byte* pc, intptr_t pc_delta) {
1931 Instr instr = instr_at(pc);
1932 DCHECK(IsJ(instr) || IsLui(instr));
1934 Instr instr_lui = instr_at(pc + 0 * Assembler::kInstrSize);
1935 Instr instr_ori = instr_at(pc + 1 * Assembler::kInstrSize);
1936 DCHECK(IsOri(instr_ori));
1937 int32_t imm = (instr_lui & static_cast<int32_t>(kImm16Mask)) << kLuiShift;
1938 imm |= (instr_ori & static_cast<int32_t>(kImm16Mask));
1939 if (imm == kEndOfJumpChain) {
1940 return 0; // Number of instructions patched.
1943 DCHECK((imm & 3) == 0);
1945 instr_lui &= ~kImm16Mask;
1946 instr_ori &= ~kImm16Mask;
1948 instr_at_put(pc + 0 * Assembler::kInstrSize,
1949 instr_lui | ((imm >> kLuiShift) & kImm16Mask));
1950 instr_at_put(pc + 1 * Assembler::kInstrSize,
1951 instr_ori | (imm & kImm16Mask));
1952 return 2; // Number of instructions patched.
1954 uint32_t imm28 = (instr & static_cast<int32_t>(kImm26Mask)) << 2;
1955 if (static_cast<int32_t>(imm28) == kEndOfJumpChain) {
1956 return 0; // Number of instructions patched.
1959 imm28 &= kImm28Mask;
1960 DCHECK((imm28 & 3) == 0);
1962 instr &= ~kImm26Mask;
1963 uint32_t imm26 = imm28 >> 2;
1964 DCHECK(is_uint26(imm26));
1966 instr_at_put(pc, instr | (imm26 & kImm26Mask));
1967 return 1; // Number of instructions patched.
1972 void Assembler::GrowBuffer() {
1973 if (!own_buffer_) FATAL("external code buffer is too small");
1975 // Compute new buffer size.
1976 CodeDesc desc; // The new buffer.
1977 if (buffer_size_ < 1 * MB) {
1978 desc.buffer_size = 2*buffer_size_;
1980 desc.buffer_size = buffer_size_ + 1*MB;
1982 CHECK_GT(desc.buffer_size, 0); // No overflow.
1984 // Set up new buffer.
1985 desc.buffer = NewArray<byte>(desc.buffer_size);
1987 desc.instr_size = pc_offset();
1988 desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
1991 int pc_delta = desc.buffer - buffer_;
1992 int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
1993 MemMove(desc.buffer, buffer_, desc.instr_size);
1994 MemMove(reloc_info_writer.pos() + rc_delta, reloc_info_writer.pos(),
1998 DeleteArray(buffer_);
1999 buffer_ = desc.buffer;
2000 buffer_size_ = desc.buffer_size;
2002 reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
2003 reloc_info_writer.last_pc() + pc_delta);
2005 // Relocate runtime entries.
2006 for (RelocIterator it(desc); !it.done(); it.next()) {
2007 RelocInfo::Mode rmode = it.rinfo()->rmode();
2008 if (rmode == RelocInfo::INTERNAL_REFERENCE) {
2009 byte* p = reinterpret_cast<byte*>(it.rinfo()->pc());
2010 RelocateInternalReference(p, pc_delta);
2014 DCHECK(!overflow());
2018 void Assembler::db(uint8_t data) {
2020 *reinterpret_cast<uint8_t*>(pc_) = data;
2021 pc_ += sizeof(uint8_t);
2025 void Assembler::dd(uint32_t data) {
2027 *reinterpret_cast<uint32_t*>(pc_) = data;
2028 pc_ += sizeof(uint32_t);
2032 void Assembler::emit_code_stub_address(Code* stub) {
2034 *reinterpret_cast<uint32_t*>(pc_) =
2035 reinterpret_cast<uint32_t>(stub->instruction_start());
2036 pc_ += sizeof(uint32_t);
2040 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
2041 // We do not try to reuse pool constants.
2042 RelocInfo rinfo(pc_, rmode, data, NULL);
2043 if (rmode >= RelocInfo::JS_RETURN && rmode <= RelocInfo::DEBUG_BREAK_SLOT) {
2044 // Adjust code for new modes.
2045 DCHECK(RelocInfo::IsDebugBreakSlot(rmode)
2046 || RelocInfo::IsJSReturn(rmode)
2047 || RelocInfo::IsComment(rmode)
2048 || RelocInfo::IsPosition(rmode));
2049 // These modes do not need an entry in the constant pool.
2051 if (!RelocInfo::IsNone(rinfo.rmode())) {
2052 // Don't record external references unless the heap will be serialized.
2053 if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
2054 !serializer_enabled() && !emit_debug_code()) {
2057 DCHECK(buffer_space() >= kMaxRelocSize); // Too late to grow buffer here.
2058 if (rmode == RelocInfo::CODE_TARGET_WITH_ID) {
2059 RelocInfo reloc_info_with_ast_id(pc_,
2061 RecordedAstId().ToInt(),
2063 ClearRecordedAstId();
2064 reloc_info_writer.Write(&reloc_info_with_ast_id);
2066 reloc_info_writer.Write(&rinfo);
2072 void Assembler::BlockTrampolinePoolFor(int instructions) {
2073 BlockTrampolinePoolBefore(pc_offset() + instructions * kInstrSize);
2077 void Assembler::CheckTrampolinePool() {
2078 // Some small sequences of instructions must not be broken up by the
2079 // insertion of a trampoline pool; such sequences are protected by setting
2080 // either trampoline_pool_blocked_nesting_ or no_trampoline_pool_before_,
2081 // which are both checked here. Also, recursive calls to CheckTrampolinePool
2082 // are blocked by trampoline_pool_blocked_nesting_.
2083 if ((trampoline_pool_blocked_nesting_ > 0) ||
2084 (pc_offset() < no_trampoline_pool_before_)) {
2085 // Emission is currently blocked; make sure we try again as soon as
2087 if (trampoline_pool_blocked_nesting_ > 0) {
2088 next_buffer_check_ = pc_offset() + kInstrSize;
2090 next_buffer_check_ = no_trampoline_pool_before_;
2095 DCHECK(!trampoline_emitted_);
2096 DCHECK(unbound_labels_count_ >= 0);
2097 if (unbound_labels_count_ > 0) {
2098 // First we emit jump (2 instructions), then we emit trampoline pool.
2099 { BlockTrampolinePoolScope block_trampoline_pool(this);
2104 int pool_start = pc_offset();
2105 for (int i = 0; i < unbound_labels_count_; i++) {
2107 imm32 = jump_address(&after_pool);
2108 { BlockGrowBufferScope block_buf_growth(this);
2109 // Buffer growth (and relocation) must be blocked for internal
2110 // references until associated instructions are emitted and available
2112 RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE);
2113 lui(at, (imm32 & kHiMask) >> kLuiShift);
2114 ori(at, at, (imm32 & kImm16Mask));
2120 trampoline_ = Trampoline(pool_start, unbound_labels_count_);
2122 trampoline_emitted_ = true;
2123 // As we are only going to emit trampoline once, we need to prevent any
2124 // further emission.
2125 next_buffer_check_ = kMaxInt;
2128 // Number of branches to unbound label at this point is zero, so we can
2129 // move next buffer check to maximum.
2130 next_buffer_check_ = pc_offset() +
2131 kMaxBranchOffset - kTrampolineSlotsSize * 16;
2137 Address Assembler::target_address_at(Address pc) {
2138 Instr instr1 = instr_at(pc);
2139 Instr instr2 = instr_at(pc + kInstrSize);
2140 // Interpret 2 instructions generated by li: lui/ori
2141 if ((GetOpcodeField(instr1) == LUI) && (GetOpcodeField(instr2) == ORI)) {
2142 // Assemble the 32 bit value.
2143 return reinterpret_cast<Address>(
2144 (GetImmediate16(instr1) << 16) | GetImmediate16(instr2));
2147 // We should never get here, force a bad address if we do.
2149 return (Address)0x0;
2153 // MIPS and ia32 use opposite encoding for qNaN and sNaN, such that ia32
2154 // qNaN is a MIPS sNaN, and ia32 sNaN is MIPS qNaN. If running from a heap
2155 // snapshot generated on ia32, the resulting MIPS sNaN must be quieted.
2156 // OS::nan_value() returns a qNaN.
2157 void Assembler::QuietNaN(HeapObject* object) {
2158 HeapNumber::cast(object)->set_value(base::OS::nan_value());
2162 // On Mips, a target address is stored in a lui/ori instruction pair, each
2163 // of which load 16 bits of the 32-bit address to a register.
2164 // Patching the address must replace both instr, and flush the i-cache.
2166 // There is an optimization below, which emits a nop when the address
2167 // fits in just 16 bits. This is unlikely to help, and should be benchmarked,
2168 // and possibly removed.
2169 void Assembler::set_target_address_at(Address pc,
2171 ICacheFlushMode icache_flush_mode) {
2172 Instr instr2 = instr_at(pc + kInstrSize);
2173 uint32_t rt_code = GetRtField(instr2);
2174 uint32_t* p = reinterpret_cast<uint32_t*>(pc);
2175 uint32_t itarget = reinterpret_cast<uint32_t>(target);
2178 // Check we have the result from a li macro-instruction, using instr pair.
2179 Instr instr1 = instr_at(pc);
2180 CHECK((GetOpcodeField(instr1) == LUI && GetOpcodeField(instr2) == ORI));
2183 // Must use 2 instructions to insure patchable code => just use lui and ori.
2184 // lui rt, upper-16.
2185 // ori rt rt, lower-16.
2186 *p = LUI | rt_code | ((itarget & kHiMask) >> kLuiShift);
2187 *(p+1) = ORI | rt_code | (rt_code << 5) | (itarget & kImm16Mask);
2189 // The following code is an optimization for the common case of Call()
2190 // or Jump() which is load to register, and jump through register:
2191 // li(t9, address); jalr(t9) (or jr(t9)).
2192 // If the destination address is in the same 256 MB page as the call, it
2193 // is faster to do a direct jal, or j, rather than jump thru register, since
2194 // that lets the cpu pipeline prefetch the target address. However each
2195 // time the address above is patched, we have to patch the direct jal/j
2196 // instruction, as well as possibly revert to jalr/jr if we now cross a
2197 // 256 MB page. Note that with the jal/j instructions, we do not need to
2198 // load the register, but that code is left, since it makes it easy to
2199 // revert this process. A further optimization could try replacing the
2200 // li sequence with nops.
2201 // This optimization can only be applied if the rt-code from instr2 is the
2202 // register used for the jalr/jr. Finally, we have to skip 'jr ra', which is
2203 // mips return. Occasionally this lands after an li().
2205 Instr instr3 = instr_at(pc + 2 * kInstrSize);
2206 uint32_t ipc = reinterpret_cast<uint32_t>(pc + 3 * kInstrSize);
2207 bool in_range = ((ipc ^ itarget) >> (kImm26Bits + kImmFieldShift)) == 0;
2208 uint32_t target_field =
2209 static_cast<uint32_t>(itarget & kJumpAddrMask) >> kImmFieldShift;
2210 bool patched_jump = false;
2212 #ifndef ALLOW_JAL_IN_BOUNDARY_REGION
2213 // This is a workaround to the 24k core E156 bug (affect some 34k cores also).
2214 // Since the excluded space is only 64KB out of 256MB (0.02 %), we will just
2215 // apply this workaround for all cores so we don't have to identify the core.
2217 // The 24k core E156 bug has some very specific requirements, we only check
2218 // the most simple one: if the address of the delay slot instruction is in
2219 // the first or last 32 KB of the 256 MB segment.
2220 uint32_t segment_mask = ((256 * MB) - 1) ^ ((32 * KB) - 1);
2221 uint32_t ipc_segment_addr = ipc & segment_mask;
2222 if (ipc_segment_addr == 0 || ipc_segment_addr == segment_mask)
2227 if (IsJalr(instr3)) {
2228 // Try to convert JALR to JAL.
2229 if (in_range && GetRt(instr2) == GetRs(instr3)) {
2230 *(p+2) = JAL | target_field;
2231 patched_jump = true;
2233 } else if (IsJr(instr3)) {
2234 // Try to convert JR to J, skip returns (jr ra).
2235 bool is_ret = static_cast<int>(GetRs(instr3)) == ra.code();
2236 if (in_range && !is_ret && GetRt(instr2) == GetRs(instr3)) {
2237 *(p+2) = J | target_field;
2238 patched_jump = true;
2240 } else if (IsJal(instr3)) {
2242 // We are patching an already converted JAL.
2243 *(p+2) = JAL | target_field;
2245 // Patch JAL, but out of range, revert to JALR.
2246 // JALR rs reg is the rt reg specified in the ORI instruction.
2247 uint32_t rs_field = GetRt(instr2) << kRsShift;
2248 uint32_t rd_field = ra.code() << kRdShift; // Return-address (ra) reg.
2249 *(p+2) = SPECIAL | rs_field | rd_field | JALR;
2251 patched_jump = true;
2252 } else if (IsJ(instr3)) {
2254 // We are patching an already converted J (jump).
2255 *(p+2) = J | target_field;
2257 // Trying patch J, but out of range, just go back to JR.
2258 // JR 'rs' reg is the 'rt' reg specified in the ORI instruction (instr2).
2259 uint32_t rs_field = GetRt(instr2) << kRsShift;
2260 *(p+2) = SPECIAL | rs_field | JR;
2262 patched_jump = true;
2265 if (icache_flush_mode != SKIP_ICACHE_FLUSH) {
2266 CpuFeatures::FlushICache(pc, (patched_jump ? 3 : 2) * sizeof(int32_t));
2271 void Assembler::JumpLabelToJumpRegister(Address pc) {
2272 // Address pc points to lui/ori instructions.
2273 // Jump to label may follow at pc + 2 * kInstrSize.
2274 uint32_t* p = reinterpret_cast<uint32_t*>(pc);
2276 Instr instr1 = instr_at(pc);
2278 Instr instr2 = instr_at(pc + 1 * kInstrSize);
2279 Instr instr3 = instr_at(pc + 2 * kInstrSize);
2280 bool patched = false;
2282 if (IsJal(instr3)) {
2283 DCHECK(GetOpcodeField(instr1) == LUI);
2284 DCHECK(GetOpcodeField(instr2) == ORI);
2286 uint32_t rs_field = GetRt(instr2) << kRsShift;
2287 uint32_t rd_field = ra.code() << kRdShift; // Return-address (ra) reg.
2288 *(p+2) = SPECIAL | rs_field | rd_field | JALR;
2290 } else if (IsJ(instr3)) {
2291 DCHECK(GetOpcodeField(instr1) == LUI);
2292 DCHECK(GetOpcodeField(instr2) == ORI);
2294 uint32_t rs_field = GetRt(instr2) << kRsShift;
2295 *(p+2) = SPECIAL | rs_field | JR;
2300 CpuFeatures::FlushICache(pc+2, sizeof(Address));
2305 Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) {
2306 // No out-of-line constant pool support.
2307 DCHECK(!FLAG_enable_ool_constant_pool);
2308 return isolate->factory()->empty_constant_pool_array();
2312 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) {
2313 // No out-of-line constant pool support.
2314 DCHECK(!FLAG_enable_ool_constant_pool);
2319 } } // namespace v8::internal
2321 #endif // V8_TARGET_ARCH_MIPS