1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
11 #if V8_TARGET_ARCH_IA32
24 //------------------------------------------------------------------
26 //------------------------------------------------------------------
28 int b; // -1 terminates, otherwise must be in range (0..255)
30 OperandOrder op_order_;
34 static const ByteMnemonic two_operands_instr[] = {
35 {0x01, "add", OPER_REG_OP_ORDER},
36 {0x03, "add", REG_OPER_OP_ORDER},
37 {0x09, "or", OPER_REG_OP_ORDER},
38 {0x0B, "or", REG_OPER_OP_ORDER},
39 {0x1B, "sbb", REG_OPER_OP_ORDER},
40 {0x21, "and", OPER_REG_OP_ORDER},
41 {0x23, "and", REG_OPER_OP_ORDER},
42 {0x29, "sub", OPER_REG_OP_ORDER},
43 {0x2A, "subb", REG_OPER_OP_ORDER},
44 {0x2B, "sub", REG_OPER_OP_ORDER},
45 {0x31, "xor", OPER_REG_OP_ORDER},
46 {0x33, "xor", REG_OPER_OP_ORDER},
47 {0x38, "cmpb", OPER_REG_OP_ORDER},
48 {0x3A, "cmpb", REG_OPER_OP_ORDER},
49 {0x3B, "cmp", REG_OPER_OP_ORDER},
50 {0x84, "test_b", REG_OPER_OP_ORDER},
51 {0x85, "test", REG_OPER_OP_ORDER},
52 {0x87, "xchg", REG_OPER_OP_ORDER},
53 {0x8A, "mov_b", REG_OPER_OP_ORDER},
54 {0x8B, "mov", REG_OPER_OP_ORDER},
55 {0x8D, "lea", REG_OPER_OP_ORDER},
56 {-1, "", UNSET_OP_ORDER}
60 static const ByteMnemonic zero_operands_instr[] = {
61 {0xC3, "ret", UNSET_OP_ORDER},
62 {0xC9, "leave", UNSET_OP_ORDER},
63 {0x90, "nop", UNSET_OP_ORDER},
64 {0xF4, "hlt", UNSET_OP_ORDER},
65 {0xCC, "int3", UNSET_OP_ORDER},
66 {0x60, "pushad", UNSET_OP_ORDER},
67 {0x61, "popad", UNSET_OP_ORDER},
68 {0x9C, "pushfd", UNSET_OP_ORDER},
69 {0x9D, "popfd", UNSET_OP_ORDER},
70 {0x9E, "sahf", UNSET_OP_ORDER},
71 {0x99, "cdq", UNSET_OP_ORDER},
72 {0x9B, "fwait", UNSET_OP_ORDER},
73 {0xFC, "cld", UNSET_OP_ORDER},
74 {0xAB, "stos", UNSET_OP_ORDER},
75 {-1, "", UNSET_OP_ORDER}
79 static const ByteMnemonic call_jump_instr[] = {
80 {0xE8, "call", UNSET_OP_ORDER},
81 {0xE9, "jmp", UNSET_OP_ORDER},
82 {-1, "", UNSET_OP_ORDER}
86 static const ByteMnemonic short_immediate_instr[] = {
87 {0x05, "add", UNSET_OP_ORDER},
88 {0x0D, "or", UNSET_OP_ORDER},
89 {0x15, "adc", UNSET_OP_ORDER},
90 {0x25, "and", UNSET_OP_ORDER},
91 {0x2D, "sub", UNSET_OP_ORDER},
92 {0x35, "xor", UNSET_OP_ORDER},
93 {0x3D, "cmp", UNSET_OP_ORDER},
94 {-1, "", UNSET_OP_ORDER}
98 // Generally we don't want to generate these because they are subject to partial
99 // register stalls. They are included for completeness and because the cmp
100 // variant is used by the RecordWrite stub. Because it does not update the
101 // register it is not subject to partial register stalls.
102 static ByteMnemonic byte_immediate_instr[] = {
103 {0x0c, "or", UNSET_OP_ORDER},
104 {0x24, "and", UNSET_OP_ORDER},
105 {0x34, "xor", UNSET_OP_ORDER},
106 {0x3c, "cmp", UNSET_OP_ORDER},
107 {-1, "", UNSET_OP_ORDER}
111 static const char* const jump_conditional_mnem[] = {
112 /*0*/ "jo", "jno", "jc", "jnc",
113 /*4*/ "jz", "jnz", "jna", "ja",
114 /*8*/ "js", "jns", "jpe", "jpo",
115 /*12*/ "jl", "jnl", "jng", "jg"
119 static const char* const set_conditional_mnem[] = {
120 /*0*/ "seto", "setno", "setc", "setnc",
121 /*4*/ "setz", "setnz", "setna", "seta",
122 /*8*/ "sets", "setns", "setpe", "setpo",
123 /*12*/ "setl", "setnl", "setng", "setg"
127 static const char* const conditional_move_mnem[] = {
128 /*0*/ "cmovo", "cmovno", "cmovc", "cmovnc",
129 /*4*/ "cmovz", "cmovnz", "cmovna", "cmova",
130 /*8*/ "cmovs", "cmovns", "cmovpe", "cmovpo",
131 /*12*/ "cmovl", "cmovnl", "cmovng", "cmovg"
135 enum InstructionType {
139 JUMP_CONDITIONAL_SHORT_INSTR,
143 SHORT_IMMEDIATE_INSTR,
148 struct InstructionDesc {
150 InstructionType type;
151 OperandOrder op_order_;
155 class InstructionTable {
158 const InstructionDesc& Get(byte x) const { return instructions_[x]; }
159 static InstructionTable* get_instance() {
160 static InstructionTable table;
165 InstructionDesc instructions_[256];
168 void CopyTable(const ByteMnemonic bm[], InstructionType type);
169 void SetTableRange(InstructionType type,
173 void AddJumpConditionalShort();
177 InstructionTable::InstructionTable() {
183 void InstructionTable::Clear() {
184 for (int i = 0; i < 256; i++) {
185 instructions_[i].mnem = "";
186 instructions_[i].type = NO_INSTR;
187 instructions_[i].op_order_ = UNSET_OP_ORDER;
192 void InstructionTable::Init() {
193 CopyTable(two_operands_instr, TWO_OPERANDS_INSTR);
194 CopyTable(zero_operands_instr, ZERO_OPERANDS_INSTR);
195 CopyTable(call_jump_instr, CALL_JUMP_INSTR);
196 CopyTable(short_immediate_instr, SHORT_IMMEDIATE_INSTR);
197 CopyTable(byte_immediate_instr, BYTE_IMMEDIATE_INSTR);
198 AddJumpConditionalShort();
199 SetTableRange(REGISTER_INSTR, 0x40, 0x47, "inc");
200 SetTableRange(REGISTER_INSTR, 0x48, 0x4F, "dec");
201 SetTableRange(REGISTER_INSTR, 0x50, 0x57, "push");
202 SetTableRange(REGISTER_INSTR, 0x58, 0x5F, "pop");
203 SetTableRange(REGISTER_INSTR, 0x91, 0x97, "xchg eax,"); // 0x90 is nop.
204 SetTableRange(MOVE_REG_INSTR, 0xB8, 0xBF, "mov");
208 void InstructionTable::CopyTable(const ByteMnemonic bm[],
209 InstructionType type) {
210 for (int i = 0; bm[i].b >= 0; i++) {
211 InstructionDesc* id = &instructions_[bm[i].b];
212 id->mnem = bm[i].mnem;
213 id->op_order_ = bm[i].op_order_;
214 ASSERT_EQ(NO_INSTR, id->type); // Information not already entered.
220 void InstructionTable::SetTableRange(InstructionType type,
224 for (byte b = start; b <= end; b++) {
225 InstructionDesc* id = &instructions_[b];
226 ASSERT_EQ(NO_INSTR, id->type); // Information not already entered.
233 void InstructionTable::AddJumpConditionalShort() {
234 for (byte b = 0x70; b <= 0x7F; b++) {
235 InstructionDesc* id = &instructions_[b];
236 ASSERT_EQ(NO_INSTR, id->type); // Information not already entered.
237 id->mnem = jump_conditional_mnem[b & 0x0F];
238 id->type = JUMP_CONDITIONAL_SHORT_INSTR;
243 // The IA32 disassembler implementation.
244 class DisassemblerIA32 {
246 DisassemblerIA32(const NameConverter& converter,
247 bool abort_on_unimplemented = true)
248 : converter_(converter),
249 instruction_table_(InstructionTable::get_instance()),
251 abort_on_unimplemented_(abort_on_unimplemented) {
252 tmp_buffer_[0] = '\0';
255 virtual ~DisassemblerIA32() {}
257 // Writes one disassembled instruction into 'buffer' (0-terminated).
258 // Returns the length of the disassembled machine instruction in bytes.
259 int InstructionDecode(v8::internal::Vector<char> buffer, byte* instruction);
262 const NameConverter& converter_;
263 InstructionTable* instruction_table_;
264 v8::internal::EmbeddedVector<char, 128> tmp_buffer_;
265 unsigned int tmp_buffer_pos_;
266 bool abort_on_unimplemented_;
280 enum ShiftOpcodeExtension {
291 const char* NameOfCPURegister(int reg) const {
292 return converter_.NameOfCPURegister(reg);
296 const char* NameOfByteCPURegister(int reg) const {
297 return converter_.NameOfByteCPURegister(reg);
301 const char* NameOfXMMRegister(int reg) const {
302 return converter_.NameOfXMMRegister(reg);
306 const char* NameOfAddress(byte* addr) const {
307 return converter_.NameOfAddress(addr);
311 // Disassembler helper functions.
312 static void get_modrm(byte data, int* mod, int* regop, int* rm) {
313 *mod = (data >> 6) & 3;
314 *regop = (data & 0x38) >> 3;
319 static void get_sib(byte data, int* scale, int* index, int* base) {
320 *scale = (data >> 6) & 3;
321 *index = (data >> 3) & 7;
325 typedef const char* (DisassemblerIA32::*RegisterNameMapping)(int reg) const;
327 int PrintRightOperandHelper(byte* modrmp, RegisterNameMapping register_name);
328 int PrintRightOperand(byte* modrmp);
329 int PrintRightByteOperand(byte* modrmp);
330 int PrintRightXMMOperand(byte* modrmp);
331 int PrintOperands(const char* mnem, OperandOrder op_order, byte* data);
332 int PrintImmediateOp(byte* data);
333 int F7Instruction(byte* data);
334 int D1D3C1Instruction(byte* data);
335 int JumpShort(byte* data);
336 int JumpConditional(byte* data, const char* comment);
337 int JumpConditionalShort(byte* data, const char* comment);
338 int SetCC(byte* data);
339 int CMov(byte* data);
340 int FPUInstruction(byte* data);
341 int MemoryFPUInstruction(int escape_opcode, int regop, byte* modrm_start);
342 int RegisterFPUInstruction(int escape_opcode, byte modrm_byte);
343 void AppendToBuffer(const char* format, ...);
346 void UnimplementedInstruction() {
347 if (abort_on_unimplemented_) {
350 AppendToBuffer("'Unimplemented Instruction'");
356 void DisassemblerIA32::AppendToBuffer(const char* format, ...) {
357 v8::internal::Vector<char> buf = tmp_buffer_ + tmp_buffer_pos_;
359 va_start(args, format);
360 int result = v8::internal::OS::VSNPrintF(buf, format, args);
362 tmp_buffer_pos_ += result;
365 int DisassemblerIA32::PrintRightOperandHelper(
367 RegisterNameMapping direct_register_name) {
369 get_modrm(*modrmp, &mod, ®op, &rm);
370 RegisterNameMapping register_name = (mod == 3) ? direct_register_name :
371 &DisassemblerIA32::NameOfCPURegister;
375 int32_t disp = *reinterpret_cast<int32_t*>(modrmp+1);
376 AppendToBuffer("[0x%x]", disp);
378 } else if (rm == esp) {
379 byte sib = *(modrmp + 1);
380 int scale, index, base;
381 get_sib(sib, &scale, &index, &base);
382 if (index == esp && base == esp && scale == 0 /*times_1*/) {
383 AppendToBuffer("[%s]", (this->*register_name)(rm));
385 } else if (base == ebp) {
386 int32_t disp = *reinterpret_cast<int32_t*>(modrmp + 2);
387 AppendToBuffer("[%s*%d%s0x%x]",
388 (this->*register_name)(index),
390 disp < 0 ? "-" : "+",
391 disp < 0 ? -disp : disp);
393 } else if (index != esp && base != ebp) {
394 // [base+index*scale]
395 AppendToBuffer("[%s+%s*%d]",
396 (this->*register_name)(base),
397 (this->*register_name)(index),
401 UnimplementedInstruction();
405 AppendToBuffer("[%s]", (this->*register_name)(rm));
409 case 1: // fall through
412 byte sib = *(modrmp + 1);
413 int scale, index, base;
414 get_sib(sib, &scale, &index, &base);
415 int disp = mod == 2 ? *reinterpret_cast<int32_t*>(modrmp + 2)
416 : *reinterpret_cast<int8_t*>(modrmp + 2);
417 if (index == base && index == rm /*esp*/ && scale == 0 /*times_1*/) {
418 AppendToBuffer("[%s%s0x%x]",
419 (this->*register_name)(rm),
420 disp < 0 ? "-" : "+",
421 disp < 0 ? -disp : disp);
423 AppendToBuffer("[%s+%s*%d%s0x%x]",
424 (this->*register_name)(base),
425 (this->*register_name)(index),
427 disp < 0 ? "-" : "+",
428 disp < 0 ? -disp : disp);
430 return mod == 2 ? 6 : 3;
433 int disp = mod == 2 ? *reinterpret_cast<int32_t*>(modrmp + 1)
434 : *reinterpret_cast<int8_t*>(modrmp + 1);
435 AppendToBuffer("[%s%s0x%x]",
436 (this->*register_name)(rm),
437 disp < 0 ? "-" : "+",
438 disp < 0 ? -disp : disp);
439 return mod == 2 ? 5 : 2;
443 AppendToBuffer("%s", (this->*register_name)(rm));
446 UnimplementedInstruction();
453 int DisassemblerIA32::PrintRightOperand(byte* modrmp) {
454 return PrintRightOperandHelper(modrmp, &DisassemblerIA32::NameOfCPURegister);
458 int DisassemblerIA32::PrintRightByteOperand(byte* modrmp) {
459 return PrintRightOperandHelper(modrmp,
460 &DisassemblerIA32::NameOfByteCPURegister);
464 int DisassemblerIA32::PrintRightXMMOperand(byte* modrmp) {
465 return PrintRightOperandHelper(modrmp,
466 &DisassemblerIA32::NameOfXMMRegister);
470 // Returns number of bytes used including the current *data.
471 // Writes instruction's mnemonic, left and right operands to 'tmp_buffer_'.
472 int DisassemblerIA32::PrintOperands(const char* mnem,
473 OperandOrder op_order,
477 get_modrm(modrm, &mod, ®op, &rm);
480 case REG_OPER_OP_ORDER: {
481 AppendToBuffer("%s %s,", mnem, NameOfCPURegister(regop));
482 advance = PrintRightOperand(data);
485 case OPER_REG_OP_ORDER: {
486 AppendToBuffer("%s ", mnem);
487 advance = PrintRightOperand(data);
488 AppendToBuffer(",%s", NameOfCPURegister(regop));
499 // Returns number of bytes used by machine instruction, including *data byte.
500 // Writes immediate instructions to 'tmp_buffer_'.
501 int DisassemblerIA32::PrintImmediateOp(byte* data) {
502 bool sign_extension_bit = (*data & 0x02) != 0;
503 byte modrm = *(data+1);
505 get_modrm(modrm, &mod, ®op, &rm);
506 const char* mnem = "Imm???";
508 case 0: mnem = "add"; break;
509 case 1: mnem = "or"; break;
510 case 2: mnem = "adc"; break;
511 case 4: mnem = "and"; break;
512 case 5: mnem = "sub"; break;
513 case 6: mnem = "xor"; break;
514 case 7: mnem = "cmp"; break;
515 default: UnimplementedInstruction();
517 AppendToBuffer("%s ", mnem);
518 int count = PrintRightOperand(data+1);
519 if (sign_extension_bit) {
520 AppendToBuffer(",0x%x", *(data + 1 + count));
521 return 1 + count + 1 /*int8*/;
523 AppendToBuffer(",0x%x", *reinterpret_cast<int32_t*>(data + 1 + count));
524 return 1 + count + 4 /*int32_t*/;
529 // Returns number of bytes used, including *data.
530 int DisassemblerIA32::F7Instruction(byte* data) {
531 ASSERT_EQ(0xF7, *data);
532 byte modrm = *(data+1);
534 get_modrm(modrm, &mod, ®op, &rm);
535 if (mod == 3 && regop != 0) {
536 const char* mnem = NULL;
538 case 2: mnem = "not"; break;
539 case 3: mnem = "neg"; break;
540 case 4: mnem = "mul"; break;
541 case 5: mnem = "imul"; break;
542 case 7: mnem = "idiv"; break;
543 default: UnimplementedInstruction();
545 AppendToBuffer("%s %s", mnem, NameOfCPURegister(rm));
547 } else if (mod == 3 && regop == eax) {
548 int32_t imm = *reinterpret_cast<int32_t*>(data+2);
549 AppendToBuffer("test %s,0x%x", NameOfCPURegister(rm), imm);
551 } else if (regop == eax) {
552 AppendToBuffer("test ");
553 int count = PrintRightOperand(data+1);
554 int32_t imm = *reinterpret_cast<int32_t*>(data+1+count);
555 AppendToBuffer(",0x%x", imm);
556 return 1+count+4 /*int32_t*/;
558 UnimplementedInstruction();
564 int DisassemblerIA32::D1D3C1Instruction(byte* data) {
566 ASSERT(op == 0xD1 || op == 0xD3 || op == 0xC1);
567 byte modrm = *(data+1);
569 get_modrm(modrm, &mod, ®op, &rm);
573 const char* mnem = NULL;
575 case kROL: mnem = "rol"; break;
576 case kROR: mnem = "ror"; break;
577 case kRCL: mnem = "rcl"; break;
578 case kRCR: mnem = "rcr"; break;
579 case kSHL: mnem = "shl"; break;
580 case KSHR: mnem = "shr"; break;
581 case kSAR: mnem = "sar"; break;
582 default: UnimplementedInstruction();
586 } else if (op == 0xC1) {
589 } else if (op == 0xD3) {
590 // Shift/rotate by cl.
592 ASSERT_NE(NULL, mnem);
593 AppendToBuffer("%s %s,", mnem, NameOfCPURegister(rm));
595 AppendToBuffer("%d", imm8);
597 AppendToBuffer("cl");
600 UnimplementedInstruction();
606 // Returns number of bytes used, including *data.
607 int DisassemblerIA32::JumpShort(byte* data) {
608 ASSERT_EQ(0xEB, *data);
610 byte* dest = data + static_cast<int8_t>(b) + 2;
611 AppendToBuffer("jmp %s", NameOfAddress(dest));
616 // Returns number of bytes used, including *data.
617 int DisassemblerIA32::JumpConditional(byte* data, const char* comment) {
618 ASSERT_EQ(0x0F, *data);
619 byte cond = *(data+1) & 0x0F;
620 byte* dest = data + *reinterpret_cast<int32_t*>(data+2) + 6;
621 const char* mnem = jump_conditional_mnem[cond];
622 AppendToBuffer("%s %s", mnem, NameOfAddress(dest));
623 if (comment != NULL) {
624 AppendToBuffer(", %s", comment);
626 return 6; // includes 0x0F
630 // Returns number of bytes used, including *data.
631 int DisassemblerIA32::JumpConditionalShort(byte* data, const char* comment) {
632 byte cond = *data & 0x0F;
634 byte* dest = data + static_cast<int8_t>(b) + 2;
635 const char* mnem = jump_conditional_mnem[cond];
636 AppendToBuffer("%s %s", mnem, NameOfAddress(dest));
637 if (comment != NULL) {
638 AppendToBuffer(", %s", comment);
644 // Returns number of bytes used, including *data.
645 int DisassemblerIA32::SetCC(byte* data) {
646 ASSERT_EQ(0x0F, *data);
647 byte cond = *(data+1) & 0x0F;
648 const char* mnem = set_conditional_mnem[cond];
649 AppendToBuffer("%s ", mnem);
650 PrintRightByteOperand(data+2);
651 return 3; // Includes 0x0F.
655 // Returns number of bytes used, including *data.
656 int DisassemblerIA32::CMov(byte* data) {
657 ASSERT_EQ(0x0F, *data);
658 byte cond = *(data + 1) & 0x0F;
659 const char* mnem = conditional_move_mnem[cond];
660 int op_size = PrintOperands(mnem, REG_OPER_OP_ORDER, data + 2);
661 return 2 + op_size; // includes 0x0F
665 // Returns number of bytes used, including *data.
666 int DisassemblerIA32::FPUInstruction(byte* data) {
667 byte escape_opcode = *data;
668 ASSERT_EQ(0xD8, escape_opcode & 0xF8);
669 byte modrm_byte = *(data+1);
671 if (modrm_byte >= 0xC0) {
672 return RegisterFPUInstruction(escape_opcode, modrm_byte);
674 return MemoryFPUInstruction(escape_opcode, modrm_byte, data+1);
678 int DisassemblerIA32::MemoryFPUInstruction(int escape_opcode,
681 const char* mnem = "?";
682 int regop = (modrm_byte >> 3) & 0x7; // reg/op field of modrm byte.
683 switch (escape_opcode) {
684 case 0xD9: switch (regop) {
685 case 0: mnem = "fld_s"; break;
686 case 2: mnem = "fst_s"; break;
687 case 3: mnem = "fstp_s"; break;
688 case 7: mnem = "fstcw"; break;
689 default: UnimplementedInstruction();
693 case 0xDB: switch (regop) {
694 case 0: mnem = "fild_s"; break;
695 case 1: mnem = "fisttp_s"; break;
696 case 2: mnem = "fist_s"; break;
697 case 3: mnem = "fistp_s"; break;
698 default: UnimplementedInstruction();
702 case 0xDD: switch (regop) {
703 case 0: mnem = "fld_d"; break;
704 case 1: mnem = "fisttp_d"; break;
705 case 2: mnem = "fst_d"; break;
706 case 3: mnem = "fstp_d"; break;
707 default: UnimplementedInstruction();
711 case 0xDF: switch (regop) {
712 case 5: mnem = "fild_d"; break;
713 case 7: mnem = "fistp_d"; break;
714 default: UnimplementedInstruction();
718 default: UnimplementedInstruction();
720 AppendToBuffer("%s ", mnem);
721 int count = PrintRightOperand(modrm_start);
725 int DisassemblerIA32::RegisterFPUInstruction(int escape_opcode,
727 bool has_register = false; // Is the FPU register encoded in modrm_byte?
728 const char* mnem = "?";
730 switch (escape_opcode) {
733 switch (modrm_byte & 0xF8) {
734 case 0xC0: mnem = "fadd_i"; break;
735 case 0xE0: mnem = "fsub_i"; break;
736 case 0xC8: mnem = "fmul_i"; break;
737 case 0xF0: mnem = "fdiv_i"; break;
738 default: UnimplementedInstruction();
743 switch (modrm_byte & 0xF8) {
753 switch (modrm_byte) {
754 case 0xE0: mnem = "fchs"; break;
755 case 0xE1: mnem = "fabs"; break;
756 case 0xE4: mnem = "ftst"; break;
757 case 0xE8: mnem = "fld1"; break;
758 case 0xEB: mnem = "fldpi"; break;
759 case 0xED: mnem = "fldln2"; break;
760 case 0xEE: mnem = "fldz"; break;
761 case 0xF0: mnem = "f2xm1"; break;
762 case 0xF1: mnem = "fyl2x"; break;
763 case 0xF4: mnem = "fxtract"; break;
764 case 0xF5: mnem = "fprem1"; break;
765 case 0xF7: mnem = "fincstp"; break;
766 case 0xF8: mnem = "fprem"; break;
767 case 0xFC: mnem = "frndint"; break;
768 case 0xFD: mnem = "fscale"; break;
769 case 0xFE: mnem = "fsin"; break;
770 case 0xFF: mnem = "fcos"; break;
771 default: UnimplementedInstruction();
777 if (modrm_byte == 0xE9) {
780 UnimplementedInstruction();
785 if ((modrm_byte & 0xF8) == 0xE8) {
788 } else if (modrm_byte == 0xE2) {
790 } else if (modrm_byte == 0xE3) {
793 UnimplementedInstruction();
799 switch (modrm_byte & 0xF8) {
800 case 0xC0: mnem = "fadd"; break;
801 case 0xE8: mnem = "fsub"; break;
802 case 0xC8: mnem = "fmul"; break;
803 case 0xF8: mnem = "fdiv"; break;
804 default: UnimplementedInstruction();
810 switch (modrm_byte & 0xF8) {
811 case 0xC0: mnem = "ffree"; break;
812 case 0xD0: mnem = "fst"; break;
813 case 0xD8: mnem = "fstp"; break;
814 default: UnimplementedInstruction();
819 if (modrm_byte == 0xD9) {
823 switch (modrm_byte & 0xF8) {
824 case 0xC0: mnem = "faddp"; break;
825 case 0xE8: mnem = "fsubp"; break;
826 case 0xC8: mnem = "fmulp"; break;
827 case 0xF8: mnem = "fdivp"; break;
828 default: UnimplementedInstruction();
834 if (modrm_byte == 0xE0) {
836 } else if ((modrm_byte & 0xF8) == 0xE8) {
842 default: UnimplementedInstruction();
846 AppendToBuffer("%s st%d", mnem, modrm_byte & 0x7);
848 AppendToBuffer("%s", mnem);
854 // Mnemonics for instructions 0xF0 byte.
855 // Returns NULL if the instruction is not handled here.
856 static const char* F0Mnem(byte f0byte) {
858 case 0x18: return "prefetch";
859 case 0xA2: return "cpuid";
860 case 0xBE: return "movsx_b";
861 case 0xBF: return "movsx_w";
862 case 0xB6: return "movzx_b";
863 case 0xB7: return "movzx_w";
864 case 0xAF: return "imul";
865 case 0xA5: return "shld";
866 case 0xAD: return "shrd";
867 case 0xAC: return "shrd"; // 3-operand version.
868 case 0xAB: return "bts";
869 case 0xBD: return "bsr";
870 default: return NULL;
875 // Disassembled instruction '*instr' and writes it into 'out_buffer'.
876 int DisassemblerIA32::InstructionDecode(v8::internal::Vector<char> out_buffer,
878 tmp_buffer_pos_ = 0; // starting to write as position 0
881 const char* branch_hint = NULL;
882 // We use these two prefixes only with branch prediction
883 if (*data == 0x3E /*ds*/) {
884 branch_hint = "predicted taken";
886 } else if (*data == 0x2E /*cs*/) {
887 branch_hint = "predicted not taken";
890 bool processed = true; // Will be set to false if the current instruction
891 // is not in 'instructions' table.
892 const InstructionDesc& idesc = instruction_table_->Get(*data);
893 switch (idesc.type) {
894 case ZERO_OPERANDS_INSTR:
895 AppendToBuffer(idesc.mnem);
899 case TWO_OPERANDS_INSTR:
901 data += PrintOperands(idesc.mnem, idesc.op_order_, data);
904 case JUMP_CONDITIONAL_SHORT_INSTR:
905 data += JumpConditionalShort(data, branch_hint);
909 AppendToBuffer("%s %s", idesc.mnem, NameOfCPURegister(*data & 0x07));
913 case MOVE_REG_INSTR: {
914 byte* addr = reinterpret_cast<byte*>(*reinterpret_cast<int32_t*>(data+1));
915 AppendToBuffer("mov %s,%s",
916 NameOfCPURegister(*data & 0x07),
917 NameOfAddress(addr));
922 case CALL_JUMP_INSTR: {
923 byte* addr = data + *reinterpret_cast<int32_t*>(data+1) + 5;
924 AppendToBuffer("%s %s", idesc.mnem, NameOfAddress(addr));
929 case SHORT_IMMEDIATE_INSTR: {
930 byte* addr = reinterpret_cast<byte*>(*reinterpret_cast<int32_t*>(data+1));
931 AppendToBuffer("%s eax,%s", idesc.mnem, NameOfAddress(addr));
936 case BYTE_IMMEDIATE_INSTR: {
937 AppendToBuffer("%s al,0x%x", idesc.mnem, data[1]);
947 UNIMPLEMENTED(); // This type is not implemented.
949 //----------------------------
953 AppendToBuffer("ret 0x%x", *reinterpret_cast<uint16_t*>(data+1));
957 case 0x69: // fall through
959 { int mod, regop, rm;
960 get_modrm(*(data+1), &mod, ®op, &rm);
962 *data == 0x6B ? *(data+2) : *reinterpret_cast<int32_t*>(data+2);
963 AppendToBuffer("imul %s,%s,0x%x",
964 NameOfCPURegister(regop),
965 NameOfCPURegister(rm),
967 data += 2 + (*data == 0x6B ? 1 : 4);
974 get_modrm(*data, &mod, ®op, &rm);
976 AppendToBuffer("test_b ");
977 data += PrintRightByteOperand(data);
979 AppendToBuffer(",0x%x", imm);
982 UnimplementedInstruction();
987 case 0x81: // fall through
988 case 0x83: // 0x81 with sign extension bit set
989 data += PrintImmediateOp(data);
993 { byte f0byte = data[1];
994 const char* f0mnem = F0Mnem(f0byte);
995 if (f0byte == 0x18) {
998 get_modrm(*data, &mod, ®op, &rm);
999 const char* suffix[] = {"nta", "1", "2", "3"};
1000 AppendToBuffer("%s%s ", f0mnem, suffix[regop & 0x03]);
1001 data += PrintRightOperand(data);
1002 } else if (f0byte == 0x1F && data[2] == 0) {
1003 AppendToBuffer("nop"); // 3 byte nop.
1005 } else if (f0byte == 0x1F && data[2] == 0x40 && data[3] == 0) {
1006 AppendToBuffer("nop"); // 4 byte nop.
1008 } else if (f0byte == 0x1F && data[2] == 0x44 && data[3] == 0 &&
1010 AppendToBuffer("nop"); // 5 byte nop.
1012 } else if (f0byte == 0x1F && data[2] == 0x80 && data[3] == 0 &&
1013 data[4] == 0 && data[5] == 0 && data[6] == 0) {
1014 AppendToBuffer("nop"); // 7 byte nop.
1016 } else if (f0byte == 0x1F && data[2] == 0x84 && data[3] == 0 &&
1017 data[4] == 0 && data[5] == 0 && data[6] == 0 &&
1019 AppendToBuffer("nop"); // 8 byte nop.
1021 } else if (f0byte == 0xA2 || f0byte == 0x31) {
1022 AppendToBuffer("%s", f0mnem);
1024 } else if (f0byte == 0x28) {
1027 get_modrm(*data, &mod, ®op, &rm);
1028 AppendToBuffer("movaps %s,%s",
1029 NameOfXMMRegister(regop),
1030 NameOfXMMRegister(rm));
1032 } else if (f0byte == 0x10) {
1035 get_modrm(*data, &mod, ®op, &rm);
1036 AppendToBuffer("movups %s,", NameOfXMMRegister(regop));
1037 data += PrintRightXMMOperand(data);
1038 } else if (f0byte == 0x11) {
1039 AppendToBuffer("movups ");
1042 get_modrm(*data, &mod, ®op, &rm);
1043 data += PrintRightXMMOperand(data);
1044 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1045 } else if (f0byte >= 0x51 && f0byte <= 0x5F) {
1046 const char* const pseudo_op[] = {
1066 get_modrm(*data, &mod, ®op, &rm);
1067 AppendToBuffer("%s %s,",
1068 pseudo_op[f0byte - 0x51],
1069 NameOfXMMRegister(regop));
1070 data += PrintRightXMMOperand(data);
1071 } else if (f0byte == 0x50) {
1074 get_modrm(*data, &mod, ®op, &rm);
1075 AppendToBuffer("movmskps %s,%s",
1076 NameOfCPURegister(regop),
1077 NameOfXMMRegister(rm));
1079 } else if (f0byte == 0xC2) {
1080 // Intel manual 2A, Table 3-11.
1083 get_modrm(*data, &mod, ®op, &rm);
1084 const char* const pseudo_op[] = {
1094 AppendToBuffer("%s %s,%s",
1096 NameOfXMMRegister(regop),
1097 NameOfXMMRegister(rm));
1099 } else if (f0byte== 0xC6) {
1100 // shufps xmm, xmm/m128, imm8
1103 get_modrm(*data, &mod, ®op, &rm);
1104 int8_t imm8 = static_cast<int8_t>(data[1]);
1105 AppendToBuffer("shufps %s,%s,%d",
1106 NameOfXMMRegister(rm),
1107 NameOfXMMRegister(regop),
1108 static_cast<int>(imm8));
1110 } else if (f0byte== 0x5B) {
1113 get_modrm(*data, &mod, ®op, &rm);
1114 AppendToBuffer("cvtdq2ps %s,",
1115 NameOfXMMRegister(rm));
1116 data += PrintRightXMMOperand(data);
1117 } else if ((f0byte & 0xF0) == 0x80) {
1118 data += JumpConditional(data, branch_hint);
1119 } else if (f0byte == 0xBE || f0byte == 0xBF || f0byte == 0xB6 ||
1120 f0byte == 0xB7 || f0byte == 0xAF) {
1122 data += PrintOperands(f0mnem, REG_OPER_OP_ORDER, data);
1123 } else if ((f0byte & 0xF0) == 0x90) {
1124 data += SetCC(data);
1125 } else if ((f0byte & 0xF0) == 0x40) {
1127 } else if (f0byte == 0xAB || f0byte == 0xA5 || f0byte == 0xAD) {
1130 AppendToBuffer("%s ", f0mnem);
1132 get_modrm(*data, &mod, ®op, &rm);
1133 data += PrintRightOperand(data);
1134 if (f0byte == 0xAB) {
1135 AppendToBuffer(",%s", NameOfCPURegister(regop));
1137 AppendToBuffer(",%s,cl", NameOfCPURegister(regop));
1139 } else if (f0byte == 0xBD) {
1142 get_modrm(*data, &mod, ®op, &rm);
1143 AppendToBuffer("%s %s,", f0mnem, NameOfCPURegister(regop));
1144 data += PrintRightOperand(data);
1146 UnimplementedInstruction();
1154 get_modrm(*data, &mod, ®op, &rm);
1156 AppendToBuffer("pop ");
1157 data += PrintRightOperand(data);
1165 get_modrm(*data, &mod, ®op, &rm);
1166 const char* mnem = NULL;
1168 case esi: mnem = "push"; break;
1169 case eax: mnem = "inc"; break;
1170 case ecx: mnem = "dec"; break;
1171 case edx: mnem = "call"; break;
1172 case esp: mnem = "jmp"; break;
1173 default: mnem = "???";
1175 AppendToBuffer("%s ", mnem);
1176 data += PrintRightOperand(data);
1180 case 0xC7: // imm32, fall through
1182 { bool is_byte = *data == 0xC6;
1185 AppendToBuffer("%s ", "mov_b");
1186 data += PrintRightByteOperand(data);
1187 int32_t imm = *data;
1188 AppendToBuffer(",0x%x", imm);
1191 AppendToBuffer("%s ", "mov");
1192 data += PrintRightOperand(data);
1193 int32_t imm = *reinterpret_cast<int32_t*>(data);
1194 AppendToBuffer(",0x%x", imm);
1203 get_modrm(*data, &mod, ®op, &rm);
1204 const char* mnem = NULL;
1206 case 5: mnem = "subb"; break;
1207 case 7: mnem = "cmpb"; break;
1208 default: UnimplementedInstruction();
1210 AppendToBuffer("%s ", mnem);
1211 data += PrintRightByteOperand(data);
1212 int32_t imm = *data;
1213 AppendToBuffer(",0x%x", imm);
1218 case 0x88: // 8bit, fall through
1220 { bool is_byte = *data == 0x88;
1223 get_modrm(*data, &mod, ®op, &rm);
1225 AppendToBuffer("%s ", "mov_b");
1226 data += PrintRightByteOperand(data);
1227 AppendToBuffer(",%s", NameOfByteCPURegister(regop));
1229 AppendToBuffer("%s ", "mov");
1230 data += PrintRightOperand(data);
1231 AppendToBuffer(",%s", NameOfCPURegister(regop));
1236 case 0x66: // prefix
1237 while (*data == 0x66) data++;
1238 if (*data == 0xf && data[1] == 0x1f) {
1239 AppendToBuffer("nop"); // 0x66 prefix
1240 } else if (*data == 0x90) {
1241 AppendToBuffer("nop"); // 0x66 prefix
1242 } else if (*data == 0x8B) {
1244 data += PrintOperands("mov_w", REG_OPER_OP_ORDER, data);
1245 } else if (*data == 0x89) {
1248 get_modrm(*data, &mod, ®op, &rm);
1249 AppendToBuffer("mov_w ");
1250 data += PrintRightOperand(data);
1251 AppendToBuffer(",%s", NameOfCPURegister(regop));
1252 } else if (*data == 0xC7) {
1254 AppendToBuffer("%s ", "mov_w");
1255 data += PrintRightOperand(data);
1256 int imm = *reinterpret_cast<int16_t*>(data);
1257 AppendToBuffer(",0x%x", imm);
1259 } else if (*data == 0x0F) {
1261 if (*data == 0x38) {
1263 if (*data == 0x17) {
1266 get_modrm(*data, &mod, ®op, &rm);
1267 AppendToBuffer("ptest %s,%s",
1268 NameOfXMMRegister(regop),
1269 NameOfXMMRegister(rm));
1271 } else if (*data == 0x40) {
1274 get_modrm(*data, &mod, ®op, &rm);
1275 AppendToBuffer("pmulld %s,%s",
1276 NameOfXMMRegister(regop));
1277 data += PrintRightXMMOperand(data);
1278 } else if (*data == 0x2A) {
1282 get_modrm(*data, &mod, ®op, &rm);
1283 AppendToBuffer("movntdqa %s,", NameOfXMMRegister(regop));
1284 data += PrintRightOperand(data);
1286 UnimplementedInstruction();
1288 } else if (*data == 0x3A) {
1290 if (*data == 0x0B) {
1293 get_modrm(*data, &mod, ®op, &rm);
1294 int8_t imm8 = static_cast<int8_t>(data[1]);
1295 AppendToBuffer("roundsd %s,%s,%d",
1296 NameOfXMMRegister(regop),
1297 NameOfXMMRegister(rm),
1298 static_cast<int>(imm8));
1300 } else if (*data == 0x16) {
1303 get_modrm(*data, &mod, ®op, &rm);
1304 int8_t imm8 = static_cast<int8_t>(data[1]);
1305 AppendToBuffer("pextrd %s,%s,%d",
1306 NameOfCPURegister(regop),
1307 NameOfXMMRegister(rm),
1308 static_cast<int>(imm8));
1310 } else if (*data == 0x21) {
1313 get_modrm(*data, &mod, ®op, &rm);
1314 int8_t imm8 = static_cast<int8_t>(data[1]);
1315 AppendToBuffer("insertps %s,%s,%d",
1316 NameOfXMMRegister(regop),
1317 NameOfXMMRegister(rm),
1318 static_cast<int>(imm8));
1320 } else if (*data == 0x17) {
1323 get_modrm(*data, &mod, ®op, &rm);
1324 int8_t imm8 = static_cast<int8_t>(data[1]);
1325 AppendToBuffer("extractps %s,%s,%d",
1326 NameOfCPURegister(rm),
1327 NameOfXMMRegister(regop),
1328 static_cast<int>(imm8));
1330 } else if (*data == 0x22) {
1333 get_modrm(*data, &mod, ®op, &rm);
1334 int8_t imm8 = static_cast<int8_t>(data[1]);
1335 AppendToBuffer("pinsrd %s,%s,%d",
1336 NameOfXMMRegister(regop),
1337 NameOfCPURegister(rm),
1338 static_cast<int>(imm8));
1341 UnimplementedInstruction();
1343 } else if (*data == 0x2E || *data == 0x2F) {
1344 const char* mnem = (*data == 0x2E) ? "ucomisd" : "comisd";
1347 get_modrm(*data, &mod, ®op, &rm);
1349 AppendToBuffer("%s %s,%s", mnem,
1350 NameOfXMMRegister(regop),
1351 NameOfXMMRegister(rm));
1354 AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
1355 data += PrintRightOperand(data);
1357 } else if (*data == 0x50) {
1360 get_modrm(*data, &mod, ®op, &rm);
1361 AppendToBuffer("movmskpd %s,%s",
1362 NameOfCPURegister(regop),
1363 NameOfXMMRegister(rm));
1365 } else if (*data == 0x51) {
1368 get_modrm(*data, &mod, ®op, &rm);
1369 AppendToBuffer("sqrtpd %s,%s",
1370 NameOfXMMRegister(regop),
1371 NameOfXMMRegister(rm));
1373 } else if (*data == 0x54) {
1376 get_modrm(*data, &mod, ®op, &rm);
1377 AppendToBuffer("andpd %s,%s",
1378 NameOfXMMRegister(regop),
1379 NameOfXMMRegister(rm));
1381 } else if (*data == 0x56) {
1384 get_modrm(*data, &mod, ®op, &rm);
1385 AppendToBuffer("orpd %s,%s",
1386 NameOfXMMRegister(regop),
1387 NameOfXMMRegister(rm));
1389 } else if (*data == 0x57) {
1392 get_modrm(*data, &mod, ®op, &rm);
1393 AppendToBuffer("xorpd %s,",
1394 NameOfXMMRegister(regop));
1395 data += PrintRightXMMOperand(data);
1396 } else if (*data == 0x58) {
1399 get_modrm(*data, &mod, ®op, &rm);
1400 AppendToBuffer("addpd %s,",
1401 NameOfXMMRegister(regop));
1402 data += PrintRightXMMOperand(data);
1403 } else if (*data == 0x59) {
1406 get_modrm(*data, &mod, ®op, &rm);
1407 AppendToBuffer("mulpd %s,",
1408 NameOfXMMRegister(regop));
1409 data += PrintRightXMMOperand(data);
1410 } else if (*data == 0x5B) {
1413 get_modrm(*data, &mod, ®op, &rm);
1414 AppendToBuffer("cvtps2dq %s,",
1415 NameOfXMMRegister(regop));
1416 data += PrintRightXMMOperand(data);
1417 } else if (*data == 0x5C) {
1420 get_modrm(*data, &mod, ®op, &rm);
1421 AppendToBuffer("subpd %s,",
1422 NameOfXMMRegister(regop));
1423 data += PrintRightXMMOperand(data);
1424 } else if (*data == 0x5D) {
1427 get_modrm(*data, &mod, ®op, &rm);
1428 AppendToBuffer("minpd %s,",
1429 NameOfXMMRegister(regop));
1430 data += PrintRightXMMOperand(data);
1431 } else if (*data == 0x5E) {
1434 get_modrm(*data, &mod, ®op, &rm);
1435 AppendToBuffer("divpd %s,",
1436 NameOfXMMRegister(regop));
1437 data += PrintRightXMMOperand(data);
1438 } else if (*data == 0x5F) {
1441 get_modrm(*data, &mod, ®op, &rm);
1442 AppendToBuffer("maxpd %s,",
1443 NameOfXMMRegister(regop));
1444 data += PrintRightXMMOperand(data);
1445 } else if (*data == 0x62) {
1448 get_modrm(*data, &mod, ®op, &rm);
1449 AppendToBuffer("punpackldq %s,",
1450 NameOfXMMRegister(regop));
1451 data += PrintRightXMMOperand(data);
1452 } else if (*data == 0xF4) {
1455 get_modrm(*data, &mod, ®op, &rm);
1456 AppendToBuffer("pmuludq %s,",
1457 NameOfXMMRegister(regop));
1458 data += PrintRightXMMOperand(data);
1459 } else if (*data == 0xFA) {
1462 get_modrm(*data, &mod, ®op, &rm);
1463 AppendToBuffer("psubd %s,",
1464 NameOfXMMRegister(regop));
1465 data += PrintRightXMMOperand(data);
1466 } else if (*data == 0xFE) {
1469 get_modrm(*data, &mod, ®op, &rm);
1470 AppendToBuffer("paddd %s,",
1471 NameOfXMMRegister(regop));
1472 data += PrintRightXMMOperand(data);
1473 } else if (*data == 0x6E) {
1476 get_modrm(*data, &mod, ®op, &rm);
1477 AppendToBuffer("movd %s,", NameOfXMMRegister(regop));
1478 data += PrintRightOperand(data);
1479 } else if (*data == 0x6F) {
1482 get_modrm(*data, &mod, ®op, &rm);
1483 AppendToBuffer("movdqa %s,", NameOfXMMRegister(regop));
1484 data += PrintRightXMMOperand(data);
1485 } else if (*data == 0x70) {
1488 get_modrm(*data, &mod, ®op, &rm);
1489 int8_t imm8 = static_cast<int8_t>(data[1]);
1490 AppendToBuffer("pshufd %s,%s,%d",
1491 NameOfXMMRegister(regop),
1492 NameOfXMMRegister(rm),
1493 static_cast<int>(imm8));
1495 } else if (*data == 0x66) {
1498 get_modrm(*data, &mod, ®op, &rm);
1499 AppendToBuffer("pcmpgtd %s,%s",
1500 NameOfXMMRegister(regop),
1501 NameOfXMMRegister(rm));
1503 } else if (*data == 0x76) {
1506 get_modrm(*data, &mod, ®op, &rm);
1507 AppendToBuffer("pcmpeqd %s,%s",
1508 NameOfXMMRegister(regop),
1509 NameOfXMMRegister(rm));
1511 } else if (*data == 0x90) {
1513 AppendToBuffer("nop"); // 2 byte nop.
1514 } else if (*data == 0xF3) {
1517 get_modrm(*data, &mod, ®op, &rm);
1518 AppendToBuffer("psllq %s,%s",
1519 NameOfXMMRegister(regop),
1520 NameOfXMMRegister(rm));
1522 } else if (*data == 0x73) {
1525 get_modrm(*data, &mod, ®op, &rm);
1526 int8_t imm8 = static_cast<int8_t>(data[1]);
1527 ASSERT(regop == esi || regop == edx);
1528 AppendToBuffer("%s %s,%d",
1529 (regop == esi) ? "psllq" : "psrlq",
1530 NameOfXMMRegister(rm),
1531 static_cast<int>(imm8));
1533 } else if (*data == 0xF2) {
1536 get_modrm(*data, &mod, ®op, &rm);
1537 AppendToBuffer("pslld %s,%s",
1538 NameOfXMMRegister(regop),
1539 NameOfXMMRegister(rm));
1541 } else if (*data == 0x72) {
1544 get_modrm(*data, &mod, ®op, &rm);
1545 int8_t imm8 = static_cast<int8_t>(data[1]);
1546 ASSERT(regop == esi || regop == edx);
1547 AppendToBuffer("%s %s,%d",
1548 (regop == esi) ? "pslld"
1549 : ((regop == edx) ? "psrld" : "psrad"),
1550 NameOfXMMRegister(rm),
1551 static_cast<int>(imm8));
1553 } else if (*data == 0xC6) {
1556 get_modrm(*data, &mod, ®op, &rm);
1557 int8_t imm8 = static_cast<int8_t>(data[1]);
1558 AppendToBuffer("shufpd %s,%s,%d",
1559 NameOfXMMRegister(regop),
1560 NameOfXMMRegister(rm),
1561 static_cast<int>(imm8));
1563 } else if (*data == 0xD2) {
1566 get_modrm(*data, &mod, ®op, &rm);
1567 AppendToBuffer("psrld %s,%s",
1568 NameOfXMMRegister(regop),
1569 NameOfXMMRegister(rm));
1571 } else if (*data == 0xD3) {
1574 get_modrm(*data, &mod, ®op, &rm);
1575 AppendToBuffer("psrlq %s,%s",
1576 NameOfXMMRegister(regop),
1577 NameOfXMMRegister(rm));
1579 } else if (*data == 0xE2) {
1582 get_modrm(*data, &mod, ®op, &rm);
1583 AppendToBuffer("psrad %s,%s",
1584 NameOfXMMRegister(regop),
1585 NameOfXMMRegister(rm));
1587 } else if (*data == 0x7F) {
1588 AppendToBuffer("movdqa ");
1591 get_modrm(*data, &mod, ®op, &rm);
1592 data += PrintRightXMMOperand(data);
1593 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1594 } else if (*data == 0x7E) {
1597 get_modrm(*data, &mod, ®op, &rm);
1598 AppendToBuffer("movd ");
1599 data += PrintRightOperand(data);
1600 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1601 } else if (*data == 0xDB) {
1604 get_modrm(*data, &mod, ®op, &rm);
1605 AppendToBuffer("pand %s,%s",
1606 NameOfXMMRegister(regop),
1607 NameOfXMMRegister(rm));
1609 } else if (*data == 0xE7) {
1612 get_modrm(*data, &mod, ®op, &rm);
1614 AppendToBuffer("movntdq ");
1615 data += PrintRightOperand(data);
1616 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1618 UnimplementedInstruction();
1620 } else if (*data == 0xEF) {
1623 get_modrm(*data, &mod, ®op, &rm);
1624 AppendToBuffer("pxor %s,%s",
1625 NameOfXMMRegister(regop),
1626 NameOfXMMRegister(rm));
1628 } else if (*data == 0xEB) {
1631 get_modrm(*data, &mod, ®op, &rm);
1632 AppendToBuffer("por %s,%s",
1633 NameOfXMMRegister(regop),
1634 NameOfXMMRegister(rm));
1637 UnimplementedInstruction();
1640 UnimplementedInstruction();
1647 get_modrm(*data, &mod, ®op, &rm);
1649 AppendToBuffer("dec_b ");
1650 data += PrintRightOperand(data);
1652 UnimplementedInstruction();
1658 AppendToBuffer("push 0x%x", *reinterpret_cast<int32_t*>(data+1));
1663 AppendToBuffer("push 0x%x", *reinterpret_cast<int8_t*>(data + 1));
1668 AppendToBuffer("test al,0x%x", *reinterpret_cast<uint8_t*>(data+1));
1673 AppendToBuffer("test eax,0x%x", *reinterpret_cast<int32_t*>(data+1));
1677 case 0xD1: // fall through
1678 case 0xD3: // fall through
1680 data += D1D3C1Instruction(data);
1683 case 0xD8: // fall through
1684 case 0xD9: // fall through
1685 case 0xDA: // fall through
1686 case 0xDB: // fall through
1687 case 0xDC: // fall through
1688 case 0xDD: // fall through
1689 case 0xDE: // fall through
1691 data += FPUInstruction(data);
1695 data += JumpShort(data);
1699 if (*(data+1) == 0x0F) {
1700 byte b2 = *(data+2);
1702 AppendToBuffer("movsd ");
1705 get_modrm(*data, &mod, ®op, &rm);
1706 data += PrintRightXMMOperand(data);
1707 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1708 } else if (b2 == 0x10) {
1711 get_modrm(*data, &mod, ®op, &rm);
1712 AppendToBuffer("movsd %s,", NameOfXMMRegister(regop));
1713 data += PrintRightXMMOperand(data);
1714 } else if (b2 == 0x5A) {
1717 get_modrm(*data, &mod, ®op, &rm);
1718 AppendToBuffer("cvtsd2ss %s,", NameOfXMMRegister(regop));
1719 data += PrintRightXMMOperand(data);
1721 const char* mnem = "?";
1723 case 0x2A: mnem = "cvtsi2sd"; break;
1724 case 0x2C: mnem = "cvttsd2si"; break;
1725 case 0x2D: mnem = "cvtsd2si"; break;
1726 case 0x51: mnem = "sqrtsd"; break;
1727 case 0x58: mnem = "addsd"; break;
1728 case 0x59: mnem = "mulsd"; break;
1729 case 0x5C: mnem = "subsd"; break;
1730 case 0x5E: mnem = "divsd"; break;
1734 get_modrm(*data, &mod, ®op, &rm);
1736 AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
1737 data += PrintRightOperand(data);
1738 } else if (b2 == 0x2C || b2 == 0x2D) {
1739 AppendToBuffer("%s %s,", mnem, NameOfCPURegister(regop));
1740 data += PrintRightXMMOperand(data);
1741 } else if (b2 == 0xC2) {
1742 // Intel manual 2A, Table 3-18.
1743 const char* const pseudo_op[] = {
1753 AppendToBuffer("%s %s,%s",
1755 NameOfXMMRegister(regop),
1756 NameOfXMMRegister(rm));
1759 AppendToBuffer("%s %s,", mnem, NameOfXMMRegister(regop));
1760 data += PrintRightXMMOperand(data);
1764 UnimplementedInstruction();
1769 if (*(data+1) == 0x0F) {
1770 byte b2 = *(data+2);
1772 AppendToBuffer("movss ");
1775 get_modrm(*data, &mod, ®op, &rm);
1776 data += PrintRightXMMOperand(data);
1777 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1778 } else if (b2 == 0x10) {
1781 get_modrm(*data, &mod, ®op, &rm);
1782 AppendToBuffer("movss %s,", NameOfXMMRegister(regop));
1783 data += PrintRightXMMOperand(data);
1784 } else if (b2 == 0x2C) {
1787 get_modrm(*data, &mod, ®op, &rm);
1788 AppendToBuffer("cvttss2si %s,", NameOfCPURegister(regop));
1789 data += PrintRightXMMOperand(data);
1790 } else if (b2 == 0x5A) {
1793 get_modrm(*data, &mod, ®op, &rm);
1794 AppendToBuffer("cvtss2sd %s,", NameOfXMMRegister(regop));
1795 data += PrintRightXMMOperand(data);
1796 } else if (b2 == 0x6F) {
1799 get_modrm(*data, &mod, ®op, &rm);
1800 AppendToBuffer("movdqu %s,", NameOfXMMRegister(regop));
1801 data += PrintRightXMMOperand(data);
1802 } else if (b2 == 0x7F) {
1803 AppendToBuffer("movdqu ");
1806 get_modrm(*data, &mod, ®op, &rm);
1807 data += PrintRightXMMOperand(data);
1808 AppendToBuffer(",%s", NameOfXMMRegister(regop));
1810 UnimplementedInstruction();
1812 } else if (*(data+1) == 0xA5) {
1814 AppendToBuffer("rep_movs");
1815 } else if (*(data+1) == 0xAB) {
1817 AppendToBuffer("rep_stos");
1819 UnimplementedInstruction();
1824 data += F7Instruction(data);
1828 UnimplementedInstruction();
1832 if (tmp_buffer_pos_ < sizeof tmp_buffer_) {
1833 tmp_buffer_[tmp_buffer_pos_] = '\0';
1836 int instr_len = data - instr;
1837 if (instr_len == 0) {
1838 printf("%02x", *data);
1840 ASSERT(instr_len > 0); // Ensure progress.
1843 // Instruction bytes.
1844 for (byte* bp = instr; bp < data; bp++) {
1845 outp += v8::internal::OS::SNPrintF(out_buffer + outp,
1849 for (int i = 6 - instr_len; i >= 0; i--) {
1850 outp += v8::internal::OS::SNPrintF(out_buffer + outp,
1854 outp += v8::internal::OS::SNPrintF(out_buffer + outp,
1856 tmp_buffer_.start());
1858 } // NOLINT (function is too long)
1861 //------------------------------------------------------------------------------
1864 static const char* cpu_regs[8] = {
1865 "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi"
1869 static const char* byte_cpu_regs[8] = {
1870 "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh"
1874 static const char* xmm_regs[8] = {
1875 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7"
1879 const char* NameConverter::NameOfAddress(byte* addr) const {
1880 v8::internal::OS::SNPrintF(tmp_buffer_, "%p", addr);
1881 return tmp_buffer_.start();
1885 const char* NameConverter::NameOfConstant(byte* addr) const {
1886 return NameOfAddress(addr);
1890 const char* NameConverter::NameOfCPURegister(int reg) const {
1891 if (0 <= reg && reg < 8) return cpu_regs[reg];
1896 const char* NameConverter::NameOfByteCPURegister(int reg) const {
1897 if (0 <= reg && reg < 8) return byte_cpu_regs[reg];
1902 const char* NameConverter::NameOfXMMRegister(int reg) const {
1903 if (0 <= reg && reg < 8) return xmm_regs[reg];
1908 const char* NameConverter::NameInCode(byte* addr) const {
1909 // IA32 does not embed debug strings at the moment.
1915 //------------------------------------------------------------------------------
1917 Disassembler::Disassembler(const NameConverter& converter)
1918 : converter_(converter) {}
1921 Disassembler::~Disassembler() {}
1924 int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer,
1925 byte* instruction) {
1926 DisassemblerIA32 d(converter_, false /*do not crash if unimplemented*/);
1927 return d.InstructionDecode(buffer, instruction);
1931 // The IA-32 assembler does not currently use constant pools.
1932 int Disassembler::ConstantPoolSizeAt(byte* instruction) { return -1; }
1935 /*static*/ void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) {
1936 NameConverter converter;
1937 Disassembler d(converter);
1938 for (byte* pc = begin; pc < end;) {
1939 v8::internal::EmbeddedVector<char, 128> buffer;
1942 pc += d.InstructionDecode(buffer, pc);
1943 fprintf(f, "%p", prev_pc);
1946 for (byte* bp = prev_pc; bp < pc; bp++) {
1947 fprintf(f, "%02x", *bp);
1949 for (int i = 6 - (pc - prev_pc); i >= 0; i--) {
1952 fprintf(f, " %s\n", buffer.start());
1957 } // namespace disasm
1959 #endif // V8_TARGET_ARCH_IA32