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31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2011 the V8 project authors. All rights reserved.
35 // A light-weight IA32 Assembler.
37 #ifndef V8_IA32_ASSEMBLER_IA32_H_
38 #define V8_IA32_ASSEMBLER_IA32_H_
41 #include "serialize.h"
48 // 1) We would prefer to use an enum, but enum values are assignment-
49 // compatible with int, which has caused code-generation bugs.
51 // 2) We would prefer to use a class instead of a struct but we don't like
52 // the register initialization to depend on the particular initialization
53 // order (which appears to be different on OS X, Linux, and Windows for the
54 // installed versions of C++ we tried). Using a struct permits C-style
55 // "initialization". Also, the Register objects cannot be const as this
56 // forces initialization stubs in MSVC, making us dependent on initialization
59 // 3) By not using an enum, we are possibly preventing the compiler from
60 // doing certain constant folds, which may significantly reduce the
61 // code generated for some assembly instructions (because they boil down
62 // to a few constants). If this is a problem, we could change the code
63 // such that we use an enum in optimized mode, and the struct in debug
64 // mode. This way we get the compile-time error checking in debug mode
65 // and best performance in optimized code.
68 static const int kMaxNumAllocatableRegisters = 6;
69 static int NumAllocatableRegisters() {
70 return kMaxNumAllocatableRegisters;
72 static const int kNumRegisters = 8;
74 static inline const char* AllocationIndexToString(int index);
76 static inline int ToAllocationIndex(Register reg);
78 static inline Register FromAllocationIndex(int index);
80 static Register from_code(int code) {
82 ASSERT(code < kNumRegisters);
83 Register r = { code };
86 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
87 bool is(Register reg) const { return code_ == reg.code_; }
88 // eax, ebx, ecx and edx are byte registers, the rest are not.
89 bool is_byte_register() const { return code_ <= 3; }
99 // Unfortunately we can't make this private in a struct.
103 const int kRegister_eax_Code = 0;
104 const int kRegister_ecx_Code = 1;
105 const int kRegister_edx_Code = 2;
106 const int kRegister_ebx_Code = 3;
107 const int kRegister_esp_Code = 4;
108 const int kRegister_ebp_Code = 5;
109 const int kRegister_esi_Code = 6;
110 const int kRegister_edi_Code = 7;
111 const int kRegister_no_reg_Code = -1;
113 const Register eax = { kRegister_eax_Code };
114 const Register ecx = { kRegister_ecx_Code };
115 const Register edx = { kRegister_edx_Code };
116 const Register ebx = { kRegister_ebx_Code };
117 const Register esp = { kRegister_esp_Code };
118 const Register ebp = { kRegister_ebp_Code };
119 const Register esi = { kRegister_esi_Code };
120 const Register edi = { kRegister_edi_Code };
121 const Register no_reg = { kRegister_no_reg_Code };
124 inline const char* Register::AllocationIndexToString(int index) {
125 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
126 // This is the mapping of allocation indices to registers.
127 const char* const kNames[] = { "eax", "ecx", "edx", "ebx", "esi", "edi" };
128 return kNames[index];
132 inline int Register::ToAllocationIndex(Register reg) {
133 ASSERT(reg.is_valid() && !reg.is(esp) && !reg.is(ebp));
134 return (reg.code() >= 6) ? reg.code() - 2 : reg.code();
138 inline Register Register::FromAllocationIndex(int index) {
139 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
140 return (index >= 4) ? from_code(index + 2) : from_code(index);
144 struct IntelDoubleRegister {
145 static const int kMaxNumRegisters = 8;
146 static const int kMaxNumAllocatableRegisters = 7;
147 static int NumAllocatableRegisters();
148 static int NumRegisters();
149 static const char* AllocationIndexToString(int index);
151 static int ToAllocationIndex(IntelDoubleRegister reg) {
152 ASSERT(reg.code() != 0);
153 return reg.code() - 1;
156 static IntelDoubleRegister FromAllocationIndex(int index) {
157 ASSERT(index >= 0 && index < NumAllocatableRegisters());
158 return from_code(index + 1);
161 static IntelDoubleRegister from_code(int code) {
162 IntelDoubleRegister result = { code };
166 bool is_valid() const {
167 return 0 <= code_ && code_ < NumRegisters();
178 const IntelDoubleRegister double_register_0 = { 0 };
179 const IntelDoubleRegister double_register_1 = { 1 };
180 const IntelDoubleRegister double_register_2 = { 2 };
181 const IntelDoubleRegister double_register_3 = { 3 };
182 const IntelDoubleRegister double_register_4 = { 4 };
183 const IntelDoubleRegister double_register_5 = { 5 };
184 const IntelDoubleRegister double_register_6 = { 6 };
185 const IntelDoubleRegister double_register_7 = { 7 };
186 const IntelDoubleRegister no_double_reg = { -1 };
189 struct XMMRegister : IntelDoubleRegister {
190 static const int kNumAllocatableRegisters = 7;
191 static const int kNumRegisters = 8;
193 static XMMRegister from_code(int code) {
194 STATIC_ASSERT(sizeof(XMMRegister) == sizeof(IntelDoubleRegister));
200 bool is(XMMRegister reg) const { return code_ == reg.code_; }
202 static XMMRegister FromAllocationIndex(int index) {
203 ASSERT(index >= 0 && index < NumAllocatableRegisters());
204 return from_code(index + 1);
207 static const char* AllocationIndexToString(int index) {
208 ASSERT(index >= 0 && index < kNumAllocatableRegisters);
209 const char* const names[] = {
223 typedef XMMRegister SIMD128Register;
226 #define xmm0 (static_cast<const XMMRegister&>(double_register_0))
227 #define xmm1 (static_cast<const XMMRegister&>(double_register_1))
228 #define xmm2 (static_cast<const XMMRegister&>(double_register_2))
229 #define xmm3 (static_cast<const XMMRegister&>(double_register_3))
230 #define xmm4 (static_cast<const XMMRegister&>(double_register_4))
231 #define xmm5 (static_cast<const XMMRegister&>(double_register_5))
232 #define xmm6 (static_cast<const XMMRegister&>(double_register_6))
233 #define xmm7 (static_cast<const XMMRegister&>(double_register_7))
234 #define no_xmm_reg (static_cast<const XMMRegister&>(no_double_reg))
237 struct X87Register : IntelDoubleRegister {
238 static const int kNumAllocatableRegisters = 5;
239 static const int kNumRegisters = 5;
241 bool is(X87Register reg) const {
242 return code_ == reg.code_;
245 static const char* AllocationIndexToString(int index) {
246 ASSERT(index >= 0 && index < kNumAllocatableRegisters);
247 const char* const names[] = {
248 "stX_0", "stX_1", "stX_2", "stX_3", "stX_4"
253 static X87Register FromAllocationIndex(int index) {
254 STATIC_ASSERT(sizeof(X87Register) == sizeof(IntelDoubleRegister));
255 ASSERT(index >= 0 && index < NumAllocatableRegisters());
257 result.code_ = index;
261 static int ToAllocationIndex(X87Register reg) {
266 #define stX_0 static_cast<const X87Register&>(double_register_0)
267 #define stX_1 static_cast<const X87Register&>(double_register_1)
268 #define stX_2 static_cast<const X87Register&>(double_register_2)
269 #define stX_3 static_cast<const X87Register&>(double_register_3)
270 #define stX_4 static_cast<const X87Register&>(double_register_4)
273 typedef IntelDoubleRegister DoubleRegister;
277 // any value < 0 is considered no_condition
299 not_carry = above_equal,
301 not_zero = not_equal,
307 // Returns the equivalent of !cc.
308 // Negation of the default no_condition (-1) results in a non-default
309 // no_condition value (-2). As long as tests for no_condition check
310 // for condition < 0, this will work as expected.
311 inline Condition NegateCondition(Condition cc) {
312 return static_cast<Condition>(cc ^ 1);
316 // Corresponds to transposing the operands of a comparison.
317 inline Condition ReverseCondition(Condition cc) {
334 return greater_equal;
341 // -----------------------------------------------------------------------------
342 // Machine instruction Immediates
344 class Immediate BASE_EMBEDDED {
346 inline explicit Immediate(int x);
347 inline explicit Immediate(const ExternalReference& ext);
348 inline explicit Immediate(Handle<Object> handle);
349 inline explicit Immediate(Smi* value);
350 inline explicit Immediate(Address addr);
352 static Immediate CodeRelativeOffset(Label* label) {
353 return Immediate(label);
356 bool is_zero() const { return x_ == 0 && RelocInfo::IsNone(rmode_); }
357 bool is_int8() const {
358 return -128 <= x_ && x_ < 128 && RelocInfo::IsNone(rmode_);
360 bool is_int16() const {
361 return -32768 <= x_ && x_ < 32768 && RelocInfo::IsNone(rmode_);
365 inline explicit Immediate(Label* value);
368 RelocInfo::Mode rmode_;
370 friend class Assembler;
371 friend class MacroAssembler;
375 // -----------------------------------------------------------------------------
376 // Machine instruction Operands
383 maximal_scale_factor = times_8,
384 times_int_size = times_4,
385 times_half_pointer_size = times_2,
386 times_pointer_size = times_4,
387 times_twice_pointer_size = times_8
391 class Operand BASE_EMBEDDED {
394 INLINE(explicit Operand(XMMRegister xmm_reg));
397 INLINE(explicit Operand(int32_t disp, RelocInfo::Mode rmode));
398 // disp only must always be relocated
401 explicit Operand(Register base, int32_t disp,
402 RelocInfo::Mode rmode = RelocInfo::NONE32);
404 // [base + index*scale + disp/r]
405 explicit Operand(Register base,
409 RelocInfo::Mode rmode = RelocInfo::NONE32);
411 // [index*scale + disp/r]
412 explicit Operand(Register index,
415 RelocInfo::Mode rmode = RelocInfo::NONE32);
417 // Offset from existing memory operand.
418 // Offset is added to existing displacement as 32-bit signed values and
419 // this must not overflow.
420 Operand(const Operand& base, int32_t offset);
422 static Operand StaticVariable(const ExternalReference& ext) {
423 return Operand(reinterpret_cast<int32_t>(ext.address()),
424 RelocInfo::EXTERNAL_REFERENCE);
427 static Operand StaticArray(Register index,
429 const ExternalReference& arr) {
430 return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()),
431 RelocInfo::EXTERNAL_REFERENCE);
434 static Operand ForCell(Handle<Cell> cell) {
435 AllowDeferredHandleDereference embedding_raw_address;
436 return Operand(reinterpret_cast<int32_t>(cell.location()),
440 // Returns true if this Operand is a wrapper for the specified register.
441 bool is_reg(Register reg) const;
443 // Returns true if this Operand is a wrapper for one register.
444 bool is_reg_only() const;
446 // Asserts that this Operand is a wrapper for one register and returns the
448 Register reg() const;
452 INLINE(explicit Operand(Register reg));
454 // Set the ModRM byte without an encoded 'reg' register. The
455 // register is encoded later as part of the emit_operand operation.
456 inline void set_modrm(int mod, Register rm);
458 inline void set_sib(ScaleFactor scale, Register index, Register base);
459 inline void set_disp8(int8_t disp);
460 inline void set_dispr(int32_t disp, RelocInfo::Mode rmode);
463 // The number of bytes in buf_.
465 // Only valid if len_ > 4.
466 RelocInfo::Mode rmode_;
468 friend class Assembler;
469 friend class MacroAssembler;
470 friend class LCodeGen;
474 // -----------------------------------------------------------------------------
475 // A Displacement describes the 32bit immediate field of an instruction which
476 // may be used together with a Label in order to refer to a yet unknown code
477 // position. Displacements stored in the instruction stream are used to describe
478 // the instruction and to chain a list of instructions using the same Label.
479 // A Displacement contains 2 different fields:
481 // next field: position of next displacement in the chain (0 = end of list)
482 // type field: instruction type
484 // A next value of null (0) indicates the end of a chain (note that there can
485 // be no displacement at position zero, because there is always at least one
486 // instruction byte before the displacement).
488 // Displacement _data field layout
490 // |31.....2|1......0|
493 class Displacement BASE_EMBEDDED {
501 int data() const { return data_; }
502 Type type() const { return TypeField::decode(data_); }
503 void next(Label* L) const {
504 int n = NextField::decode(data_);
505 n > 0 ? L->link_to(n) : L->Unuse();
507 void link_to(Label* L) { init(L, type()); }
509 explicit Displacement(int data) { data_ = data; }
511 Displacement(Label* L, Type type) { init(L, type); }
514 PrintF("%s (%x) ", (type() == UNCONDITIONAL_JUMP ? "jmp" : "[other]"),
515 NextField::decode(data_));
521 class TypeField: public BitField<Type, 0, 2> {};
522 class NextField: public BitField<int, 2, 32-2> {};
524 void init(Label* L, Type type);
529 // CpuFeatures keeps track of which features are supported by the target CPU.
530 // Supported features must be enabled by a CpuFeatureScope before use.
532 // if (assembler->IsSupported(SSE2)) {
533 // CpuFeatureScope fscope(assembler, SSE2);
534 // // Generate SSE2 floating point code.
536 // // Generate standard x87 floating point code.
538 class CpuFeatures : public AllStatic {
540 // Detect features of the target CPU. Set safe defaults if the serializer
541 // is enabled (snapshots must be portable).
544 // Check whether a feature is supported by the target CPU.
545 static bool IsSupported(CpuFeature f) {
546 ASSERT(initialized_);
547 if (Check(f, cross_compile_)) return true;
548 if (f == SSE2 && !FLAG_enable_sse2) return false;
549 if (f == SSE3 && !FLAG_enable_sse3) return false;
550 if (f == SSE4_1 && !FLAG_enable_sse4_1) return false;
551 if (f == CMOV && !FLAG_enable_cmov) return false;
552 return Check(f, supported_);
555 static bool IsFoundByRuntimeProbingOnly(CpuFeature f) {
556 ASSERT(initialized_);
557 return Check(f, found_by_runtime_probing_only_);
560 static bool IsSafeForSnapshot(CpuFeature f) {
561 return Check(f, cross_compile_) ||
563 (!Serializer::enabled() || !IsFoundByRuntimeProbingOnly(f)));
566 static bool VerifyCrossCompiling() {
567 return cross_compile_ == 0;
570 static bool VerifyCrossCompiling(CpuFeature f) {
571 uint64_t mask = flag2set(f);
572 return cross_compile_ == 0 ||
573 (cross_compile_ & mask) == mask;
577 static bool Check(CpuFeature f, uint64_t set) {
578 return (set & flag2set(f)) != 0;
581 static uint64_t flag2set(CpuFeature f) {
582 return static_cast<uint64_t>(1) << f;
586 static bool initialized_;
588 static uint64_t supported_;
589 static uint64_t found_by_runtime_probing_only_;
591 static uint64_t cross_compile_;
593 friend class ExternalReference;
594 friend class PlatformFeatureScope;
595 DISALLOW_COPY_AND_ASSIGN(CpuFeatures);
599 class Assembler : public AssemblerBase {
601 // We check before assembling an instruction that there is sufficient
602 // space to write an instruction and its relocation information.
603 // The relocation writer's position must be kGap bytes above the end of
604 // the generated instructions. This leaves enough space for the
605 // longest possible ia32 instruction, 15 bytes, and the longest possible
606 // relocation information encoding, RelocInfoWriter::kMaxLength == 16.
607 // (There is a 15 byte limit on ia32 instruction length that rules out some
608 // otherwise valid instructions.)
609 // This allows for a single, fast space check per instruction.
610 static const int kGap = 32;
613 // Create an assembler. Instructions and relocation information are emitted
614 // into a buffer, with the instructions starting from the beginning and the
615 // relocation information starting from the end of the buffer. See CodeDesc
616 // for a detailed comment on the layout (globals.h).
618 // If the provided buffer is NULL, the assembler allocates and grows its own
619 // buffer, and buffer_size determines the initial buffer size. The buffer is
620 // owned by the assembler and deallocated upon destruction of the assembler.
622 // If the provided buffer is not NULL, the assembler uses the provided buffer
623 // for code generation and assumes its size to be buffer_size. If the buffer
624 // is too small, a fatal error occurs. No deallocation of the buffer is done
625 // upon destruction of the assembler.
626 // TODO(vitalyr): the assembler does not need an isolate.
627 Assembler(Isolate* isolate, void* buffer, int buffer_size);
628 virtual ~Assembler() { }
630 // GetCode emits any pending (non-emitted) code and fills the descriptor
631 // desc. GetCode() is idempotent; it returns the same result if no other
632 // Assembler functions are invoked in between GetCode() calls.
633 void GetCode(CodeDesc* desc);
635 // Read/Modify the code target in the branch/call instruction at pc.
636 inline static Address target_address_at(Address pc);
637 inline static void set_target_address_at(Address pc, Address target);
639 // Return the code target address at a call site from the return address
640 // of that call in the instruction stream.
641 inline static Address target_address_from_return_address(Address pc);
643 // This sets the branch destination (which is in the instruction on x86).
644 // This is for calls and branches within generated code.
645 inline static void deserialization_set_special_target_at(
646 Address instruction_payload, Address target) {
647 set_target_address_at(instruction_payload, target);
650 static const int kSpecialTargetSize = kPointerSize;
652 // Distance between the address of the code target in the call instruction
653 // and the return address
654 static const int kCallTargetAddressOffset = kPointerSize;
655 // Distance between start of patched return sequence and the emitted address
657 static const int kPatchReturnSequenceAddressOffset = 1; // JMP imm32.
659 // Distance between start of patched debug break slot and the emitted address
661 static const int kPatchDebugBreakSlotAddressOffset = 1; // JMP imm32.
663 static const int kCallInstructionLength = 5;
664 static const int kPatchDebugBreakSlotReturnOffset = kPointerSize;
665 static const int kJSReturnSequenceLength = 6;
667 // The debug break slot must be able to contain a call instruction.
668 static const int kDebugBreakSlotLength = kCallInstructionLength;
670 // One byte opcode for test al, 0xXX.
671 static const byte kTestAlByte = 0xA8;
672 // One byte opcode for nop.
673 static const byte kNopByte = 0x90;
675 // One byte opcode for a short unconditional jump.
676 static const byte kJmpShortOpcode = 0xEB;
677 // One byte prefix for a short conditional jump.
678 static const byte kJccShortPrefix = 0x70;
679 static const byte kJncShortOpcode = kJccShortPrefix | not_carry;
680 static const byte kJcShortOpcode = kJccShortPrefix | carry;
681 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero;
682 static const byte kJzShortOpcode = kJccShortPrefix | zero;
685 // ---------------------------------------------------------------------------
688 // - function names correspond one-to-one to ia32 instruction mnemonics
689 // - unless specified otherwise, instructions operate on 32bit operands
690 // - instructions on 8bit (byte) operands/registers have a trailing '_b'
691 // - instructions on 16bit (word) operands/registers have a trailing '_w'
692 // - naming conflicts with C++ keywords are resolved via a trailing '_'
694 // NOTE ON INTERFACE: Currently, the interface is not very consistent
695 // in the sense that some operations (e.g. mov()) can be called in more
696 // the one way to generate the same instruction: The Register argument
697 // can in some cases be replaced with an Operand(Register) argument.
698 // This should be cleaned up and made more orthogonal. The questions
699 // is: should we always use Operands instead of Registers where an
700 // Operand is possible, or should we have a Register (overloaded) form
701 // instead? We must be careful to make sure that the selected instruction
702 // is obvious from the parameters to avoid hard-to-find code generation
705 // Insert the smallest number of nop instructions
706 // possible to align the pc offset to a multiple
707 // of m. m must be a power of 2.
709 void Nop(int bytes = 1);
710 // Aligns code to something that's optimal for a jump target for the platform.
711 void CodeTargetAlign();
720 void push(const Immediate& x);
721 void push_imm32(int32_t imm32);
722 void push(Register src);
723 void push(const Operand& src);
725 void pop(Register dst);
726 void pop(const Operand& dst);
728 void enter(const Immediate& size);
732 void mov_b(Register dst, Register src) { mov_b(dst, Operand(src)); }
733 void mov_b(Register dst, const Operand& src);
734 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); }
735 void mov_b(const Operand& dst, int8_t imm8);
736 void mov_b(const Operand& dst, Register src);
738 void mov_w(Register dst, const Operand& src);
739 void mov_w(const Operand& dst, Register src);
740 void mov_w(const Operand& dst, int16_t imm16);
742 void mov(Register dst, int32_t imm32);
743 void mov(Register dst, const Immediate& x);
744 void mov(Register dst, Handle<Object> handle);
745 void mov(Register dst, const Operand& src);
746 void mov(Register dst, Register src);
747 void mov(const Operand& dst, const Immediate& x);
748 void mov(const Operand& dst, Handle<Object> handle);
749 void mov(const Operand& dst, Register src);
751 void movsx_b(Register dst, Register src) { movsx_b(dst, Operand(src)); }
752 void movsx_b(Register dst, const Operand& src);
754 void movsx_w(Register dst, Register src) { movsx_w(dst, Operand(src)); }
755 void movsx_w(Register dst, const Operand& src);
757 void movzx_b(Register dst, Register src) { movzx_b(dst, Operand(src)); }
758 void movzx_b(Register dst, const Operand& src);
760 void movzx_w(Register dst, Register src) { movzx_w(dst, Operand(src)); }
761 void movzx_w(Register dst, const Operand& src);
764 void cmov(Condition cc, Register dst, Register src) {
765 cmov(cc, dst, Operand(src));
767 void cmov(Condition cc, Register dst, const Operand& src);
772 // Repetitive string instructions.
777 // Exchange two registers
778 void xchg(Register dst, Register src);
781 void adc(Register dst, int32_t imm32);
782 void adc(Register dst, const Operand& src);
784 void add(Register dst, Register src) { add(dst, Operand(src)); }
785 void add(Register dst, const Operand& src);
786 void add(const Operand& dst, Register src);
787 void add(Register dst, const Immediate& imm) { add(Operand(dst), imm); }
788 void add(const Operand& dst, const Immediate& x);
790 void and_(Register dst, int32_t imm32);
791 void and_(Register dst, const Immediate& x);
792 void and_(Register dst, Register src) { and_(dst, Operand(src)); }
793 void and_(Register dst, const Operand& src);
794 void and_(const Operand& dst, Register src);
795 void and_(const Operand& dst, const Immediate& x);
797 void cmpb(Register reg, int8_t imm8) { cmpb(Operand(reg), imm8); }
798 void cmpb(const Operand& op, int8_t imm8);
799 void cmpb(Register reg, const Operand& op);
800 void cmpb(const Operand& op, Register reg);
801 void cmpb_al(const Operand& op);
802 void cmpw_ax(const Operand& op);
803 void cmpw(const Operand& op, Immediate imm16);
804 void cmp(Register reg, int32_t imm32);
805 void cmp(Register reg, Handle<Object> handle);
806 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); }
807 void cmp(Register reg, const Operand& op);
808 void cmp(Register reg, const Immediate& imm) { cmp(Operand(reg), imm); }
809 void cmp(const Operand& op, const Immediate& imm);
810 void cmp(const Operand& op, Handle<Object> handle);
812 void dec_b(Register dst);
813 void dec_b(const Operand& dst);
815 void dec(Register dst);
816 void dec(const Operand& dst);
820 void idiv(Register src);
822 // Signed multiply instructions.
823 void imul(Register src); // edx:eax = eax * src.
824 void imul(Register dst, Register src) { imul(dst, Operand(src)); }
825 void imul(Register dst, const Operand& src); // dst = dst * src.
826 void imul(Register dst, Register src, int32_t imm32); // dst = src * imm32.
828 void inc(Register dst);
829 void inc(const Operand& dst);
831 void lea(Register dst, const Operand& src);
833 // Unsigned multiply instruction.
834 void mul(Register src); // edx:eax = eax * reg.
836 void neg(Register dst);
838 void not_(Register dst);
840 void or_(Register dst, int32_t imm32);
841 void or_(Register dst, Register src) { or_(dst, Operand(src)); }
842 void or_(Register dst, const Operand& src);
843 void or_(const Operand& dst, Register src);
844 void or_(Register dst, const Immediate& imm) { or_(Operand(dst), imm); }
845 void or_(const Operand& dst, const Immediate& x);
847 void rcl(Register dst, uint8_t imm8);
848 void rcr(Register dst, uint8_t imm8);
849 void ror(Register dst, uint8_t imm8);
850 void ror_cl(Register dst);
852 void sar(Register dst, uint8_t imm8);
853 void sar_cl(Register dst);
855 void sbb(Register dst, const Operand& src);
857 void shld(Register dst, Register src) { shld(dst, Operand(src)); }
858 void shld(Register dst, const Operand& src);
860 void shl(Register dst, uint8_t imm8);
861 void shl_cl(Register dst);
863 void shrd(Register dst, Register src) { shrd(dst, Operand(src)); }
864 void shrd(Register dst, const Operand& src);
866 void shr(Register dst, uint8_t imm8);
867 void shr_cl(Register dst);
869 void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); }
870 void sub(const Operand& dst, const Immediate& x);
871 void sub(Register dst, Register src) { sub(dst, Operand(src)); }
872 void sub(Register dst, const Operand& src);
873 void sub(const Operand& dst, Register src);
875 void test(Register reg, const Immediate& imm);
876 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); }
877 void test(Register reg, const Operand& op);
878 void test_b(Register reg, const Operand& op);
879 void test(const Operand& op, const Immediate& imm);
880 void test_b(Register reg, uint8_t imm8);
881 void test_b(const Operand& op, uint8_t imm8);
883 void xor_(Register dst, int32_t imm32);
884 void xor_(Register dst, Register src) { xor_(dst, Operand(src)); }
885 void xor_(Register dst, const Operand& src);
886 void xor_(const Operand& dst, Register src);
887 void xor_(Register dst, const Immediate& imm) { xor_(Operand(dst), imm); }
888 void xor_(const Operand& dst, const Immediate& x);
891 void bt(const Operand& dst, Register src);
892 void bts(Register dst, Register src) { bts(Operand(dst), src); }
893 void bts(const Operand& dst, Register src);
901 // Label operations & relative jumps (PPUM Appendix D)
903 // Takes a branch opcode (cc) and a label (L) and generates
904 // either a backward branch or a forward branch and links it
905 // to the label fixup chain. Usage:
907 // Label L; // unbound label
908 // j(cc, &L); // forward branch to unbound label
909 // bind(&L); // bind label to the current pc
910 // j(cc, &L); // backward branch to bound label
911 // bind(&L); // illegal: a label may be bound only once
913 // Note: The same Label can be used for forward and backward branches
914 // but it may be bound only once.
916 void bind(Label* L); // binds an unbound label L to the current code position
920 void call(byte* entry, RelocInfo::Mode rmode);
921 int CallSize(const Operand& adr);
922 void call(Register reg) { call(Operand(reg)); }
923 void call(const Operand& adr);
924 int CallSize(Handle<Code> code, RelocInfo::Mode mode);
925 void call(Handle<Code> code,
926 RelocInfo::Mode rmode,
927 TypeFeedbackId id = TypeFeedbackId::None());
930 // unconditional jump to L
931 void jmp(Label* L, Label::Distance distance = Label::kFar);
932 void jmp(byte* entry, RelocInfo::Mode rmode);
933 void jmp(Register reg) { jmp(Operand(reg)); }
934 void jmp(const Operand& adr);
935 void jmp(Handle<Code> code, RelocInfo::Mode rmode);
940 Label::Distance distance = Label::kFar);
941 void j(Condition cc, byte* entry, RelocInfo::Mode rmode);
942 void j(Condition cc, Handle<Code> code);
944 // Floating-point operations
953 void fld_s(const Operand& adr);
954 void fld_d(const Operand& adr);
956 void fstp_s(const Operand& adr);
957 void fst_s(const Operand& adr);
958 void fstp_d(const Operand& adr);
959 void fst_d(const Operand& adr);
961 void fild_s(const Operand& adr);
962 void fild_d(const Operand& adr);
964 void fist_s(const Operand& adr);
966 void fistp_s(const Operand& adr);
967 void fistp_d(const Operand& adr);
969 // The fisttp instructions require SSE3.
970 void fisttp_s(const Operand& adr);
971 void fisttp_d(const Operand& adr);
992 void fisub_s(const Operand& adr);
994 void faddp(int i = 1);
995 void fsubp(int i = 1);
996 void fsubrp(int i = 1);
997 void fmulp(int i = 1);
998 void fdivp(int i = 1);
1002 void fxch(int i = 1);
1004 void ffree(int i = 0);
1019 void setcc(Condition cc, Register reg);
1024 void movaps(XMMRegister dst, XMMRegister src);
1025 void movups(XMMRegister dst, const Operand& src);
1026 void movups(const Operand& dst, XMMRegister src);
1027 void shufps(XMMRegister dst, XMMRegister src, byte imm8);
1029 void andps(XMMRegister dst, const Operand& src);
1030 void andps(XMMRegister dst, XMMRegister src) { andps(dst, Operand(src)); }
1031 void xorps(XMMRegister dst, const Operand& src);
1032 void xorps(XMMRegister dst, XMMRegister src) { xorps(dst, Operand(src)); }
1033 void orps(XMMRegister dst, const Operand& src);
1034 void orps(XMMRegister dst, XMMRegister src) { orps(dst, Operand(src)); }
1036 void addps(XMMRegister dst, const Operand& src);
1037 void addps(XMMRegister dst, XMMRegister src) { addps(dst, Operand(src)); }
1038 void subps(XMMRegister dst, const Operand& src);
1039 void subps(XMMRegister dst, XMMRegister src) { subps(dst, Operand(src)); }
1040 void mulps(XMMRegister dst, const Operand& src);
1041 void mulps(XMMRegister dst, XMMRegister src) { mulps(dst, Operand(src)); }
1042 void divps(XMMRegister dst, const Operand& src);
1043 void divps(XMMRegister dst, XMMRegister src) { divps(dst, Operand(src)); }
1044 void minps(XMMRegister dst, XMMRegister src) { minps(dst, Operand(src)); }
1045 void minps(XMMRegister dst, const Operand& src);
1046 void maxps(XMMRegister dst, XMMRegister src) { maxps(dst, Operand(src)); }
1047 void maxps(XMMRegister dst, const Operand& src);
1048 void rcpps(XMMRegister dst, XMMRegister src) { rcpps(dst, Operand(src)); }
1049 void rcpps(XMMRegister dst, const Operand& src);
1050 void rsqrtps(XMMRegister dst, XMMRegister src) { rsqrtps(dst, Operand(src)); }
1051 void rsqrtps(XMMRegister dst, const Operand& src);
1052 void sqrtps(XMMRegister dst, XMMRegister src) { sqrtps(dst, Operand(src)); }
1053 void sqrtps(XMMRegister dst, const Operand& src);
1055 void cvtdq2ps(XMMRegister dst, const Operand& src);
1056 void cmpps(XMMRegister dst, XMMRegister src, int8_t cmp);
1057 void cmpeqps(XMMRegister dst, XMMRegister src);
1058 void cmpltps(XMMRegister dst, XMMRegister src);
1059 void cmpleps(XMMRegister dst, XMMRegister src);
1060 void cmpneqps(XMMRegister dst, XMMRegister src);
1061 void cmpnltps(XMMRegister dst, XMMRegister src);
1062 void cmpnleps(XMMRegister dst, XMMRegister src);
1064 // SSE 2, introduced by SIMD
1065 void paddd(XMMRegister dst, XMMRegister src) { paddd(dst, Operand(src)); }
1066 void paddd(XMMRegister dst, const Operand& src);
1067 void psubd(XMMRegister dst, XMMRegister src) { psubd(dst, Operand(src)); }
1068 void psubd(XMMRegister dst, const Operand& src);
1069 void pmuludq(XMMRegister dst, XMMRegister src) { pmuludq(dst, Operand(src)); }
1070 void pmuludq(XMMRegister dst, const Operand& src);
1071 void punpackldq(XMMRegister dst, XMMRegister src) {
1072 punpackldq(dst, Operand(src));
1074 void punpackldq(XMMRegister dst, const Operand& src);
1075 void cvtps2dq(XMMRegister dst, XMMRegister src) {
1076 cvtps2dq(dst, Operand(src));
1078 void cvtps2dq(XMMRegister dst, const Operand& src);
1079 void cvtdq2ps(XMMRegister dst, XMMRegister src) {
1080 cvtdq2ps(dst, Operand(src));
1082 // SSE 4.1, introduced by SIMD
1083 void insertps(XMMRegister dst, XMMRegister src, byte imm8);
1084 void pmulld(XMMRegister dst, XMMRegister src) { pmulld(dst, Operand(src)); }
1085 void pmulld(XMMRegister dst, const Operand& src);
1087 // SSE2 instructions
1088 void cvttss2si(Register dst, const Operand& src);
1089 void cvttss2si(Register dst, XMMRegister src) {
1090 cvttss2si(dst, Operand(src));
1092 void cvttsd2si(Register dst, const Operand& src);
1093 void cvtsd2si(Register dst, XMMRegister src);
1095 void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); }
1096 void cvtsi2sd(XMMRegister dst, const Operand& src);
1097 void cvtss2sd(XMMRegister dst, XMMRegister src);
1098 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1100 void addsd(XMMRegister dst, XMMRegister src);
1101 void addsd(XMMRegister dst, const Operand& src);
1102 void subsd(XMMRegister dst, XMMRegister src);
1103 void mulsd(XMMRegister dst, XMMRegister src);
1104 void mulsd(XMMRegister dst, const Operand& src);
1105 void divsd(XMMRegister dst, XMMRegister src);
1106 void xorpd(XMMRegister dst, XMMRegister src);
1107 void sqrtsd(XMMRegister dst, XMMRegister src);
1109 void andpd(XMMRegister dst, XMMRegister src);
1110 void orpd(XMMRegister dst, XMMRegister src);
1112 void ucomisd(XMMRegister dst, XMMRegister src) { ucomisd(dst, Operand(src)); }
1113 void ucomisd(XMMRegister dst, const Operand& src);
1116 kRoundToNearest = 0x0,
1122 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
1124 void movmskpd(Register dst, XMMRegister src);
1125 void movmskps(Register dst, XMMRegister src);
1127 void cmpltsd(XMMRegister dst, XMMRegister src);
1128 void pcmpeqd(XMMRegister dst, XMMRegister src);
1129 void pcmpgtd(XMMRegister dst, XMMRegister src);
1131 void movdqa(XMMRegister dst, const Operand& src);
1132 void movdqa(const Operand& dst, XMMRegister src);
1133 void movdqu(XMMRegister dst, const Operand& src);
1134 void movdqu(const Operand& dst, XMMRegister src);
1135 void movdq(bool aligned, XMMRegister dst, const Operand& src) {
1143 void movd(XMMRegister dst, Register src) { movd(dst, Operand(src)); }
1144 void movd(XMMRegister dst, const Operand& src);
1145 void movd(Register dst, XMMRegister src) { movd(Operand(dst), src); }
1146 void movd(const Operand& dst, XMMRegister src);
1147 void movsd(XMMRegister dst, XMMRegister src) { movsd(dst, Operand(src)); }
1148 void movsd(XMMRegister dst, const Operand& src);
1149 void movsd(const Operand& dst, XMMRegister src);
1152 void movss(XMMRegister dst, const Operand& src);
1153 void movss(const Operand& dst, XMMRegister src);
1154 void movss(XMMRegister dst, XMMRegister src) { movss(dst, Operand(src)); }
1155 void extractps(Register dst, XMMRegister src, byte imm8);
1157 void pand(XMMRegister dst, XMMRegister src);
1158 void pxor(XMMRegister dst, XMMRegister src);
1159 void por(XMMRegister dst, XMMRegister src);
1160 void ptest(XMMRegister dst, XMMRegister src);
1162 void psllq(XMMRegister reg, int8_t shift);
1163 void psllq(XMMRegister dst, XMMRegister src);
1164 void pslld(XMMRegister reg, int8_t shift);
1165 void pslld(XMMRegister dst, XMMRegister src);
1166 void psrld(XMMRegister reg, int8_t shift);
1167 void psrld(XMMRegister dst, XMMRegister src);
1168 void psrad(XMMRegister reg, int8_t shift);
1169 void psrad(XMMRegister dst, XMMRegister src);
1170 void psrlq(XMMRegister reg, int8_t shift);
1171 void psrlq(XMMRegister dst, XMMRegister src);
1172 void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle);
1173 void pextrd(Register dst, XMMRegister src, int8_t offset) {
1174 pextrd(Operand(dst), src, offset);
1176 void pextrd(const Operand& dst, XMMRegister src, int8_t offset);
1177 void pinsrd(XMMRegister dst, Register src, int8_t offset) {
1178 pinsrd(dst, Operand(src), offset);
1180 void pinsrd(XMMRegister dst, const Operand& src, int8_t offset);
1182 // Parallel XMM operations.
1183 void movntdqa(XMMRegister dst, const Operand& src);
1184 void movntdq(const Operand& dst, XMMRegister src);
1185 // Prefetch src position into cache level.
1186 // Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a
1188 void prefetch(const Operand& src, int level);
1189 // TODO(lrn): Need SFENCE for movnt?
1194 // Check the code size generated from label to here.
1195 int SizeOfCodeGeneratedSince(Label* label) {
1196 return pc_offset() - label->pos();
1199 // Mark address of the ExitJSFrame code.
1200 void RecordJSReturn();
1202 // Mark address of a debug break slot.
1203 void RecordDebugBreakSlot();
1205 // Record a comment relocation entry that can be used by a disassembler.
1206 // Use --code-comments to enable, or provide "force = true" flag to always
1208 void RecordComment(const char* msg, bool force = false);
1210 // Writes a single byte or word of data in the code stream. Used for
1211 // inline tables, e.g., jump-tables.
1212 void db(uint8_t data);
1213 void dd(uint32_t data);
1215 // Check if there is less than kGap bytes available in the buffer.
1216 // If this is the case, we need to grow the buffer before emitting
1217 // an instruction or relocation information.
1218 inline bool overflow() const { return pc_ >= reloc_info_writer.pos() - kGap; }
1220 // Get the number of bytes available in the buffer.
1221 inline int available_space() const { return reloc_info_writer.pos() - pc_; }
1223 static bool IsNop(Address addr);
1225 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1227 int relocation_writer_size() {
1228 return (buffer_ + buffer_size_) - reloc_info_writer.pos();
1231 // Avoid overflows for displacements etc.
1232 static const int kMaximalBufferSize = 512*MB;
1234 byte byte_at(int pos) { return buffer_[pos]; }
1235 void set_byte_at(int pos, byte value) { buffer_[pos] = value; }
1238 void emit_sse_operand(XMMRegister reg, const Operand& adr);
1239 void emit_sse_operand(XMMRegister dst, XMMRegister src);
1240 void emit_sse_operand(Register dst, XMMRegister src);
1241 void emit_sse_operand(XMMRegister dst, Register src);
1243 byte* addr_at(int pos) { return buffer_ + pos; }
1247 uint32_t long_at(int pos) {
1248 return *reinterpret_cast<uint32_t*>(addr_at(pos));
1250 void long_at_put(int pos, uint32_t x) {
1251 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
1256 inline void emit(uint32_t x);
1257 inline void emit(Handle<Object> handle);
1258 inline void emit(uint32_t x,
1259 RelocInfo::Mode rmode,
1260 TypeFeedbackId id = TypeFeedbackId::None());
1261 inline void emit(Handle<Code> code,
1262 RelocInfo::Mode rmode,
1263 TypeFeedbackId id = TypeFeedbackId::None());
1264 inline void emit(const Immediate& x);
1265 inline void emit_w(const Immediate& x);
1267 // Emit the code-object-relative offset of the label's position
1268 inline void emit_code_relative_offset(Label* label);
1270 // instruction generation
1271 void emit_arith_b(int op1, int op2, Register dst, int imm8);
1273 // Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81)
1274 // with a given destination expression and an immediate operand. It attempts
1275 // to use the shortest encoding possible.
1276 // sel specifies the /n in the modrm byte (see the Intel PRM).
1277 void emit_arith(int sel, Operand dst, const Immediate& x);
1279 void emit_operand(Register reg, const Operand& adr);
1281 void emit_farith(int b1, int b2, int i);
1284 void print(Label* L);
1285 void bind_to(Label* L, int pos);
1288 inline Displacement disp_at(Label* L);
1289 inline void disp_at_put(Label* L, Displacement disp);
1290 inline void emit_disp(Label* L, Displacement::Type type);
1291 inline void emit_near_disp(Label* L);
1293 // record reloc info for current pc_
1294 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1296 friend class CodePatcher;
1297 friend class EnsureSpace;
1300 RelocInfoWriter reloc_info_writer;
1302 PositionsRecorder positions_recorder_;
1303 friend class PositionsRecorder;
1307 // Helper class that ensures that there is enough space for generating
1308 // instructions and relocation information. The constructor makes
1309 // sure that there is enough space and (in debug mode) the destructor
1310 // checks that we did not generate too much.
1311 class EnsureSpace BASE_EMBEDDED {
1313 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
1314 if (assembler_->overflow()) assembler_->GrowBuffer();
1316 space_before_ = assembler_->available_space();
1322 int bytes_generated = space_before_ - assembler_->available_space();
1323 ASSERT(bytes_generated < assembler_->kGap);
1328 Assembler* assembler_;
1334 } } // namespace v8::internal
1336 #endif // V8_IA32_ASSEMBLER_IA32_H_