1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
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5 // modification, are permitted provided that the following conditions are
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31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2011 the V8 project authors. All rights reserved.
35 // A light-weight IA32 Assembler.
37 #ifndef V8_IA32_ASSEMBLER_IA32_H_
38 #define V8_IA32_ASSEMBLER_IA32_H_
40 #include "src/isolate.h"
41 #include "src/serialize.h"
48 // 1) We would prefer to use an enum, but enum values are assignment-
49 // compatible with int, which has caused code-generation bugs.
51 // 2) We would prefer to use a class instead of a struct but we don't like
52 // the register initialization to depend on the particular initialization
53 // order (which appears to be different on OS X, Linux, and Windows for the
54 // installed versions of C++ we tried). Using a struct permits C-style
55 // "initialization". Also, the Register objects cannot be const as this
56 // forces initialization stubs in MSVC, making us dependent on initialization
59 // 3) By not using an enum, we are possibly preventing the compiler from
60 // doing certain constant folds, which may significantly reduce the
61 // code generated for some assembly instructions (because they boil down
62 // to a few constants). If this is a problem, we could change the code
63 // such that we use an enum in optimized mode, and the struct in debug
64 // mode. This way we get the compile-time error checking in debug mode
65 // and best performance in optimized code.
68 static const int kMaxNumAllocatableRegisters = 6;
69 static int NumAllocatableRegisters() {
70 return kMaxNumAllocatableRegisters;
72 static const int kNumRegisters = 8;
74 static inline const char* AllocationIndexToString(int index);
76 static inline int ToAllocationIndex(Register reg);
78 static inline Register FromAllocationIndex(int index);
80 static Register from_code(int code) {
82 ASSERT(code < kNumRegisters);
83 Register r = { code };
86 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
87 bool is(Register reg) const { return code_ == reg.code_; }
88 // eax, ebx, ecx and edx are byte registers, the rest are not.
89 bool is_byte_register() const { return code_ <= 3; }
99 // Unfortunately we can't make this private in a struct.
103 const int kRegister_eax_Code = 0;
104 const int kRegister_ecx_Code = 1;
105 const int kRegister_edx_Code = 2;
106 const int kRegister_ebx_Code = 3;
107 const int kRegister_esp_Code = 4;
108 const int kRegister_ebp_Code = 5;
109 const int kRegister_esi_Code = 6;
110 const int kRegister_edi_Code = 7;
111 const int kRegister_no_reg_Code = -1;
113 const Register eax = { kRegister_eax_Code };
114 const Register ecx = { kRegister_ecx_Code };
115 const Register edx = { kRegister_edx_Code };
116 const Register ebx = { kRegister_ebx_Code };
117 const Register esp = { kRegister_esp_Code };
118 const Register ebp = { kRegister_ebp_Code };
119 const Register esi = { kRegister_esi_Code };
120 const Register edi = { kRegister_edi_Code };
121 const Register no_reg = { kRegister_no_reg_Code };
124 inline const char* Register::AllocationIndexToString(int index) {
125 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
126 // This is the mapping of allocation indices to registers.
127 const char* const kNames[] = { "eax", "ecx", "edx", "ebx", "esi", "edi" };
128 return kNames[index];
132 inline int Register::ToAllocationIndex(Register reg) {
133 ASSERT(reg.is_valid() && !reg.is(esp) && !reg.is(ebp));
134 return (reg.code() >= 6) ? reg.code() - 2 : reg.code();
138 inline Register Register::FromAllocationIndex(int index) {
139 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
140 return (index >= 4) ? from_code(index + 2) : from_code(index);
145 static const int kMaxNumAllocatableRegisters = 7;
146 static const int kMaxNumRegisters = 8;
147 static int NumAllocatableRegisters() {
148 return kMaxNumAllocatableRegisters;
151 static int ToAllocationIndex(XMMRegister reg) {
152 ASSERT(reg.code() != 0);
153 return reg.code() - 1;
156 static XMMRegister FromAllocationIndex(int index) {
157 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
158 return from_code(index + 1);
161 static XMMRegister from_code(int code) {
162 XMMRegister result = { code };
166 bool is_valid() const {
167 return 0 <= code_ && code_ < kMaxNumRegisters;
175 bool is(XMMRegister reg) const { return code_ == reg.code_; }
177 static const char* AllocationIndexToString(int index) {
178 ASSERT(index >= 0 && index < kMaxNumAllocatableRegisters);
179 const char* const names[] = {
195 typedef XMMRegister DoubleRegister;
196 typedef XMMRegister SIMD128Register;
198 const XMMRegister xmm0 = { 0 };
199 const XMMRegister xmm1 = { 1 };
200 const XMMRegister xmm2 = { 2 };
201 const XMMRegister xmm3 = { 3 };
202 const XMMRegister xmm4 = { 4 };
203 const XMMRegister xmm5 = { 5 };
204 const XMMRegister xmm6 = { 6 };
205 const XMMRegister xmm7 = { 7 };
206 const XMMRegister no_xmm_reg = { -1 };
210 // any value < 0 is considered no_condition
232 not_carry = above_equal,
234 not_zero = not_equal,
240 // Returns the equivalent of !cc.
241 // Negation of the default no_condition (-1) results in a non-default
242 // no_condition value (-2). As long as tests for no_condition check
243 // for condition < 0, this will work as expected.
244 inline Condition NegateCondition(Condition cc) {
245 return static_cast<Condition>(cc ^ 1);
249 // Commute a condition such that {a cond b == b cond' a}.
250 inline Condition CommuteCondition(Condition cc) {
267 return greater_equal;
274 // -----------------------------------------------------------------------------
275 // Machine instruction Immediates
277 class Immediate BASE_EMBEDDED {
279 inline explicit Immediate(int x);
280 inline explicit Immediate(const ExternalReference& ext);
281 inline explicit Immediate(Handle<Object> handle);
282 inline explicit Immediate(Smi* value);
283 inline explicit Immediate(Address addr);
285 static Immediate CodeRelativeOffset(Label* label) {
286 return Immediate(label);
289 bool is_zero() const { return x_ == 0 && RelocInfo::IsNone(rmode_); }
290 bool is_int8() const {
291 return -128 <= x_ && x_ < 128 && RelocInfo::IsNone(rmode_);
293 bool is_int16() const {
294 return -32768 <= x_ && x_ < 32768 && RelocInfo::IsNone(rmode_);
298 inline explicit Immediate(Label* value);
301 RelocInfo::Mode rmode_;
303 friend class Assembler;
304 friend class MacroAssembler;
308 // -----------------------------------------------------------------------------
309 // Machine instruction Operands
316 maximal_scale_factor = times_8,
317 times_int_size = times_4,
318 times_half_pointer_size = times_2,
319 times_pointer_size = times_4,
320 times_twice_pointer_size = times_8
324 class Operand BASE_EMBEDDED {
327 INLINE(explicit Operand(XMMRegister xmm_reg));
330 INLINE(explicit Operand(int32_t disp, RelocInfo::Mode rmode));
331 // disp only must always be relocated
334 explicit Operand(Register base, int32_t disp,
335 RelocInfo::Mode rmode = RelocInfo::NONE32);
337 // [base + index*scale + disp/r]
338 explicit Operand(Register base,
342 RelocInfo::Mode rmode = RelocInfo::NONE32);
344 // [index*scale + disp/r]
345 explicit Operand(Register index,
348 RelocInfo::Mode rmode = RelocInfo::NONE32);
350 // Offset from existing memory operand.
351 // Offset is added to existing displacement as 32-bit signed values and
352 // this must not overflow.
353 Operand(const Operand& base, int32_t offset);
355 static Operand StaticVariable(const ExternalReference& ext) {
356 return Operand(reinterpret_cast<int32_t>(ext.address()),
357 RelocInfo::EXTERNAL_REFERENCE);
360 static Operand StaticArray(Register index,
362 const ExternalReference& arr) {
363 return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()),
364 RelocInfo::EXTERNAL_REFERENCE);
367 static Operand ForCell(Handle<Cell> cell) {
368 AllowDeferredHandleDereference embedding_raw_address;
369 return Operand(reinterpret_cast<int32_t>(cell.location()),
373 // Returns true if this Operand is a wrapper for the specified register.
374 bool is_reg(Register reg) const;
376 // Returns true if this Operand is a wrapper for one register.
377 bool is_reg_only() const;
379 // Asserts that this Operand is a wrapper for one register and returns the
381 Register reg() const;
385 INLINE(explicit Operand(Register reg));
387 // Set the ModRM byte without an encoded 'reg' register. The
388 // register is encoded later as part of the emit_operand operation.
389 inline void set_modrm(int mod, Register rm);
391 inline void set_sib(ScaleFactor scale, Register index, Register base);
392 inline void set_disp8(int8_t disp);
393 inline void set_dispr(int32_t disp, RelocInfo::Mode rmode);
396 // The number of bytes in buf_.
398 // Only valid if len_ > 4.
399 RelocInfo::Mode rmode_;
401 friend class Assembler;
402 friend class MacroAssembler;
403 friend class LCodeGen;
407 // -----------------------------------------------------------------------------
408 // A Displacement describes the 32bit immediate field of an instruction which
409 // may be used together with a Label in order to refer to a yet unknown code
410 // position. Displacements stored in the instruction stream are used to describe
411 // the instruction and to chain a list of instructions using the same Label.
412 // A Displacement contains 2 different fields:
414 // next field: position of next displacement in the chain (0 = end of list)
415 // type field: instruction type
417 // A next value of null (0) indicates the end of a chain (note that there can
418 // be no displacement at position zero, because there is always at least one
419 // instruction byte before the displacement).
421 // Displacement _data field layout
423 // |31.....2|1......0|
426 class Displacement BASE_EMBEDDED {
434 int data() const { return data_; }
435 Type type() const { return TypeField::decode(data_); }
436 void next(Label* L) const {
437 int n = NextField::decode(data_);
438 n > 0 ? L->link_to(n) : L->Unuse();
440 void link_to(Label* L) { init(L, type()); }
442 explicit Displacement(int data) { data_ = data; }
444 Displacement(Label* L, Type type) { init(L, type); }
447 PrintF("%s (%x) ", (type() == UNCONDITIONAL_JUMP ? "jmp" : "[other]"),
448 NextField::decode(data_));
454 class TypeField: public BitField<Type, 0, 2> {};
455 class NextField: public BitField<int, 2, 32-2> {};
457 void init(Label* L, Type type);
461 class Assembler : public AssemblerBase {
463 // We check before assembling an instruction that there is sufficient
464 // space to write an instruction and its relocation information.
465 // The relocation writer's position must be kGap bytes above the end of
466 // the generated instructions. This leaves enough space for the
467 // longest possible ia32 instruction, 15 bytes, and the longest possible
468 // relocation information encoding, RelocInfoWriter::kMaxLength == 16.
469 // (There is a 15 byte limit on ia32 instruction length that rules out some
470 // otherwise valid instructions.)
471 // This allows for a single, fast space check per instruction.
472 static const int kGap = 32;
475 // Create an assembler. Instructions and relocation information are emitted
476 // into a buffer, with the instructions starting from the beginning and the
477 // relocation information starting from the end of the buffer. See CodeDesc
478 // for a detailed comment on the layout (globals.h).
480 // If the provided buffer is NULL, the assembler allocates and grows its own
481 // buffer, and buffer_size determines the initial buffer size. The buffer is
482 // owned by the assembler and deallocated upon destruction of the assembler.
484 // If the provided buffer is not NULL, the assembler uses the provided buffer
485 // for code generation and assumes its size to be buffer_size. If the buffer
486 // is too small, a fatal error occurs. No deallocation of the buffer is done
487 // upon destruction of the assembler.
488 // TODO(vitalyr): the assembler does not need an isolate.
489 Assembler(Isolate* isolate, void* buffer, int buffer_size);
490 virtual ~Assembler() { }
492 // GetCode emits any pending (non-emitted) code and fills the descriptor
493 // desc. GetCode() is idempotent; it returns the same result if no other
494 // Assembler functions are invoked in between GetCode() calls.
495 void GetCode(CodeDesc* desc);
497 // Read/Modify the code target in the branch/call instruction at pc.
498 inline static Address target_address_at(Address pc,
499 ConstantPoolArray* constant_pool);
500 inline static void set_target_address_at(Address pc,
501 ConstantPoolArray* constant_pool,
503 ICacheFlushMode icache_flush_mode =
504 FLUSH_ICACHE_IF_NEEDED);
505 static inline Address target_address_at(Address pc, Code* code) {
506 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
507 return target_address_at(pc, constant_pool);
509 static inline void set_target_address_at(Address pc,
512 ICacheFlushMode icache_flush_mode =
513 FLUSH_ICACHE_IF_NEEDED) {
514 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
515 set_target_address_at(pc, constant_pool, target);
518 // Return the code target address at a call site from the return address
519 // of that call in the instruction stream.
520 inline static Address target_address_from_return_address(Address pc);
522 // This sets the branch destination (which is in the instruction on x86).
523 // This is for calls and branches within generated code.
524 inline static void deserialization_set_special_target_at(
525 Address instruction_payload, Code* code, Address target) {
526 set_target_address_at(instruction_payload, code, target);
529 static const int kSpecialTargetSize = kPointerSize;
531 // Distance between the address of the code target in the call instruction
532 // and the return address
533 static const int kCallTargetAddressOffset = kPointerSize;
534 // Distance between start of patched return sequence and the emitted address
536 static const int kPatchReturnSequenceAddressOffset = 1; // JMP imm32.
538 // Distance between start of patched debug break slot and the emitted address
540 static const int kPatchDebugBreakSlotAddressOffset = 1; // JMP imm32.
542 static const int kCallInstructionLength = 5;
543 static const int kPatchDebugBreakSlotReturnOffset = kPointerSize;
544 static const int kJSReturnSequenceLength = 6;
546 // The debug break slot must be able to contain a call instruction.
547 static const int kDebugBreakSlotLength = kCallInstructionLength;
549 // One byte opcode for test al, 0xXX.
550 static const byte kTestAlByte = 0xA8;
551 // One byte opcode for nop.
552 static const byte kNopByte = 0x90;
554 // One byte opcode for a short unconditional jump.
555 static const byte kJmpShortOpcode = 0xEB;
556 // One byte prefix for a short conditional jump.
557 static const byte kJccShortPrefix = 0x70;
558 static const byte kJncShortOpcode = kJccShortPrefix | not_carry;
559 static const byte kJcShortOpcode = kJccShortPrefix | carry;
560 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero;
561 static const byte kJzShortOpcode = kJccShortPrefix | zero;
564 // ---------------------------------------------------------------------------
567 // - function names correspond one-to-one to ia32 instruction mnemonics
568 // - unless specified otherwise, instructions operate on 32bit operands
569 // - instructions on 8bit (byte) operands/registers have a trailing '_b'
570 // - instructions on 16bit (word) operands/registers have a trailing '_w'
571 // - naming conflicts with C++ keywords are resolved via a trailing '_'
573 // NOTE ON INTERFACE: Currently, the interface is not very consistent
574 // in the sense that some operations (e.g. mov()) can be called in more
575 // the one way to generate the same instruction: The Register argument
576 // can in some cases be replaced with an Operand(Register) argument.
577 // This should be cleaned up and made more orthogonal. The questions
578 // is: should we always use Operands instead of Registers where an
579 // Operand is possible, or should we have a Register (overloaded) form
580 // instead? We must be careful to make sure that the selected instruction
581 // is obvious from the parameters to avoid hard-to-find code generation
584 // Insert the smallest number of nop instructions
585 // possible to align the pc offset to a multiple
586 // of m. m must be a power of 2.
588 void Nop(int bytes = 1);
589 // Aligns code to something that's optimal for a jump target for the platform.
590 void CodeTargetAlign();
599 void push(const Immediate& x);
600 void push_imm32(int32_t imm32);
601 void push(Register src);
602 void push(const Operand& src);
604 void pop(Register dst);
605 void pop(const Operand& dst);
607 void enter(const Immediate& size);
611 void mov_b(Register dst, Register src) { mov_b(dst, Operand(src)); }
612 void mov_b(Register dst, const Operand& src);
613 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); }
614 void mov_b(const Operand& dst, int8_t imm8);
615 void mov_b(const Operand& dst, Register src);
617 void mov_w(Register dst, const Operand& src);
618 void mov_w(const Operand& dst, Register src);
619 void mov_w(const Operand& dst, int16_t imm16);
621 void mov(Register dst, int32_t imm32);
622 void mov(Register dst, const Immediate& x);
623 void mov(Register dst, Handle<Object> handle);
624 void mov(Register dst, const Operand& src);
625 void mov(Register dst, Register src);
626 void mov(const Operand& dst, const Immediate& x);
627 void mov(const Operand& dst, Handle<Object> handle);
628 void mov(const Operand& dst, Register src);
630 void movsx_b(Register dst, Register src) { movsx_b(dst, Operand(src)); }
631 void movsx_b(Register dst, const Operand& src);
633 void movsx_w(Register dst, Register src) { movsx_w(dst, Operand(src)); }
634 void movsx_w(Register dst, const Operand& src);
636 void movzx_b(Register dst, Register src) { movzx_b(dst, Operand(src)); }
637 void movzx_b(Register dst, const Operand& src);
639 void movzx_w(Register dst, Register src) { movzx_w(dst, Operand(src)); }
640 void movzx_w(Register dst, const Operand& src);
643 void cmov(Condition cc, Register dst, Register src) {
644 cmov(cc, dst, Operand(src));
646 void cmov(Condition cc, Register dst, const Operand& src);
651 // Repetitive string instructions.
656 // Exchange two registers
657 void xchg(Register dst, Register src);
660 void adc(Register dst, int32_t imm32);
661 void adc(Register dst, const Operand& src);
663 void add(Register dst, Register src) { add(dst, Operand(src)); }
664 void add(Register dst, const Operand& src);
665 void add(const Operand& dst, Register src);
666 void add(Register dst, const Immediate& imm) { add(Operand(dst), imm); }
667 void add(const Operand& dst, const Immediate& x);
669 void and_(Register dst, int32_t imm32);
670 void and_(Register dst, const Immediate& x);
671 void and_(Register dst, Register src) { and_(dst, Operand(src)); }
672 void and_(Register dst, const Operand& src);
673 void and_(const Operand& dst, Register src);
674 void and_(const Operand& dst, const Immediate& x);
676 void cmpb(Register reg, int8_t imm8) { cmpb(Operand(reg), imm8); }
677 void cmpb(const Operand& op, int8_t imm8);
678 void cmpb(Register reg, const Operand& op);
679 void cmpb(const Operand& op, Register reg);
680 void cmpb_al(const Operand& op);
681 void cmpw_ax(const Operand& op);
682 void cmpw(const Operand& op, Immediate imm16);
683 void cmp(Register reg, int32_t imm32);
684 void cmp(Register reg, Handle<Object> handle);
685 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); }
686 void cmp(Register reg, const Operand& op);
687 void cmp(Register reg, const Immediate& imm) { cmp(Operand(reg), imm); }
688 void cmp(const Operand& op, const Immediate& imm);
689 void cmp(const Operand& op, Handle<Object> handle);
691 void dec_b(Register dst);
692 void dec_b(const Operand& dst);
694 void dec(Register dst);
695 void dec(const Operand& dst);
699 void idiv(Register src);
701 // Signed multiply instructions.
702 void imul(Register src); // edx:eax = eax * src.
703 void imul(Register dst, Register src) { imul(dst, Operand(src)); }
704 void imul(Register dst, const Operand& src); // dst = dst * src.
705 void imul(Register dst, Register src, int32_t imm32); // dst = src * imm32.
707 void inc(Register dst);
708 void inc(const Operand& dst);
710 void lea(Register dst, const Operand& src);
712 // Unsigned multiply instruction.
713 void mul(Register src); // edx:eax = eax * reg.
715 void neg(Register dst);
717 void not_(Register dst);
719 void or_(Register dst, int32_t imm32);
720 void or_(Register dst, Register src) { or_(dst, Operand(src)); }
721 void or_(Register dst, const Operand& src);
722 void or_(const Operand& dst, Register src);
723 void or_(Register dst, const Immediate& imm) { or_(Operand(dst), imm); }
724 void or_(const Operand& dst, const Immediate& x);
726 void rcl(Register dst, uint8_t imm8);
727 void rcr(Register dst, uint8_t imm8);
728 void ror(Register dst, uint8_t imm8);
729 void ror_cl(Register dst);
731 void sar(Register dst, uint8_t imm8);
732 void sar_cl(Register dst);
734 void sbb(Register dst, const Operand& src);
736 void shld(Register dst, Register src) { shld(dst, Operand(src)); }
737 void shld(Register dst, const Operand& src);
739 void shl(Register dst, uint8_t imm8);
740 void shl_cl(Register dst);
742 void shrd(Register dst, Register src) { shrd(dst, Operand(src)); }
743 void shrd(Register dst, const Operand& src);
745 void shr(Register dst, uint8_t imm8);
746 void shr_cl(Register dst);
748 void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); }
749 void sub(const Operand& dst, const Immediate& x);
750 void sub(Register dst, Register src) { sub(dst, Operand(src)); }
751 void sub(Register dst, const Operand& src);
752 void sub(const Operand& dst, Register src);
754 void test(Register reg, const Immediate& imm);
755 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); }
756 void test(Register reg, const Operand& op);
757 void test_b(Register reg, const Operand& op);
758 void test(const Operand& op, const Immediate& imm);
759 void test_b(Register reg, uint8_t imm8);
760 void test_b(const Operand& op, uint8_t imm8);
762 void xor_(Register dst, int32_t imm32);
763 void xor_(Register dst, Register src) { xor_(dst, Operand(src)); }
764 void xor_(Register dst, const Operand& src);
765 void xor_(const Operand& dst, Register src);
766 void xor_(Register dst, const Immediate& imm) { xor_(Operand(dst), imm); }
767 void xor_(const Operand& dst, const Immediate& x);
770 void bt(const Operand& dst, Register src);
771 void bts(Register dst, Register src) { bts(Operand(dst), src); }
772 void bts(const Operand& dst, Register src);
773 void bsr(Register dst, Register src) { bsr(dst, Operand(src)); }
774 void bsr(Register dst, const Operand& src);
782 // Label operations & relative jumps (PPUM Appendix D)
784 // Takes a branch opcode (cc) and a label (L) and generates
785 // either a backward branch or a forward branch and links it
786 // to the label fixup chain. Usage:
788 // Label L; // unbound label
789 // j(cc, &L); // forward branch to unbound label
790 // bind(&L); // bind label to the current pc
791 // j(cc, &L); // backward branch to bound label
792 // bind(&L); // illegal: a label may be bound only once
794 // Note: The same Label can be used for forward and backward branches
795 // but it may be bound only once.
797 void bind(Label* L); // binds an unbound label L to the current code position
801 void call(byte* entry, RelocInfo::Mode rmode);
802 int CallSize(const Operand& adr);
803 void call(Register reg) { call(Operand(reg)); }
804 void call(const Operand& adr);
805 int CallSize(Handle<Code> code, RelocInfo::Mode mode);
806 void call(Handle<Code> code,
807 RelocInfo::Mode rmode,
808 TypeFeedbackId id = TypeFeedbackId::None());
811 // unconditional jump to L
812 void jmp(Label* L, Label::Distance distance = Label::kFar);
813 void jmp(byte* entry, RelocInfo::Mode rmode);
814 void jmp(Register reg) { jmp(Operand(reg)); }
815 void jmp(const Operand& adr);
816 void jmp(Handle<Code> code, RelocInfo::Mode rmode);
821 Label::Distance distance = Label::kFar);
822 void j(Condition cc, byte* entry, RelocInfo::Mode rmode);
823 void j(Condition cc, Handle<Code> code);
825 // Floating-point operations
834 void fld_s(const Operand& adr);
835 void fld_d(const Operand& adr);
837 void fstp_s(const Operand& adr);
838 void fst_s(const Operand& adr);
839 void fstp_d(const Operand& adr);
840 void fst_d(const Operand& adr);
842 void fild_s(const Operand& adr);
843 void fild_d(const Operand& adr);
845 void fist_s(const Operand& adr);
847 void fistp_s(const Operand& adr);
848 void fistp_d(const Operand& adr);
850 // The fisttp instructions require SSE3.
851 void fisttp_s(const Operand& adr);
852 void fisttp_d(const Operand& adr);
873 void fisub_s(const Operand& adr);
875 void faddp(int i = 1);
876 void fsubp(int i = 1);
877 void fsubrp(int i = 1);
878 void fmulp(int i = 1);
879 void fdivp(int i = 1);
883 void fxch(int i = 1);
885 void ffree(int i = 0);
900 void setcc(Condition cc, Register reg);
905 void movaps(XMMRegister dst, XMMRegister src);
906 void movups(XMMRegister dst, const Operand& src);
907 void movups(const Operand& dst, XMMRegister src);
908 void shufps(XMMRegister dst, XMMRegister src, byte imm8);
909 void shufpd(XMMRegister dst, XMMRegister src, byte imm8);
911 void andps(XMMRegister dst, const Operand& src);
912 void andps(XMMRegister dst, XMMRegister src) { andps(dst, Operand(src)); }
913 void xorps(XMMRegister dst, const Operand& src);
914 void xorps(XMMRegister dst, XMMRegister src) { xorps(dst, Operand(src)); }
915 void orps(XMMRegister dst, const Operand& src);
916 void orps(XMMRegister dst, XMMRegister src) { orps(dst, Operand(src)); }
918 void addps(XMMRegister dst, const Operand& src);
919 void addps(XMMRegister dst, XMMRegister src) { addps(dst, Operand(src)); }
920 void subps(XMMRegister dst, const Operand& src);
921 void subps(XMMRegister dst, XMMRegister src) { subps(dst, Operand(src)); }
922 void mulps(XMMRegister dst, const Operand& src);
923 void mulps(XMMRegister dst, XMMRegister src) { mulps(dst, Operand(src)); }
924 void divps(XMMRegister dst, const Operand& src);
925 void divps(XMMRegister dst, XMMRegister src) { divps(dst, Operand(src)); }
926 void minps(XMMRegister dst, XMMRegister src) { minps(dst, Operand(src)); }
927 void minps(XMMRegister dst, const Operand& src);
928 void maxps(XMMRegister dst, XMMRegister src) { maxps(dst, Operand(src)); }
929 void maxps(XMMRegister dst, const Operand& src);
930 void rcpps(XMMRegister dst, XMMRegister src) { rcpps(dst, Operand(src)); }
931 void rcpps(XMMRegister dst, const Operand& src);
932 void rsqrtps(XMMRegister dst, XMMRegister src) { rsqrtps(dst, Operand(src)); }
933 void rsqrtps(XMMRegister dst, const Operand& src);
934 void sqrtps(XMMRegister dst, XMMRegister src) { sqrtps(dst, Operand(src)); }
935 void sqrtps(XMMRegister dst, const Operand& src);
936 void sqrtpd(XMMRegister dst, XMMRegister src) { sqrtpd(dst, Operand(src)); }
937 void sqrtpd(XMMRegister dst, const Operand& src);
939 void addpd(XMMRegister dst, const Operand& src);
940 void addpd(XMMRegister dst, XMMRegister src) { addpd(dst, Operand(src)); }
941 void subpd(XMMRegister dst, const Operand& src);
942 void subpd(XMMRegister dst, XMMRegister src) { subpd(dst, Operand(src)); }
943 void mulpd(XMMRegister dst, const Operand& src);
944 void mulpd(XMMRegister dst, XMMRegister src) { mulpd(dst, Operand(src)); }
945 void divpd(XMMRegister dst, const Operand& src);
946 void divpd(XMMRegister dst, XMMRegister src) { divpd(dst, Operand(src)); }
947 void minpd(XMMRegister dst, XMMRegister src) { minpd(dst, Operand(src)); }
948 void minpd(XMMRegister dst, const Operand& src);
949 void maxpd(XMMRegister dst, XMMRegister src) { maxpd(dst, Operand(src)); }
950 void maxpd(XMMRegister dst, const Operand& src);
952 void cvtdq2ps(XMMRegister dst, const Operand& src);
953 void cmpps(XMMRegister dst, XMMRegister src, int8_t cmp);
954 void cmpeqps(XMMRegister dst, XMMRegister src);
955 void cmpltps(XMMRegister dst, XMMRegister src);
956 void cmpleps(XMMRegister dst, XMMRegister src);
957 void cmpneqps(XMMRegister dst, XMMRegister src);
958 void cmpnltps(XMMRegister dst, XMMRegister src);
959 void cmpnleps(XMMRegister dst, XMMRegister src);
961 // SSE 2, introduced by SIMD
962 void paddd(XMMRegister dst, XMMRegister src) { paddd(dst, Operand(src)); }
963 void paddd(XMMRegister dst, const Operand& src);
964 void psubd(XMMRegister dst, XMMRegister src) { psubd(dst, Operand(src)); }
965 void psubd(XMMRegister dst, const Operand& src);
966 void pmuludq(XMMRegister dst, XMMRegister src) { pmuludq(dst, Operand(src)); }
967 void pmuludq(XMMRegister dst, const Operand& src);
968 void punpackldq(XMMRegister dst, XMMRegister src) {
969 punpackldq(dst, Operand(src));
971 void punpackldq(XMMRegister dst, const Operand& src);
972 void cvtps2dq(XMMRegister dst, XMMRegister src) {
973 cvtps2dq(dst, Operand(src));
975 void cvtps2dq(XMMRegister dst, const Operand& src);
976 void cvtdq2ps(XMMRegister dst, XMMRegister src) {
977 cvtdq2ps(dst, Operand(src));
979 // SSE 4.1, introduced by SIMD
980 void insertps(XMMRegister dst, XMMRegister src, byte imm8);
981 void pmulld(XMMRegister dst, XMMRegister src) { pmulld(dst, Operand(src)); }
982 void pmulld(XMMRegister dst, const Operand& src);
985 void cvttss2si(Register dst, const Operand& src);
986 void cvttss2si(Register dst, XMMRegister src) {
987 cvttss2si(dst, Operand(src));
989 void cvttsd2si(Register dst, const Operand& src);
990 void cvtsd2si(Register dst, XMMRegister src);
992 void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); }
993 void cvtsi2sd(XMMRegister dst, const Operand& src);
994 void cvtss2sd(XMMRegister dst, XMMRegister src);
995 void cvtsd2ss(XMMRegister dst, XMMRegister src);
997 void addsd(XMMRegister dst, XMMRegister src);
998 void addsd(XMMRegister dst, const Operand& src);
999 void subsd(XMMRegister dst, XMMRegister src);
1000 void mulsd(XMMRegister dst, XMMRegister src);
1001 void mulsd(XMMRegister dst, const Operand& src);
1002 void divsd(XMMRegister dst, XMMRegister src);
1003 void xorpd(XMMRegister dst, XMMRegister src);
1004 void xorpd(XMMRegister dst, const Operand& src);
1005 void sqrtsd(XMMRegister dst, XMMRegister src);
1006 void sqrtsd(XMMRegister dst, const Operand& src);
1008 void andpd(XMMRegister dst, XMMRegister src);
1009 void andpd(XMMRegister dst, const Operand& src);
1010 void orpd(XMMRegister dst, XMMRegister src);
1012 void ucomisd(XMMRegister dst, XMMRegister src) { ucomisd(dst, Operand(src)); }
1013 void ucomisd(XMMRegister dst, const Operand& src);
1016 kRoundToNearest = 0x0,
1022 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
1024 void movmskpd(Register dst, XMMRegister src);
1025 void movmskps(Register dst, XMMRegister src);
1027 void cmpltsd(XMMRegister dst, XMMRegister src);
1028 void pcmpeqd(XMMRegister dst, XMMRegister src);
1029 void pcmpgtd(XMMRegister dst, XMMRegister src);
1031 void movdqa(XMMRegister dst, const Operand& src);
1032 void movdqa(const Operand& dst, XMMRegister src);
1033 void movdqu(XMMRegister dst, const Operand& src);
1034 void movdqu(const Operand& dst, XMMRegister src);
1035 void movdq(bool aligned, XMMRegister dst, const Operand& src) {
1043 void movd(XMMRegister dst, Register src) { movd(dst, Operand(src)); }
1044 void movd(XMMRegister dst, const Operand& src);
1045 void movd(Register dst, XMMRegister src) { movd(Operand(dst), src); }
1046 void movd(const Operand& dst, XMMRegister src);
1047 void movsd(XMMRegister dst, XMMRegister src) { movsd(dst, Operand(src)); }
1048 void movsd(XMMRegister dst, const Operand& src);
1049 void movsd(const Operand& dst, XMMRegister src);
1052 void movss(XMMRegister dst, const Operand& src);
1053 void movss(const Operand& dst, XMMRegister src);
1054 void movss(XMMRegister dst, XMMRegister src) { movss(dst, Operand(src)); }
1055 void extractps(Register dst, XMMRegister src, byte imm8);
1057 void pand(XMMRegister dst, XMMRegister src);
1058 void pxor(XMMRegister dst, XMMRegister src);
1059 void por(XMMRegister dst, XMMRegister src);
1060 void ptest(XMMRegister dst, XMMRegister src);
1062 void psllq(XMMRegister reg, int8_t shift);
1063 void psllq(XMMRegister dst, XMMRegister src);
1064 void pslld(XMMRegister reg, int8_t shift);
1065 void pslld(XMMRegister dst, XMMRegister src);
1066 void psrld(XMMRegister reg, int8_t shift);
1067 void psrld(XMMRegister dst, XMMRegister src);
1068 void psrad(XMMRegister reg, int8_t shift);
1069 void psrad(XMMRegister dst, XMMRegister src);
1070 void psrlq(XMMRegister reg, int8_t shift);
1071 void psrlq(XMMRegister dst, XMMRegister src);
1072 void psrldq(XMMRegister dst, int8_t shift);
1073 void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle);
1074 void pextrd(Register dst, XMMRegister src, int8_t offset) {
1075 pextrd(Operand(dst), src, offset);
1077 void pextrd(const Operand& dst, XMMRegister src, int8_t offset);
1078 void pinsrd(XMMRegister dst, Register src, int8_t offset) {
1079 pinsrd(dst, Operand(src), offset);
1081 void pinsrd(XMMRegister dst, const Operand& src, int8_t offset);
1083 // Parallel XMM operations.
1084 void movntdqa(XMMRegister dst, const Operand& src);
1085 void movntdq(const Operand& dst, XMMRegister src);
1086 // Prefetch src position into cache level.
1087 // Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a
1089 void prefetch(const Operand& src, int level);
1090 // TODO(lrn): Need SFENCE for movnt?
1095 // Check the code size generated from label to here.
1096 int SizeOfCodeGeneratedSince(Label* label) {
1097 return pc_offset() - label->pos();
1100 // Mark address of the ExitJSFrame code.
1101 void RecordJSReturn();
1103 // Mark address of a debug break slot.
1104 void RecordDebugBreakSlot();
1106 // Record a comment relocation entry that can be used by a disassembler.
1107 // Use --code-comments to enable, or provide "force = true" flag to always
1109 void RecordComment(const char* msg, bool force = false);
1111 // Writes a single byte or word of data in the code stream. Used for
1112 // inline tables, e.g., jump-tables.
1113 void db(uint8_t data);
1114 void dd(uint32_t data);
1116 // Check if there is less than kGap bytes available in the buffer.
1117 // If this is the case, we need to grow the buffer before emitting
1118 // an instruction or relocation information.
1119 inline bool buffer_overflow() const {
1120 return pc_ >= reloc_info_writer.pos() - kGap;
1123 // Get the number of bytes available in the buffer.
1124 inline int available_space() const { return reloc_info_writer.pos() - pc_; }
1126 static bool IsNop(Address addr);
1128 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1130 int relocation_writer_size() {
1131 return (buffer_ + buffer_size_) - reloc_info_writer.pos();
1134 // Avoid overflows for displacements etc.
1135 static const int kMaximalBufferSize = 512*MB;
1137 byte byte_at(int pos) { return buffer_[pos]; }
1138 void set_byte_at(int pos, byte value) { buffer_[pos] = value; }
1140 // Allocate a constant pool of the correct size for the generated code.
1141 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
1143 // Generate the constant pool for the generated code.
1144 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1147 void emit_sse_operand(XMMRegister reg, const Operand& adr);
1148 void emit_sse_operand(XMMRegister dst, XMMRegister src);
1149 void emit_sse_operand(Register dst, XMMRegister src);
1150 void emit_sse_operand(XMMRegister dst, Register src);
1152 byte* addr_at(int pos) { return buffer_ + pos; }
1156 uint32_t long_at(int pos) {
1157 return *reinterpret_cast<uint32_t*>(addr_at(pos));
1159 void long_at_put(int pos, uint32_t x) {
1160 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
1165 inline void emit(uint32_t x);
1166 inline void emit(Handle<Object> handle);
1167 inline void emit(uint32_t x,
1168 RelocInfo::Mode rmode,
1169 TypeFeedbackId id = TypeFeedbackId::None());
1170 inline void emit(Handle<Code> code,
1171 RelocInfo::Mode rmode,
1172 TypeFeedbackId id = TypeFeedbackId::None());
1173 inline void emit(const Immediate& x);
1174 inline void emit_w(const Immediate& x);
1176 // Emit the code-object-relative offset of the label's position
1177 inline void emit_code_relative_offset(Label* label);
1179 // instruction generation
1180 void emit_arith_b(int op1, int op2, Register dst, int imm8);
1182 // Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81)
1183 // with a given destination expression and an immediate operand. It attempts
1184 // to use the shortest encoding possible.
1185 // sel specifies the /n in the modrm byte (see the Intel PRM).
1186 void emit_arith(int sel, Operand dst, const Immediate& x);
1188 void emit_operand(Register reg, const Operand& adr);
1190 void emit_farith(int b1, int b2, int i);
1193 void print(Label* L);
1194 void bind_to(Label* L, int pos);
1197 inline Displacement disp_at(Label* L);
1198 inline void disp_at_put(Label* L, Displacement disp);
1199 inline void emit_disp(Label* L, Displacement::Type type);
1200 inline void emit_near_disp(Label* L);
1202 // record reloc info for current pc_
1203 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1205 friend class CodePatcher;
1206 friend class EnsureSpace;
1209 RelocInfoWriter reloc_info_writer;
1211 PositionsRecorder positions_recorder_;
1212 friend class PositionsRecorder;
1216 // Helper class that ensures that there is enough space for generating
1217 // instructions and relocation information. The constructor makes
1218 // sure that there is enough space and (in debug mode) the destructor
1219 // checks that we did not generate too much.
1220 class EnsureSpace BASE_EMBEDDED {
1222 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
1223 if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
1225 space_before_ = assembler_->available_space();
1231 int bytes_generated = space_before_ - assembler_->available_space();
1232 ASSERT(bytes_generated < assembler_->kGap);
1237 Assembler* assembler_;
1243 } } // namespace v8::internal
1245 #endif // V8_IA32_ASSEMBLER_IA32_H_