1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
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5 // modification, are permitted provided that the following conditions are
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9 // this list of conditions and the following disclaimer.
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29 // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 // The original source code covered by the above license above has been
32 // modified significantly by Google Inc.
33 // Copyright 2011 the V8 project authors. All rights reserved.
35 // A light-weight IA32 Assembler.
37 #ifndef V8_IA32_ASSEMBLER_IA32_H_
38 #define V8_IA32_ASSEMBLER_IA32_H_
40 #include "src/isolate.h"
41 #include "src/serialize.h"
48 // 1) We would prefer to use an enum, but enum values are assignment-
49 // compatible with int, which has caused code-generation bugs.
51 // 2) We would prefer to use a class instead of a struct but we don't like
52 // the register initialization to depend on the particular initialization
53 // order (which appears to be different on OS X, Linux, and Windows for the
54 // installed versions of C++ we tried). Using a struct permits C-style
55 // "initialization". Also, the Register objects cannot be const as this
56 // forces initialization stubs in MSVC, making us dependent on initialization
59 // 3) By not using an enum, we are possibly preventing the compiler from
60 // doing certain constant folds, which may significantly reduce the
61 // code generated for some assembly instructions (because they boil down
62 // to a few constants). If this is a problem, we could change the code
63 // such that we use an enum in optimized mode, and the struct in debug
64 // mode. This way we get the compile-time error checking in debug mode
65 // and best performance in optimized code.
68 static const int kMaxNumAllocatableRegisters = 6;
69 static int NumAllocatableRegisters() {
70 return kMaxNumAllocatableRegisters;
72 static const int kNumRegisters = 8;
74 static inline const char* AllocationIndexToString(int index);
76 static inline int ToAllocationIndex(Register reg);
78 static inline Register FromAllocationIndex(int index);
80 static Register from_code(int code) {
82 DCHECK(code < kNumRegisters);
83 Register r = { code };
86 bool is_valid() const { return 0 <= code_ && code_ < kNumRegisters; }
87 bool is(Register reg) const { return code_ == reg.code_; }
88 // eax, ebx, ecx and edx are byte registers, the rest are not.
89 bool is_byte_register() const { return code_ <= 3; }
99 // Unfortunately we can't make this private in a struct.
103 const int kRegister_eax_Code = 0;
104 const int kRegister_ecx_Code = 1;
105 const int kRegister_edx_Code = 2;
106 const int kRegister_ebx_Code = 3;
107 const int kRegister_esp_Code = 4;
108 const int kRegister_ebp_Code = 5;
109 const int kRegister_esi_Code = 6;
110 const int kRegister_edi_Code = 7;
111 const int kRegister_no_reg_Code = -1;
113 const Register eax = { kRegister_eax_Code };
114 const Register ecx = { kRegister_ecx_Code };
115 const Register edx = { kRegister_edx_Code };
116 const Register ebx = { kRegister_ebx_Code };
117 const Register esp = { kRegister_esp_Code };
118 const Register ebp = { kRegister_ebp_Code };
119 const Register esi = { kRegister_esi_Code };
120 const Register edi = { kRegister_edi_Code };
121 const Register no_reg = { kRegister_no_reg_Code };
124 inline const char* Register::AllocationIndexToString(int index) {
125 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
126 // This is the mapping of allocation indices to registers.
127 const char* const kNames[] = { "eax", "ecx", "edx", "ebx", "esi", "edi" };
128 return kNames[index];
132 inline int Register::ToAllocationIndex(Register reg) {
133 DCHECK(reg.is_valid() && !reg.is(esp) && !reg.is(ebp));
134 return (reg.code() >= 6) ? reg.code() - 2 : reg.code();
138 inline Register Register::FromAllocationIndex(int index) {
139 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
140 return (index >= 4) ? from_code(index + 2) : from_code(index);
145 static const int kMaxNumAllocatableRegisters = 7;
146 static const int kMaxNumRegisters = 8;
147 static int NumAllocatableRegisters() {
148 return kMaxNumAllocatableRegisters;
151 static int ToAllocationIndex(XMMRegister reg) {
152 DCHECK(reg.code() != 0);
153 return reg.code() - 1;
156 static XMMRegister FromAllocationIndex(int index) {
157 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
158 return from_code(index + 1);
161 static XMMRegister from_code(int code) {
162 XMMRegister result = { code };
166 bool is_valid() const {
167 return 0 <= code_ && code_ < kMaxNumRegisters;
175 bool is(XMMRegister reg) const { return code_ == reg.code_; }
177 static const char* AllocationIndexToString(int index) {
178 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters);
179 const char* const names[] = {
195 typedef XMMRegister DoubleRegister;
196 typedef XMMRegister SIMD128Register;
198 const XMMRegister xmm0 = { 0 };
199 const XMMRegister xmm1 = { 1 };
200 const XMMRegister xmm2 = { 2 };
201 const XMMRegister xmm3 = { 3 };
202 const XMMRegister xmm4 = { 4 };
203 const XMMRegister xmm5 = { 5 };
204 const XMMRegister xmm6 = { 6 };
205 const XMMRegister xmm7 = { 7 };
206 const XMMRegister no_xmm_reg = { -1 };
210 // any value < 0 is considered no_condition
232 not_carry = above_equal,
234 not_zero = not_equal,
240 // Returns the equivalent of !cc.
241 // Negation of the default no_condition (-1) results in a non-default
242 // no_condition value (-2). As long as tests for no_condition check
243 // for condition < 0, this will work as expected.
244 inline Condition NegateCondition(Condition cc) {
245 return static_cast<Condition>(cc ^ 1);
249 // Commute a condition such that {a cond b == b cond' a}.
250 inline Condition CommuteCondition(Condition cc) {
267 return greater_equal;
274 // -----------------------------------------------------------------------------
275 // Machine instruction Immediates
277 class Immediate BASE_EMBEDDED {
279 inline explicit Immediate(int x);
280 inline explicit Immediate(const ExternalReference& ext);
281 inline explicit Immediate(Handle<Object> handle);
282 inline explicit Immediate(Smi* value);
283 inline explicit Immediate(Address addr);
285 static Immediate CodeRelativeOffset(Label* label) {
286 return Immediate(label);
289 bool is_zero() const { return x_ == 0 && RelocInfo::IsNone(rmode_); }
290 bool is_int8() const {
291 return -128 <= x_ && x_ < 128 && RelocInfo::IsNone(rmode_);
293 bool is_int16() const {
294 return -32768 <= x_ && x_ < 32768 && RelocInfo::IsNone(rmode_);
298 inline explicit Immediate(Label* value);
301 RelocInfo::Mode rmode_;
303 friend class Operand;
304 friend class Assembler;
305 friend class MacroAssembler;
309 // -----------------------------------------------------------------------------
310 // Machine instruction Operands
317 maximal_scale_factor = times_8,
318 times_int_size = times_4,
319 times_half_pointer_size = times_2,
320 times_pointer_size = times_4,
321 times_twice_pointer_size = times_8
325 class Operand BASE_EMBEDDED {
328 INLINE(explicit Operand(Register reg));
331 INLINE(explicit Operand(XMMRegister xmm_reg));
334 INLINE(explicit Operand(int32_t disp, RelocInfo::Mode rmode));
337 INLINE(explicit Operand(Immediate imm));
340 explicit Operand(Register base, int32_t disp,
341 RelocInfo::Mode rmode = RelocInfo::NONE32);
343 // [base + index*scale + disp/r]
344 explicit Operand(Register base,
348 RelocInfo::Mode rmode = RelocInfo::NONE32);
350 // [index*scale + disp/r]
351 explicit Operand(Register index,
354 RelocInfo::Mode rmode = RelocInfo::NONE32);
356 // Offset from existing memory operand.
357 // Offset is added to existing displacement as 32-bit signed values and
358 // this must not overflow.
359 Operand(const Operand& base, int32_t offset);
361 static Operand StaticVariable(const ExternalReference& ext) {
362 return Operand(reinterpret_cast<int32_t>(ext.address()),
363 RelocInfo::EXTERNAL_REFERENCE);
366 static Operand StaticArray(Register index,
368 const ExternalReference& arr) {
369 return Operand(index, scale, reinterpret_cast<int32_t>(arr.address()),
370 RelocInfo::EXTERNAL_REFERENCE);
373 static Operand ForCell(Handle<Cell> cell) {
374 AllowDeferredHandleDereference embedding_raw_address;
375 return Operand(reinterpret_cast<int32_t>(cell.location()),
379 static Operand ForRegisterPlusImmediate(Register base, Immediate imm) {
380 return Operand(base, imm.x_, imm.rmode_);
383 // Returns true if this Operand is a wrapper for the specified register.
384 bool is_reg(Register reg) const;
386 // Returns true if this Operand is a wrapper for one register.
387 bool is_reg_only() const;
389 // Asserts that this Operand is a wrapper for one register and returns the
391 Register reg() const;
394 // Set the ModRM byte without an encoded 'reg' register. The
395 // register is encoded later as part of the emit_operand operation.
396 inline void set_modrm(int mod, Register rm);
398 inline void set_sib(ScaleFactor scale, Register index, Register base);
399 inline void set_disp8(int8_t disp);
400 inline void set_dispr(int32_t disp, RelocInfo::Mode rmode);
403 // The number of bytes in buf_.
405 // Only valid if len_ > 4.
406 RelocInfo::Mode rmode_;
408 friend class Assembler;
409 friend class MacroAssembler;
413 // -----------------------------------------------------------------------------
414 // A Displacement describes the 32bit immediate field of an instruction which
415 // may be used together with a Label in order to refer to a yet unknown code
416 // position. Displacements stored in the instruction stream are used to describe
417 // the instruction and to chain a list of instructions using the same Label.
418 // A Displacement contains 2 different fields:
420 // next field: position of next displacement in the chain (0 = end of list)
421 // type field: instruction type
423 // A next value of null (0) indicates the end of a chain (note that there can
424 // be no displacement at position zero, because there is always at least one
425 // instruction byte before the displacement).
427 // Displacement _data field layout
429 // |31.....2|1......0|
432 class Displacement BASE_EMBEDDED {
440 int data() const { return data_; }
441 Type type() const { return TypeField::decode(data_); }
442 void next(Label* L) const {
443 int n = NextField::decode(data_);
444 n > 0 ? L->link_to(n) : L->Unuse();
446 void link_to(Label* L) { init(L, type()); }
448 explicit Displacement(int data) { data_ = data; }
450 Displacement(Label* L, Type type) { init(L, type); }
453 PrintF("%s (%x) ", (type() == UNCONDITIONAL_JUMP ? "jmp" : "[other]"),
454 NextField::decode(data_));
460 class TypeField: public BitField<Type, 0, 2> {};
461 class NextField: public BitField<int, 2, 32-2> {};
463 void init(Label* L, Type type);
467 class Assembler : public AssemblerBase {
469 // We check before assembling an instruction that there is sufficient
470 // space to write an instruction and its relocation information.
471 // The relocation writer's position must be kGap bytes above the end of
472 // the generated instructions. This leaves enough space for the
473 // longest possible ia32 instruction, 15 bytes, and the longest possible
474 // relocation information encoding, RelocInfoWriter::kMaxLength == 16.
475 // (There is a 15 byte limit on ia32 instruction length that rules out some
476 // otherwise valid instructions.)
477 // This allows for a single, fast space check per instruction.
478 static const int kGap = 32;
481 // Create an assembler. Instructions and relocation information are emitted
482 // into a buffer, with the instructions starting from the beginning and the
483 // relocation information starting from the end of the buffer. See CodeDesc
484 // for a detailed comment on the layout (globals.h).
486 // If the provided buffer is NULL, the assembler allocates and grows its own
487 // buffer, and buffer_size determines the initial buffer size. The buffer is
488 // owned by the assembler and deallocated upon destruction of the assembler.
490 // If the provided buffer is not NULL, the assembler uses the provided buffer
491 // for code generation and assumes its size to be buffer_size. If the buffer
492 // is too small, a fatal error occurs. No deallocation of the buffer is done
493 // upon destruction of the assembler.
494 // TODO(vitalyr): the assembler does not need an isolate.
495 Assembler(Isolate* isolate, void* buffer, int buffer_size);
496 virtual ~Assembler() { }
498 // GetCode emits any pending (non-emitted) code and fills the descriptor
499 // desc. GetCode() is idempotent; it returns the same result if no other
500 // Assembler functions are invoked in between GetCode() calls.
501 void GetCode(CodeDesc* desc);
503 // Read/Modify the code target in the branch/call instruction at pc.
504 inline static Address target_address_at(Address pc,
505 ConstantPoolArray* constant_pool);
506 inline static void set_target_address_at(Address pc,
507 ConstantPoolArray* constant_pool,
509 ICacheFlushMode icache_flush_mode =
510 FLUSH_ICACHE_IF_NEEDED);
511 static inline Address target_address_at(Address pc, Code* code) {
512 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
513 return target_address_at(pc, constant_pool);
515 static inline void set_target_address_at(Address pc,
518 ICacheFlushMode icache_flush_mode =
519 FLUSH_ICACHE_IF_NEEDED) {
520 ConstantPoolArray* constant_pool = code ? code->constant_pool() : NULL;
521 set_target_address_at(pc, constant_pool, target);
524 // Return the code target address at a call site from the return address
525 // of that call in the instruction stream.
526 inline static Address target_address_from_return_address(Address pc);
528 // Return the code target address of the patch debug break slot
529 inline static Address break_address_from_return_address(Address pc);
531 // This sets the branch destination (which is in the instruction on x86).
532 // This is for calls and branches within generated code.
533 inline static void deserialization_set_special_target_at(
534 Address instruction_payload, Code* code, Address target) {
535 set_target_address_at(instruction_payload, code, target);
538 static const int kSpecialTargetSize = kPointerSize;
540 // Distance between the address of the code target in the call instruction
541 // and the return address
542 static const int kCallTargetAddressOffset = kPointerSize;
543 // Distance between start of patched return sequence and the emitted address
545 static const int kPatchReturnSequenceAddressOffset = 1; // JMP imm32.
547 // Distance between start of patched debug break slot and the emitted address
549 static const int kPatchDebugBreakSlotAddressOffset = 1; // JMP imm32.
551 static const int kCallInstructionLength = 5;
552 static const int kPatchDebugBreakSlotReturnOffset = kPointerSize;
553 static const int kJSReturnSequenceLength = 6;
555 // The debug break slot must be able to contain a call instruction.
556 static const int kDebugBreakSlotLength = kCallInstructionLength;
558 // One byte opcode for test al, 0xXX.
559 static const byte kTestAlByte = 0xA8;
560 // One byte opcode for nop.
561 static const byte kNopByte = 0x90;
563 // One byte opcode for a short unconditional jump.
564 static const byte kJmpShortOpcode = 0xEB;
565 // One byte prefix for a short conditional jump.
566 static const byte kJccShortPrefix = 0x70;
567 static const byte kJncShortOpcode = kJccShortPrefix | not_carry;
568 static const byte kJcShortOpcode = kJccShortPrefix | carry;
569 static const byte kJnzShortOpcode = kJccShortPrefix | not_zero;
570 static const byte kJzShortOpcode = kJccShortPrefix | zero;
573 // ---------------------------------------------------------------------------
576 // - function names correspond one-to-one to ia32 instruction mnemonics
577 // - unless specified otherwise, instructions operate on 32bit operands
578 // - instructions on 8bit (byte) operands/registers have a trailing '_b'
579 // - instructions on 16bit (word) operands/registers have a trailing '_w'
580 // - naming conflicts with C++ keywords are resolved via a trailing '_'
582 // NOTE ON INTERFACE: Currently, the interface is not very consistent
583 // in the sense that some operations (e.g. mov()) can be called in more
584 // the one way to generate the same instruction: The Register argument
585 // can in some cases be replaced with an Operand(Register) argument.
586 // This should be cleaned up and made more orthogonal. The questions
587 // is: should we always use Operands instead of Registers where an
588 // Operand is possible, or should we have a Register (overloaded) form
589 // instead? We must be careful to make sure that the selected instruction
590 // is obvious from the parameters to avoid hard-to-find code generation
593 // Insert the smallest number of nop instructions
594 // possible to align the pc offset to a multiple
595 // of m. m must be a power of 2.
597 void Nop(int bytes = 1);
598 // Aligns code to something that's optimal for a jump target for the platform.
599 void CodeTargetAlign();
608 void push(const Immediate& x);
609 void push_imm32(int32_t imm32);
610 void push(Register src);
611 void push(const Operand& src);
613 void pop(Register dst);
614 void pop(const Operand& dst);
616 void enter(const Immediate& size);
620 void mov_b(Register dst, Register src) { mov_b(dst, Operand(src)); }
621 void mov_b(Register dst, const Operand& src);
622 void mov_b(Register dst, int8_t imm8) { mov_b(Operand(dst), imm8); }
623 void mov_b(const Operand& dst, int8_t imm8);
624 void mov_b(const Operand& dst, Register src);
626 void mov_w(Register dst, const Operand& src);
627 void mov_w(const Operand& dst, Register src);
628 void mov_w(const Operand& dst, int16_t imm16);
630 void mov(Register dst, int32_t imm32);
631 void mov(Register dst, const Immediate& x);
632 void mov(Register dst, Handle<Object> handle);
633 void mov(Register dst, const Operand& src);
634 void mov(Register dst, Register src);
635 void mov(const Operand& dst, const Immediate& x);
636 void mov(const Operand& dst, Handle<Object> handle);
637 void mov(const Operand& dst, Register src);
639 void movsx_b(Register dst, Register src) { movsx_b(dst, Operand(src)); }
640 void movsx_b(Register dst, const Operand& src);
642 void movsx_w(Register dst, Register src) { movsx_w(dst, Operand(src)); }
643 void movsx_w(Register dst, const Operand& src);
645 void movzx_b(Register dst, Register src) { movzx_b(dst, Operand(src)); }
646 void movzx_b(Register dst, const Operand& src);
648 void movzx_w(Register dst, Register src) { movzx_w(dst, Operand(src)); }
649 void movzx_w(Register dst, const Operand& src);
652 void cmov(Condition cc, Register dst, Register src) {
653 cmov(cc, dst, Operand(src));
655 void cmov(Condition cc, Register dst, const Operand& src);
660 // Repetitive string instructions.
666 void xchg(Register dst, Register src);
667 void xchg(Register dst, const Operand& src);
670 void adc(Register dst, int32_t imm32);
671 void adc(Register dst, const Operand& src);
673 void add(Register dst, Register src) { add(dst, Operand(src)); }
674 void add(Register dst, const Operand& src);
675 void add(const Operand& dst, Register src);
676 void add(Register dst, const Immediate& imm) { add(Operand(dst), imm); }
677 void add(const Operand& dst, const Immediate& x);
679 void and_(Register dst, int32_t imm32);
680 void and_(Register dst, const Immediate& x);
681 void and_(Register dst, Register src) { and_(dst, Operand(src)); }
682 void and_(Register dst, const Operand& src);
683 void and_(const Operand& dst, Register src);
684 void and_(const Operand& dst, const Immediate& x);
686 void cmpb(Register reg, int8_t imm8) { cmpb(Operand(reg), imm8); }
687 void cmpb(const Operand& op, int8_t imm8);
688 void cmpb(Register reg, const Operand& op);
689 void cmpb(const Operand& op, Register reg);
690 void cmpb_al(const Operand& op);
691 void cmpw_ax(const Operand& op);
692 void cmpw(const Operand& op, Immediate imm16);
693 void cmp(Register reg, int32_t imm32);
694 void cmp(Register reg, Handle<Object> handle);
695 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); }
696 void cmp(Register reg, const Operand& op);
697 void cmp(Register reg, const Immediate& imm) { cmp(Operand(reg), imm); }
698 void cmp(const Operand& op, const Immediate& imm);
699 void cmp(const Operand& op, Handle<Object> handle);
701 void dec_b(Register dst);
702 void dec_b(const Operand& dst);
704 void dec(Register dst);
705 void dec(const Operand& dst);
709 void idiv(Register src) { idiv(Operand(src)); }
710 void idiv(const Operand& src);
711 void div(Register src) { div(Operand(src)); }
712 void div(const Operand& src);
714 // Signed multiply instructions.
715 void imul(Register src); // edx:eax = eax * src.
716 void imul(Register dst, Register src) { imul(dst, Operand(src)); }
717 void imul(Register dst, const Operand& src); // dst = dst * src.
718 void imul(Register dst, Register src, int32_t imm32); // dst = src * imm32.
719 void imul(Register dst, const Operand& src, int32_t imm32);
721 void inc(Register dst);
722 void inc(const Operand& dst);
724 void lea(Register dst, const Operand& src);
726 // Unsigned multiply instruction.
727 void mul(Register src); // edx:eax = eax * reg.
729 void neg(Register dst);
730 void neg(const Operand& dst);
732 void not_(Register dst);
733 void not_(const Operand& dst);
735 void or_(Register dst, int32_t imm32);
736 void or_(Register dst, Register src) { or_(dst, Operand(src)); }
737 void or_(Register dst, const Operand& src);
738 void or_(const Operand& dst, Register src);
739 void or_(Register dst, const Immediate& imm) { or_(Operand(dst), imm); }
740 void or_(const Operand& dst, const Immediate& x);
742 void rcl(Register dst, uint8_t imm8);
743 void rcr(Register dst, uint8_t imm8);
744 void ror(Register dst, uint8_t imm8);
745 void ror_cl(Register dst);
747 void sar(Register dst, uint8_t imm8) { sar(Operand(dst), imm8); }
748 void sar(const Operand& dst, uint8_t imm8);
749 void sar_cl(Register dst) { sar_cl(Operand(dst)); }
750 void sar_cl(const Operand& dst);
752 void sbb(Register dst, const Operand& src);
754 void shld(Register dst, Register src) { shld(dst, Operand(src)); }
755 void shld(Register dst, const Operand& src);
757 void shl(Register dst, uint8_t imm8) { shl(Operand(dst), imm8); }
758 void shl(const Operand& dst, uint8_t imm8);
759 void shl_cl(Register dst) { shl_cl(Operand(dst)); }
760 void shl_cl(const Operand& dst);
762 void shrd(Register dst, Register src) { shrd(dst, Operand(src)); }
763 void shrd(Register dst, const Operand& src);
765 void shr(Register dst, uint8_t imm8) { shr(Operand(dst), imm8); }
766 void shr(const Operand& dst, uint8_t imm8);
767 void shr_cl(Register dst) { shr_cl(Operand(dst)); }
768 void shr_cl(const Operand& dst);
770 void sub(Register dst, const Immediate& imm) { sub(Operand(dst), imm); }
771 void sub(const Operand& dst, const Immediate& x);
772 void sub(Register dst, Register src) { sub(dst, Operand(src)); }
773 void sub(Register dst, const Operand& src);
774 void sub(const Operand& dst, Register src);
776 void test(Register reg, const Immediate& imm);
777 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); }
778 void test(Register reg, const Operand& op);
779 void test_b(Register reg, const Operand& op);
780 void test(const Operand& op, const Immediate& imm);
781 void test_b(Register reg, uint8_t imm8);
782 void test_b(const Operand& op, uint8_t imm8);
784 void xor_(Register dst, int32_t imm32);
785 void xor_(Register dst, Register src) { xor_(dst, Operand(src)); }
786 void xor_(Register dst, const Operand& src);
787 void xor_(const Operand& dst, Register src);
788 void xor_(Register dst, const Immediate& imm) { xor_(Operand(dst), imm); }
789 void xor_(const Operand& dst, const Immediate& x);
792 void bt(const Operand& dst, Register src);
793 void bts(Register dst, Register src) { bts(Operand(dst), src); }
794 void bts(const Operand& dst, Register src);
795 void bsr(Register dst, Register src) { bsr(dst, Operand(src)); }
796 void bsr(Register dst, const Operand& src);
804 // Label operations & relative jumps (PPUM Appendix D)
806 // Takes a branch opcode (cc) and a label (L) and generates
807 // either a backward branch or a forward branch and links it
808 // to the label fixup chain. Usage:
810 // Label L; // unbound label
811 // j(cc, &L); // forward branch to unbound label
812 // bind(&L); // bind label to the current pc
813 // j(cc, &L); // backward branch to bound label
814 // bind(&L); // illegal: a label may be bound only once
816 // Note: The same Label can be used for forward and backward branches
817 // but it may be bound only once.
819 void bind(Label* L); // binds an unbound label L to the current code position
823 void call(byte* entry, RelocInfo::Mode rmode);
824 int CallSize(const Operand& adr);
825 void call(Register reg) { call(Operand(reg)); }
826 void call(const Operand& adr);
827 int CallSize(Handle<Code> code, RelocInfo::Mode mode);
828 void call(Handle<Code> code,
829 RelocInfo::Mode rmode,
830 TypeFeedbackId id = TypeFeedbackId::None());
833 // unconditional jump to L
834 void jmp(Label* L, Label::Distance distance = Label::kFar);
835 void jmp(byte* entry, RelocInfo::Mode rmode);
836 void jmp(Register reg) { jmp(Operand(reg)); }
837 void jmp(const Operand& adr);
838 void jmp(Handle<Code> code, RelocInfo::Mode rmode);
843 Label::Distance distance = Label::kFar);
844 void j(Condition cc, byte* entry, RelocInfo::Mode rmode);
845 void j(Condition cc, Handle<Code> code);
847 // Floating-point operations
856 void fld_s(const Operand& adr);
857 void fld_d(const Operand& adr);
859 void fstp_s(const Operand& adr);
860 void fst_s(const Operand& adr);
861 void fstp_d(const Operand& adr);
862 void fst_d(const Operand& adr);
864 void fild_s(const Operand& adr);
865 void fild_d(const Operand& adr);
867 void fist_s(const Operand& adr);
869 void fistp_s(const Operand& adr);
870 void fistp_d(const Operand& adr);
872 // The fisttp instructions require SSE3.
873 void fisttp_s(const Operand& adr);
874 void fisttp_d(const Operand& adr);
895 void fisub_s(const Operand& adr);
897 void faddp(int i = 1);
898 void fsubp(int i = 1);
899 void fsubrp(int i = 1);
900 void fmulp(int i = 1);
901 void fdivp(int i = 1);
905 void fxch(int i = 1);
907 void ffree(int i = 0);
922 void setcc(Condition cc, Register reg);
927 void movaps(XMMRegister dst, XMMRegister src);
928 void movups(XMMRegister dst, const Operand& src);
929 void movups(const Operand& dst, XMMRegister src);
930 void shufps(XMMRegister dst, XMMRegister src, byte imm8);
931 void shufpd(XMMRegister dst, XMMRegister src, byte imm8);
933 void andps(XMMRegister dst, const Operand& src);
934 void andps(XMMRegister dst, XMMRegister src) { andps(dst, Operand(src)); }
935 void xorps(XMMRegister dst, const Operand& src);
936 void xorps(XMMRegister dst, XMMRegister src) { xorps(dst, Operand(src)); }
937 void orps(XMMRegister dst, const Operand& src);
938 void orps(XMMRegister dst, XMMRegister src) { orps(dst, Operand(src)); }
940 void addps(XMMRegister dst, const Operand& src);
941 void addps(XMMRegister dst, XMMRegister src) { addps(dst, Operand(src)); }
942 void subps(XMMRegister dst, const Operand& src);
943 void subps(XMMRegister dst, XMMRegister src) { subps(dst, Operand(src)); }
944 void mulps(XMMRegister dst, const Operand& src);
945 void mulps(XMMRegister dst, XMMRegister src) { mulps(dst, Operand(src)); }
946 void divps(XMMRegister dst, const Operand& src);
947 void divps(XMMRegister dst, XMMRegister src) { divps(dst, Operand(src)); }
948 void minps(XMMRegister dst, XMMRegister src) { minps(dst, Operand(src)); }
949 void minps(XMMRegister dst, const Operand& src);
950 void maxps(XMMRegister dst, XMMRegister src) { maxps(dst, Operand(src)); }
951 void maxps(XMMRegister dst, const Operand& src);
952 void rcpps(XMMRegister dst, XMMRegister src) { rcpps(dst, Operand(src)); }
953 void rcpps(XMMRegister dst, const Operand& src);
954 void rsqrtps(XMMRegister dst, XMMRegister src) { rsqrtps(dst, Operand(src)); }
955 void rsqrtps(XMMRegister dst, const Operand& src);
956 void sqrtps(XMMRegister dst, XMMRegister src) { sqrtps(dst, Operand(src)); }
957 void sqrtps(XMMRegister dst, const Operand& src);
958 void sqrtpd(XMMRegister dst, XMMRegister src) { sqrtpd(dst, Operand(src)); }
959 void sqrtpd(XMMRegister dst, const Operand& src);
961 void addpd(XMMRegister dst, const Operand& src);
962 void addpd(XMMRegister dst, XMMRegister src) { addpd(dst, Operand(src)); }
963 void subpd(XMMRegister dst, const Operand& src);
964 void subpd(XMMRegister dst, XMMRegister src) { subpd(dst, Operand(src)); }
965 void mulpd(XMMRegister dst, const Operand& src);
966 void mulpd(XMMRegister dst, XMMRegister src) { mulpd(dst, Operand(src)); }
967 void divpd(XMMRegister dst, const Operand& src);
968 void divpd(XMMRegister dst, XMMRegister src) { divpd(dst, Operand(src)); }
969 void minpd(XMMRegister dst, XMMRegister src) { minpd(dst, Operand(src)); }
970 void minpd(XMMRegister dst, const Operand& src);
971 void maxpd(XMMRegister dst, XMMRegister src) { maxpd(dst, Operand(src)); }
972 void maxpd(XMMRegister dst, const Operand& src);
974 void cvtdq2ps(XMMRegister dst, const Operand& src);
975 void cmpps(XMMRegister dst, XMMRegister src, int8_t cmp);
976 void cmpeqps(XMMRegister dst, XMMRegister src);
977 void cmpltps(XMMRegister dst, XMMRegister src);
978 void cmpleps(XMMRegister dst, XMMRegister src);
979 void cmpneqps(XMMRegister dst, XMMRegister src);
980 void cmpnltps(XMMRegister dst, XMMRegister src);
981 void cmpnleps(XMMRegister dst, XMMRegister src);
983 // SSE 2, introduced by SIMD
984 void paddd(XMMRegister dst, XMMRegister src) { paddd(dst, Operand(src)); }
985 void paddd(XMMRegister dst, const Operand& src);
986 void psubd(XMMRegister dst, XMMRegister src) { psubd(dst, Operand(src)); }
987 void psubd(XMMRegister dst, const Operand& src);
988 void pmuludq(XMMRegister dst, XMMRegister src) { pmuludq(dst, Operand(src)); }
989 void pmuludq(XMMRegister dst, const Operand& src);
990 void punpackldq(XMMRegister dst, XMMRegister src) {
991 punpackldq(dst, Operand(src));
993 void punpackldq(XMMRegister dst, const Operand& src);
994 void cvtps2dq(XMMRegister dst, XMMRegister src) {
995 cvtps2dq(dst, Operand(src));
997 void cvtps2dq(XMMRegister dst, const Operand& src);
998 void cvtdq2ps(XMMRegister dst, XMMRegister src) {
999 cvtdq2ps(dst, Operand(src));
1001 // SSE 4.1, introduced by SIMD
1002 void insertps(XMMRegister dst, XMMRegister src, byte imm8);
1003 void pmulld(XMMRegister dst, XMMRegister src) { pmulld(dst, Operand(src)); }
1004 void pmulld(XMMRegister dst, const Operand& src);
1006 // SSE2 instructions
1007 void cvttss2si(Register dst, const Operand& src);
1008 void cvttss2si(Register dst, XMMRegister src) {
1009 cvttss2si(dst, Operand(src));
1011 void cvttsd2si(Register dst, const Operand& src);
1012 void cvttsd2si(Register dst, XMMRegister src) {
1013 cvttsd2si(dst, Operand(src));
1015 void cvtsd2si(Register dst, XMMRegister src);
1017 void cvtsi2sd(XMMRegister dst, Register src) { cvtsi2sd(dst, Operand(src)); }
1018 void cvtsi2sd(XMMRegister dst, const Operand& src);
1019 void cvtss2sd(XMMRegister dst, XMMRegister src);
1020 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1022 void addsd(XMMRegister dst, XMMRegister src);
1023 void addsd(XMMRegister dst, const Operand& src);
1024 void subsd(XMMRegister dst, XMMRegister src);
1025 void mulsd(XMMRegister dst, XMMRegister src);
1026 void mulsd(XMMRegister dst, const Operand& src);
1027 void divsd(XMMRegister dst, XMMRegister src);
1028 void xorpd(XMMRegister dst, XMMRegister src);
1029 void xorpd(XMMRegister dst, const Operand& src);
1030 void sqrtsd(XMMRegister dst, XMMRegister src);
1031 void sqrtsd(XMMRegister dst, const Operand& src);
1033 void andpd(XMMRegister dst, XMMRegister src);
1034 void andpd(XMMRegister dst, const Operand& src);
1035 void orpd(XMMRegister dst, XMMRegister src);
1037 void ucomisd(XMMRegister dst, XMMRegister src) { ucomisd(dst, Operand(src)); }
1038 void ucomisd(XMMRegister dst, const Operand& src);
1041 kRoundToNearest = 0x0,
1047 void roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode);
1049 void movmskpd(Register dst, XMMRegister src);
1050 void movmskps(Register dst, XMMRegister src);
1052 void cmpltsd(XMMRegister dst, XMMRegister src);
1053 void pcmpeqd(XMMRegister dst, XMMRegister src);
1054 void pcmpgtd(XMMRegister dst, XMMRegister src);
1056 void movdqa(XMMRegister dst, const Operand& src);
1057 void movdqa(const Operand& dst, XMMRegister src);
1058 void movdqu(XMMRegister dst, const Operand& src);
1059 void movdqu(const Operand& dst, XMMRegister src);
1060 void movdq(bool aligned, XMMRegister dst, const Operand& src) {
1068 void movd(XMMRegister dst, Register src) { movd(dst, Operand(src)); }
1069 void movd(XMMRegister dst, const Operand& src);
1070 void movd(Register dst, XMMRegister src) { movd(Operand(dst), src); }
1071 void movd(const Operand& dst, XMMRegister src);
1072 void movsd(XMMRegister dst, XMMRegister src) { movsd(dst, Operand(src)); }
1073 void movsd(XMMRegister dst, const Operand& src);
1074 void movsd(const Operand& dst, XMMRegister src);
1077 void movss(XMMRegister dst, const Operand& src);
1078 void movss(const Operand& dst, XMMRegister src);
1079 void movss(XMMRegister dst, XMMRegister src) { movss(dst, Operand(src)); }
1080 void extractps(Register dst, XMMRegister src, byte imm8);
1082 void pand(XMMRegister dst, XMMRegister src);
1083 void pxor(XMMRegister dst, XMMRegister src);
1084 void por(XMMRegister dst, XMMRegister src);
1085 void ptest(XMMRegister dst, XMMRegister src);
1087 void psllq(XMMRegister reg, int8_t shift);
1088 void psllq(XMMRegister dst, XMMRegister src);
1089 void pslld(XMMRegister reg, int8_t shift);
1090 void pslld(XMMRegister dst, XMMRegister src);
1091 void psrld(XMMRegister reg, int8_t shift);
1092 void psrld(XMMRegister dst, XMMRegister src);
1093 void psrad(XMMRegister reg, int8_t shift);
1094 void psrad(XMMRegister dst, XMMRegister src);
1095 void psrlq(XMMRegister reg, int8_t shift);
1096 void psrlq(XMMRegister dst, XMMRegister src);
1097 void psrldq(XMMRegister dst, int8_t shift);
1098 void pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle);
1099 void pextrd(Register dst, XMMRegister src, int8_t offset) {
1100 pextrd(Operand(dst), src, offset);
1102 void pextrd(const Operand& dst, XMMRegister src, int8_t offset);
1103 void pinsrd(XMMRegister dst, Register src, int8_t offset) {
1104 pinsrd(dst, Operand(src), offset);
1106 void pinsrd(XMMRegister dst, const Operand& src, int8_t offset);
1108 // Parallel XMM operations.
1109 void movntdqa(XMMRegister dst, const Operand& src);
1110 void movntdq(const Operand& dst, XMMRegister src);
1111 // Prefetch src position into cache level.
1112 // Level 1, 2 or 3 specifies CPU cache level. Level 0 specifies a
1114 void prefetch(const Operand& src, int level);
1115 // TODO(lrn): Need SFENCE for movnt?
1120 // Check the code size generated from label to here.
1121 int SizeOfCodeGeneratedSince(Label* label) {
1122 return pc_offset() - label->pos();
1125 // Mark address of the ExitJSFrame code.
1126 void RecordJSReturn();
1128 // Mark address of a debug break slot.
1129 void RecordDebugBreakSlot();
1131 // Record a comment relocation entry that can be used by a disassembler.
1132 // Use --code-comments to enable, or provide "force = true" flag to always
1134 void RecordComment(const char* msg, bool force = false);
1136 // Writes a single byte or word of data in the code stream. Used for
1137 // inline tables, e.g., jump-tables.
1138 void db(uint8_t data);
1139 void dd(uint32_t data);
1141 // Check if there is less than kGap bytes available in the buffer.
1142 // If this is the case, we need to grow the buffer before emitting
1143 // an instruction or relocation information.
1144 inline bool buffer_overflow() const {
1145 return pc_ >= reloc_info_writer.pos() - kGap;
1148 // Get the number of bytes available in the buffer.
1149 inline int available_space() const { return reloc_info_writer.pos() - pc_; }
1151 static bool IsNop(Address addr);
1153 PositionsRecorder* positions_recorder() { return &positions_recorder_; }
1155 int relocation_writer_size() {
1156 return (buffer_ + buffer_size_) - reloc_info_writer.pos();
1159 // Avoid overflows for displacements etc.
1160 static const int kMaximalBufferSize = 512*MB;
1162 byte byte_at(int pos) { return buffer_[pos]; }
1163 void set_byte_at(int pos, byte value) { buffer_[pos] = value; }
1165 // Allocate a constant pool of the correct size for the generated code.
1166 Handle<ConstantPoolArray> NewConstantPool(Isolate* isolate);
1168 // Generate the constant pool for the generated code.
1169 void PopulateConstantPool(ConstantPoolArray* constant_pool);
1172 void emit_sse_operand(XMMRegister reg, const Operand& adr);
1173 void emit_sse_operand(XMMRegister dst, XMMRegister src);
1174 void emit_sse_operand(Register dst, XMMRegister src);
1175 void emit_sse_operand(XMMRegister dst, Register src);
1177 byte* addr_at(int pos) { return buffer_ + pos; }
1181 uint32_t long_at(int pos) {
1182 return *reinterpret_cast<uint32_t*>(addr_at(pos));
1184 void long_at_put(int pos, uint32_t x) {
1185 *reinterpret_cast<uint32_t*>(addr_at(pos)) = x;
1190 inline void emit(uint32_t x);
1191 inline void emit(Handle<Object> handle);
1192 inline void emit(uint32_t x,
1193 RelocInfo::Mode rmode,
1194 TypeFeedbackId id = TypeFeedbackId::None());
1195 inline void emit(Handle<Code> code,
1196 RelocInfo::Mode rmode,
1197 TypeFeedbackId id = TypeFeedbackId::None());
1198 inline void emit(const Immediate& x);
1199 inline void emit_w(const Immediate& x);
1201 // Emit the code-object-relative offset of the label's position
1202 inline void emit_code_relative_offset(Label* label);
1204 // instruction generation
1205 void emit_arith_b(int op1, int op2, Register dst, int imm8);
1207 // Emit a basic arithmetic instruction (i.e. first byte of the family is 0x81)
1208 // with a given destination expression and an immediate operand. It attempts
1209 // to use the shortest encoding possible.
1210 // sel specifies the /n in the modrm byte (see the Intel PRM).
1211 void emit_arith(int sel, Operand dst, const Immediate& x);
1213 void emit_operand(Register reg, const Operand& adr);
1215 void emit_farith(int b1, int b2, int i);
1218 void print(Label* L);
1219 void bind_to(Label* L, int pos);
1222 inline Displacement disp_at(Label* L);
1223 inline void disp_at_put(Label* L, Displacement disp);
1224 inline void emit_disp(Label* L, Displacement::Type type);
1225 inline void emit_near_disp(Label* L);
1227 // record reloc info for current pc_
1228 void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0);
1230 friend class CodePatcher;
1231 friend class EnsureSpace;
1234 RelocInfoWriter reloc_info_writer;
1236 PositionsRecorder positions_recorder_;
1237 friend class PositionsRecorder;
1241 // Helper class that ensures that there is enough space for generating
1242 // instructions and relocation information. The constructor makes
1243 // sure that there is enough space and (in debug mode) the destructor
1244 // checks that we did not generate too much.
1245 class EnsureSpace BASE_EMBEDDED {
1247 explicit EnsureSpace(Assembler* assembler) : assembler_(assembler) {
1248 if (assembler_->buffer_overflow()) assembler_->GrowBuffer();
1250 space_before_ = assembler_->available_space();
1256 int bytes_generated = space_before_ - assembler_->available_space();
1257 DCHECK(bytes_generated < assembler_->kGap);
1262 Assembler* assembler_;
1268 } } // namespace v8::internal
1270 #endif // V8_IA32_ASSEMBLER_IA32_H_