1 // Copyright (c) 1994-2006 Sun Microsystems Inc.
2 // All Rights Reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions
8 // - Redistributions of source code must retain the above copyright notice,
9 // this list of conditions and the following disclaimer.
11 // - Redistribution in binary form must reproduce the above copyright
12 // notice, this list of conditions and the following disclaimer in the
13 // documentation and/or other materials provided with the
16 // - Neither the name of Sun Microsystems or the names of contributors may
17 // be used to endorse or promote products derived from this software without
18 // specific prior written permission.
20 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23 // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24 // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
31 // OF THE POSSIBILITY OF SUCH DAMAGE.
33 // The original source code covered by the above license above has been modified
34 // significantly by Google Inc.
35 // Copyright 2012 the V8 project authors. All rights reserved.
39 #if V8_TARGET_ARCH_IA32
41 #include "src/base/bits.h"
42 #include "src/base/cpu.h"
43 #include "src/disassembler.h"
44 #include "src/macro-assembler.h"
45 #include "src/serialize.h"
50 // -----------------------------------------------------------------------------
51 // Implementation of CpuFeatures
53 void CpuFeatures::ProbeImpl(bool cross_compile) {
55 CHECK(cpu.has_sse2()); // SSE2 support is mandatory.
56 CHECK(cpu.has_cmov()); // CMOV support is mandatory.
58 // Only use statically determined features for cross compile (snapshot).
59 if (cross_compile) return;
61 if (cpu.has_sse41() && FLAG_enable_sse4_1) supported_ |= 1u << SSE4_1;
62 if (cpu.has_sse3() && FLAG_enable_sse3) supported_ |= 1u << SSE3;
66 void CpuFeatures::PrintTarget() { }
67 void CpuFeatures::PrintFeatures() { }
70 // -----------------------------------------------------------------------------
71 // Implementation of Displacement
73 void Displacement::init(Label* L, Type type) {
74 DCHECK(!L->is_bound());
78 DCHECK(next > 0); // Displacements must be at positions > 0
80 // Ensure that we _never_ overflow the next field.
81 DCHECK(NextField::is_valid(Assembler::kMaximalBufferSize));
82 data_ = NextField::encode(next) | TypeField::encode(type);
86 // -----------------------------------------------------------------------------
87 // Implementation of RelocInfo
90 const int RelocInfo::kApplyMask =
91 RelocInfo::kCodeTargetMask | 1 << RelocInfo::RUNTIME_ENTRY |
92 1 << RelocInfo::JS_RETURN | 1 << RelocInfo::INTERNAL_REFERENCE |
93 1 << RelocInfo::DEBUG_BREAK_SLOT | 1 << RelocInfo::CODE_AGE_SEQUENCE;
96 bool RelocInfo::IsCodedSpecially() {
97 // The deserializer needs to know whether a pointer is specially coded. Being
98 // specially coded on IA32 means that it is a relative address, as used by
99 // branch instructions. These are also the ones that need changing when a
100 // code object moves.
101 return (1 << rmode_) & kApplyMask;
105 bool RelocInfo::IsInConstantPool() {
110 void RelocInfo::PatchCode(byte* instructions, int instruction_count) {
111 // Patch the code at the current address with the supplied instructions.
112 for (int i = 0; i < instruction_count; i++) {
113 *(pc_ + i) = *(instructions + i);
116 // Indicate that code has changed.
117 CpuFeatures::FlushICache(pc_, instruction_count);
121 // Patch the code at the current PC with a call to the target address.
122 // Additional guard int3 instructions can be added if required.
123 void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
124 // Call instruction takes up 5 bytes and int3 takes up one byte.
125 static const int kCallCodeSize = 5;
126 int code_size = kCallCodeSize + guard_bytes;
128 // Create a code patcher.
129 CodePatcher patcher(pc_, code_size);
131 // Add a label for checking the size of the code used for returning.
133 Label check_codesize;
134 patcher.masm()->bind(&check_codesize);
138 patcher.masm()->call(target, RelocInfo::NONE32);
140 // Check that the size of the code generated is as expected.
141 DCHECK_EQ(kCallCodeSize,
142 patcher.masm()->SizeOfCodeGeneratedSince(&check_codesize));
144 // Add the requested number of int3 instructions after the call.
145 DCHECK_GE(guard_bytes, 0);
146 for (int i = 0; i < guard_bytes; i++) {
147 patcher.masm()->int3();
152 // -----------------------------------------------------------------------------
153 // Implementation of Operand
155 Operand::Operand(Register base, int32_t disp, RelocInfo::Mode rmode) {
157 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
160 if (base.is(esp)) set_sib(times_1, esp, base);
161 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
164 if (base.is(esp)) set_sib(times_1, esp, base);
169 if (base.is(esp)) set_sib(times_1, esp, base);
170 set_dispr(disp, rmode);
175 Operand::Operand(Register base,
179 RelocInfo::Mode rmode) {
180 DCHECK(!index.is(esp)); // illegal addressing mode
181 // [base + index*scale + disp/r]
182 if (disp == 0 && RelocInfo::IsNone(rmode) && !base.is(ebp)) {
183 // [base + index*scale]
185 set_sib(scale, index, base);
186 } else if (is_int8(disp) && RelocInfo::IsNone(rmode)) {
187 // [base + index*scale + disp8]
189 set_sib(scale, index, base);
192 // [base + index*scale + disp/r]
194 set_sib(scale, index, base);
195 set_dispr(disp, rmode);
200 Operand::Operand(Register index,
203 RelocInfo::Mode rmode) {
204 DCHECK(!index.is(esp)); // illegal addressing mode
205 // [index*scale + disp/r]
207 set_sib(scale, index, ebp);
208 set_dispr(disp, rmode);
212 Operand::Operand(const Operand& operand, int32_t offset) {
213 DCHECK(operand.len_ >= 1);
214 // Operand encodes REX ModR/M [SIB] [Disp].
215 byte modrm = operand.buf_[0];
216 DCHECK(modrm < 0xC0); // Disallow mode 3 (register target).
217 bool has_sib = ((modrm & 0x07) == 0x04);
218 byte mode = modrm & 0xC0;
219 int disp_offset = has_sib ? 2 : 1;
220 int base_reg = (has_sib ? operand.buf_[1] : modrm) & 0x07;
221 // Mode 0 with rbp/r13 as ModR/M or SIB base register always has a 32-bit
223 bool is_baseless = (mode == 0) && (base_reg == 0x05); // No base or RIP base.
224 int32_t disp_value = 0;
225 if (mode == 0x80 || is_baseless) {
226 // Mode 2 or mode 0 with rbp/r13 as base: Word displacement.
227 disp_value = *bit_cast<const int32_t*>(&operand.buf_[disp_offset]);
228 } else if (mode == 0x40) {
229 // Mode 1: Byte displacement.
230 disp_value = static_cast<signed char>(operand.buf_[disp_offset]);
233 // Write new operand with same registers, but with modified displacement.
234 DCHECK(offset >= 0 ? disp_value + offset >= disp_value
235 : disp_value + offset < disp_value); // No overflow.
236 disp_value += offset;
237 if (!is_int8(disp_value) || is_baseless) {
238 // Need 32 bits of displacement, mode 2 or mode 1 with register rbp/r13.
239 buf_[0] = (modrm & 0x3f) | (is_baseless ? 0x00 : 0x80);
240 len_ = disp_offset + 4;
241 Memory::int32_at(&buf_[disp_offset]) = disp_value;
242 } else if (disp_value != 0 || (base_reg == 0x05)) {
243 // Need 8 bits of displacement.
244 buf_[0] = (modrm & 0x3f) | 0x40; // Mode 1.
245 len_ = disp_offset + 1;
246 buf_[disp_offset] = static_cast<byte>(disp_value);
248 // Need no displacement.
249 buf_[0] = (modrm & 0x3f); // Mode 0.
253 buf_[1] = operand.buf_[1];
258 bool Operand::is_reg(Register reg) const {
259 return ((buf_[0] & 0xF8) == 0xC0) // addressing mode is register only.
260 && ((buf_[0] & 0x07) == reg.code()); // register codes match.
264 bool Operand::is_reg_only() const {
265 return (buf_[0] & 0xF8) == 0xC0; // Addressing mode is register only.
269 Register Operand::reg() const {
270 DCHECK(is_reg_only());
271 return Register::from_code(buf_[0] & 0x07);
275 // -----------------------------------------------------------------------------
276 // Implementation of Assembler.
278 // Emit a single byte. Must always be inlined.
283 #ifdef GENERATED_CODE_COVERAGE
284 static void InitCoverageLog();
287 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
288 : AssemblerBase(isolate, buffer, buffer_size),
289 positions_recorder_(this) {
290 // Clear the buffer in debug mode unless it was provided by the
291 // caller in which case we can't be sure it's okay to overwrite
292 // existing code in it; see CodePatcher::CodePatcher(...).
295 memset(buffer_, 0xCC, buffer_size_); // int3
299 reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
301 #ifdef GENERATED_CODE_COVERAGE
307 void Assembler::GetCode(CodeDesc* desc) {
308 // Finalize code (at this point overflow() may be true, but the gap ensures
309 // that we are still not overlapping instructions and relocation info).
310 DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap.
311 // Set up code descriptor.
312 desc->buffer = buffer_;
313 desc->buffer_size = buffer_size_;
314 desc->instr_size = pc_offset();
315 desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos();
320 void Assembler::Align(int m) {
321 DCHECK(base::bits::IsPowerOfTwo32(m));
323 int addr = pc_offset();
324 Nop((m - (addr & mask)) & mask);
328 bool Assembler::IsNop(Address addr) {
330 while (*a == 0x66) a++;
331 if (*a == 0x90) return true;
332 if (a[0] == 0xf && a[1] == 0x1f) return true;
337 void Assembler::Nop(int bytes) {
338 EnsureSpace ensure_space(this);
340 // Multi byte nops from http://support.amd.com/us/Processor_TechDocs/40546.pdf
402 void Assembler::CodeTargetAlign() {
403 Align(16); // Preferred alignment of jump targets on ia32.
407 void Assembler::cpuid() {
408 EnsureSpace ensure_space(this);
414 void Assembler::pushad() {
415 EnsureSpace ensure_space(this);
420 void Assembler::popad() {
421 EnsureSpace ensure_space(this);
426 void Assembler::pushfd() {
427 EnsureSpace ensure_space(this);
432 void Assembler::popfd() {
433 EnsureSpace ensure_space(this);
438 void Assembler::push(const Immediate& x) {
439 EnsureSpace ensure_space(this);
450 void Assembler::push_imm32(int32_t imm32) {
451 EnsureSpace ensure_space(this);
457 void Assembler::push(Register src) {
458 EnsureSpace ensure_space(this);
459 EMIT(0x50 | src.code());
463 void Assembler::push(const Operand& src) {
464 EnsureSpace ensure_space(this);
466 emit_operand(esi, src);
470 void Assembler::pop(Register dst) {
471 DCHECK(reloc_info_writer.last_pc() != NULL);
472 EnsureSpace ensure_space(this);
473 EMIT(0x58 | dst.code());
477 void Assembler::pop(const Operand& dst) {
478 EnsureSpace ensure_space(this);
480 emit_operand(eax, dst);
484 void Assembler::enter(const Immediate& size) {
485 EnsureSpace ensure_space(this);
492 void Assembler::leave() {
493 EnsureSpace ensure_space(this);
498 void Assembler::mov_b(Register dst, const Operand& src) {
499 CHECK(dst.is_byte_register());
500 EnsureSpace ensure_space(this);
502 emit_operand(dst, src);
506 void Assembler::mov_b(const Operand& dst, int8_t imm8) {
507 EnsureSpace ensure_space(this);
509 emit_operand(eax, dst);
514 void Assembler::mov_b(const Operand& dst, Register src) {
515 CHECK(src.is_byte_register());
516 EnsureSpace ensure_space(this);
518 emit_operand(src, dst);
522 void Assembler::mov_w(Register dst, const Operand& src) {
523 EnsureSpace ensure_space(this);
526 emit_operand(dst, src);
530 void Assembler::mov_w(const Operand& dst, Register src) {
531 EnsureSpace ensure_space(this);
534 emit_operand(src, dst);
538 void Assembler::mov_w(const Operand& dst, int16_t imm16) {
539 EnsureSpace ensure_space(this);
542 emit_operand(eax, dst);
543 EMIT(static_cast<int8_t>(imm16 & 0xff));
544 EMIT(static_cast<int8_t>(imm16 >> 8));
548 void Assembler::mov(Register dst, int32_t imm32) {
549 EnsureSpace ensure_space(this);
550 EMIT(0xB8 | dst.code());
555 void Assembler::mov(Register dst, const Immediate& x) {
556 EnsureSpace ensure_space(this);
557 EMIT(0xB8 | dst.code());
562 void Assembler::mov(Register dst, Handle<Object> handle) {
563 EnsureSpace ensure_space(this);
564 EMIT(0xB8 | dst.code());
569 void Assembler::mov(Register dst, const Operand& src) {
570 EnsureSpace ensure_space(this);
572 emit_operand(dst, src);
576 void Assembler::mov(Register dst, Register src) {
577 EnsureSpace ensure_space(this);
579 EMIT(0xC0 | src.code() << 3 | dst.code());
583 void Assembler::mov(const Operand& dst, const Immediate& x) {
584 EnsureSpace ensure_space(this);
586 emit_operand(eax, dst);
591 void Assembler::mov(const Operand& dst, Handle<Object> handle) {
592 EnsureSpace ensure_space(this);
594 emit_operand(eax, dst);
599 void Assembler::mov(const Operand& dst, Register src) {
600 EnsureSpace ensure_space(this);
602 emit_operand(src, dst);
606 void Assembler::movsx_b(Register dst, const Operand& src) {
607 EnsureSpace ensure_space(this);
610 emit_operand(dst, src);
614 void Assembler::movsx_w(Register dst, const Operand& src) {
615 EnsureSpace ensure_space(this);
618 emit_operand(dst, src);
622 void Assembler::movzx_b(Register dst, const Operand& src) {
623 EnsureSpace ensure_space(this);
626 emit_operand(dst, src);
630 void Assembler::movzx_w(Register dst, const Operand& src) {
631 EnsureSpace ensure_space(this);
634 emit_operand(dst, src);
638 void Assembler::cmov(Condition cc, Register dst, const Operand& src) {
639 EnsureSpace ensure_space(this);
640 // Opcode: 0f 40 + cc /r.
643 emit_operand(dst, src);
647 void Assembler::cld() {
648 EnsureSpace ensure_space(this);
653 void Assembler::rep_movs() {
654 EnsureSpace ensure_space(this);
660 void Assembler::rep_stos() {
661 EnsureSpace ensure_space(this);
667 void Assembler::stos() {
668 EnsureSpace ensure_space(this);
673 void Assembler::xchg(Register dst, Register src) {
674 EnsureSpace ensure_space(this);
675 if (src.is(eax) || dst.is(eax)) { // Single-byte encoding.
676 EMIT(0x90 | (src.is(eax) ? dst.code() : src.code()));
679 EMIT(0xC0 | src.code() << 3 | dst.code());
684 void Assembler::xchg(Register dst, const Operand& src) {
685 EnsureSpace ensure_space(this);
687 emit_operand(dst, src);
691 void Assembler::adc(Register dst, int32_t imm32) {
692 EnsureSpace ensure_space(this);
693 emit_arith(2, Operand(dst), Immediate(imm32));
697 void Assembler::adc(Register dst, const Operand& src) {
698 EnsureSpace ensure_space(this);
700 emit_operand(dst, src);
704 void Assembler::add(Register dst, const Operand& src) {
705 EnsureSpace ensure_space(this);
707 emit_operand(dst, src);
711 void Assembler::add(const Operand& dst, Register src) {
712 EnsureSpace ensure_space(this);
714 emit_operand(src, dst);
718 void Assembler::add(const Operand& dst, const Immediate& x) {
719 DCHECK(reloc_info_writer.last_pc() != NULL);
720 EnsureSpace ensure_space(this);
721 emit_arith(0, dst, x);
725 void Assembler::and_(Register dst, int32_t imm32) {
726 and_(dst, Immediate(imm32));
730 void Assembler::and_(Register dst, const Immediate& x) {
731 EnsureSpace ensure_space(this);
732 emit_arith(4, Operand(dst), x);
736 void Assembler::and_(Register dst, const Operand& src) {
737 EnsureSpace ensure_space(this);
739 emit_operand(dst, src);
743 void Assembler::and_(const Operand& dst, const Immediate& x) {
744 EnsureSpace ensure_space(this);
745 emit_arith(4, dst, x);
749 void Assembler::and_(const Operand& dst, Register src) {
750 EnsureSpace ensure_space(this);
752 emit_operand(src, dst);
756 void Assembler::cmpb(const Operand& op, int8_t imm8) {
757 EnsureSpace ensure_space(this);
758 if (op.is_reg(eax)) {
762 emit_operand(edi, op); // edi == 7
768 void Assembler::cmpb(const Operand& op, Register reg) {
769 CHECK(reg.is_byte_register());
770 EnsureSpace ensure_space(this);
772 emit_operand(reg, op);
776 void Assembler::cmpb(Register reg, const Operand& op) {
777 CHECK(reg.is_byte_register());
778 EnsureSpace ensure_space(this);
780 emit_operand(reg, op);
784 void Assembler::cmpw(const Operand& op, Immediate imm16) {
785 DCHECK(imm16.is_int16());
786 EnsureSpace ensure_space(this);
789 emit_operand(edi, op);
794 void Assembler::cmp(Register reg, int32_t imm32) {
795 EnsureSpace ensure_space(this);
796 emit_arith(7, Operand(reg), Immediate(imm32));
800 void Assembler::cmp(Register reg, Handle<Object> handle) {
801 EnsureSpace ensure_space(this);
802 emit_arith(7, Operand(reg), Immediate(handle));
806 void Assembler::cmp(Register reg, const Operand& op) {
807 EnsureSpace ensure_space(this);
809 emit_operand(reg, op);
813 void Assembler::cmp(const Operand& op, const Immediate& imm) {
814 EnsureSpace ensure_space(this);
815 emit_arith(7, op, imm);
819 void Assembler::cmp(const Operand& op, Handle<Object> handle) {
820 EnsureSpace ensure_space(this);
821 emit_arith(7, op, Immediate(handle));
825 void Assembler::cmpb_al(const Operand& op) {
826 EnsureSpace ensure_space(this);
827 EMIT(0x38); // CMP r/m8, r8
828 emit_operand(eax, op); // eax has same code as register al.
832 void Assembler::cmpw_ax(const Operand& op) {
833 EnsureSpace ensure_space(this);
835 EMIT(0x39); // CMP r/m16, r16
836 emit_operand(eax, op); // eax has same code as register ax.
840 void Assembler::dec_b(Register dst) {
841 CHECK(dst.is_byte_register());
842 EnsureSpace ensure_space(this);
844 EMIT(0xC8 | dst.code());
848 void Assembler::dec_b(const Operand& dst) {
849 EnsureSpace ensure_space(this);
851 emit_operand(ecx, dst);
855 void Assembler::dec(Register dst) {
856 EnsureSpace ensure_space(this);
857 EMIT(0x48 | dst.code());
861 void Assembler::dec(const Operand& dst) {
862 EnsureSpace ensure_space(this);
864 emit_operand(ecx, dst);
868 void Assembler::cdq() {
869 EnsureSpace ensure_space(this);
874 void Assembler::idiv(const Operand& src) {
875 EnsureSpace ensure_space(this);
877 emit_operand(edi, src);
881 void Assembler::div(const Operand& src) {
882 EnsureSpace ensure_space(this);
884 emit_operand(esi, src);
888 void Assembler::imul(Register reg) {
889 EnsureSpace ensure_space(this);
891 EMIT(0xE8 | reg.code());
895 void Assembler::imul(Register dst, const Operand& src) {
896 EnsureSpace ensure_space(this);
899 emit_operand(dst, src);
903 void Assembler::imul(Register dst, Register src, int32_t imm32) {
904 imul(dst, Operand(src), imm32);
908 void Assembler::imul(Register dst, const Operand& src, int32_t imm32) {
909 EnsureSpace ensure_space(this);
910 if (is_int8(imm32)) {
912 emit_operand(dst, src);
916 emit_operand(dst, src);
922 void Assembler::inc(Register dst) {
923 EnsureSpace ensure_space(this);
924 EMIT(0x40 | dst.code());
928 void Assembler::inc(const Operand& dst) {
929 EnsureSpace ensure_space(this);
931 emit_operand(eax, dst);
935 void Assembler::lea(Register dst, const Operand& src) {
936 EnsureSpace ensure_space(this);
938 emit_operand(dst, src);
942 void Assembler::mul(Register src) {
943 EnsureSpace ensure_space(this);
945 EMIT(0xE0 | src.code());
949 void Assembler::neg(Register dst) {
950 EnsureSpace ensure_space(this);
952 EMIT(0xD8 | dst.code());
956 void Assembler::neg(const Operand& dst) {
957 EnsureSpace ensure_space(this);
959 emit_operand(ebx, dst);
963 void Assembler::not_(Register dst) {
964 EnsureSpace ensure_space(this);
966 EMIT(0xD0 | dst.code());
970 void Assembler::not_(const Operand& dst) {
971 EnsureSpace ensure_space(this);
973 emit_operand(edx, dst);
977 void Assembler::or_(Register dst, int32_t imm32) {
978 EnsureSpace ensure_space(this);
979 emit_arith(1, Operand(dst), Immediate(imm32));
983 void Assembler::or_(Register dst, const Operand& src) {
984 EnsureSpace ensure_space(this);
986 emit_operand(dst, src);
990 void Assembler::or_(const Operand& dst, const Immediate& x) {
991 EnsureSpace ensure_space(this);
992 emit_arith(1, dst, x);
996 void Assembler::or_(const Operand& dst, Register src) {
997 EnsureSpace ensure_space(this);
999 emit_operand(src, dst);
1003 void Assembler::rcl(Register dst, uint8_t imm8) {
1004 EnsureSpace ensure_space(this);
1005 DCHECK(is_uint5(imm8)); // illegal shift count
1008 EMIT(0xD0 | dst.code());
1011 EMIT(0xD0 | dst.code());
1017 void Assembler::rcr(Register dst, uint8_t imm8) {
1018 EnsureSpace ensure_space(this);
1019 DCHECK(is_uint5(imm8)); // illegal shift count
1022 EMIT(0xD8 | dst.code());
1025 EMIT(0xD8 | dst.code());
1031 void Assembler::ror(const Operand& dst, uint8_t imm8) {
1032 EnsureSpace ensure_space(this);
1033 DCHECK(is_uint5(imm8)); // illegal shift count
1036 emit_operand(ecx, dst);
1039 emit_operand(ecx, dst);
1045 void Assembler::ror_cl(const Operand& dst) {
1046 EnsureSpace ensure_space(this);
1048 emit_operand(ecx, dst);
1052 void Assembler::sar(const Operand& dst, uint8_t imm8) {
1053 EnsureSpace ensure_space(this);
1054 DCHECK(is_uint5(imm8)); // illegal shift count
1057 emit_operand(edi, dst);
1060 emit_operand(edi, dst);
1066 void Assembler::sar_cl(const Operand& dst) {
1067 EnsureSpace ensure_space(this);
1069 emit_operand(edi, dst);
1073 void Assembler::sbb(Register dst, const Operand& src) {
1074 EnsureSpace ensure_space(this);
1076 emit_operand(dst, src);
1080 void Assembler::shld(Register dst, const Operand& src) {
1081 EnsureSpace ensure_space(this);
1084 emit_operand(dst, src);
1088 void Assembler::shl(const Operand& dst, uint8_t imm8) {
1089 EnsureSpace ensure_space(this);
1090 DCHECK(is_uint5(imm8)); // illegal shift count
1093 emit_operand(esp, dst);
1096 emit_operand(esp, dst);
1102 void Assembler::shl_cl(const Operand& dst) {
1103 EnsureSpace ensure_space(this);
1105 emit_operand(esp, dst);
1109 void Assembler::shrd(Register dst, const Operand& src) {
1110 EnsureSpace ensure_space(this);
1113 emit_operand(dst, src);
1117 void Assembler::shr(const Operand& dst, uint8_t imm8) {
1118 EnsureSpace ensure_space(this);
1119 DCHECK(is_uint5(imm8)); // illegal shift count
1122 emit_operand(ebp, dst);
1125 emit_operand(ebp, dst);
1131 void Assembler::shr_cl(const Operand& dst) {
1132 EnsureSpace ensure_space(this);
1134 emit_operand(ebp, dst);
1138 void Assembler::sub(const Operand& dst, const Immediate& x) {
1139 EnsureSpace ensure_space(this);
1140 emit_arith(5, dst, x);
1144 void Assembler::sub(Register dst, const Operand& src) {
1145 EnsureSpace ensure_space(this);
1147 emit_operand(dst, src);
1151 void Assembler::sub(const Operand& dst, Register src) {
1152 EnsureSpace ensure_space(this);
1154 emit_operand(src, dst);
1158 void Assembler::test(Register reg, const Immediate& imm) {
1159 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1160 test_b(reg, imm.x_);
1164 EnsureSpace ensure_space(this);
1165 // This is not using emit_arith because test doesn't support
1166 // sign-extension of 8-bit operands.
1171 EMIT(0xC0 | reg.code());
1177 void Assembler::test(Register reg, const Operand& op) {
1178 EnsureSpace ensure_space(this);
1180 emit_operand(reg, op);
1184 void Assembler::test_b(Register reg, const Operand& op) {
1185 CHECK(reg.is_byte_register());
1186 EnsureSpace ensure_space(this);
1188 emit_operand(reg, op);
1192 void Assembler::test(const Operand& op, const Immediate& imm) {
1193 if (op.is_reg_only()) {
1194 test(op.reg(), imm);
1197 if (RelocInfo::IsNone(imm.rmode_) && is_uint8(imm.x_)) {
1198 return test_b(op, imm.x_);
1200 EnsureSpace ensure_space(this);
1202 emit_operand(eax, op);
1207 void Assembler::test_b(Register reg, uint8_t imm8) {
1208 EnsureSpace ensure_space(this);
1209 // Only use test against byte for registers that have a byte
1210 // variant: eax, ebx, ecx, and edx.
1214 } else if (reg.is_byte_register()) {
1215 emit_arith_b(0xF6, 0xC0, reg, imm8);
1218 EMIT(0xC0 | reg.code());
1224 void Assembler::test_b(const Operand& op, uint8_t imm8) {
1225 if (op.is_reg_only()) {
1226 test_b(op.reg(), imm8);
1229 EnsureSpace ensure_space(this);
1231 emit_operand(eax, op);
1236 void Assembler::xor_(Register dst, int32_t imm32) {
1237 EnsureSpace ensure_space(this);
1238 emit_arith(6, Operand(dst), Immediate(imm32));
1242 void Assembler::xor_(Register dst, const Operand& src) {
1243 EnsureSpace ensure_space(this);
1245 emit_operand(dst, src);
1249 void Assembler::xor_(const Operand& dst, Register src) {
1250 EnsureSpace ensure_space(this);
1252 emit_operand(src, dst);
1256 void Assembler::xor_(const Operand& dst, const Immediate& x) {
1257 EnsureSpace ensure_space(this);
1258 emit_arith(6, dst, x);
1262 void Assembler::bt(const Operand& dst, Register src) {
1263 EnsureSpace ensure_space(this);
1266 emit_operand(src, dst);
1270 void Assembler::bts(const Operand& dst, Register src) {
1271 EnsureSpace ensure_space(this);
1274 emit_operand(src, dst);
1278 void Assembler::bsr(Register dst, const Operand& src) {
1279 EnsureSpace ensure_space(this);
1282 emit_operand(dst, src);
1286 void Assembler::hlt() {
1287 EnsureSpace ensure_space(this);
1292 void Assembler::int3() {
1293 EnsureSpace ensure_space(this);
1298 void Assembler::nop() {
1299 EnsureSpace ensure_space(this);
1304 void Assembler::ret(int imm16) {
1305 EnsureSpace ensure_space(this);
1306 DCHECK(is_uint16(imm16));
1312 EMIT((imm16 >> 8) & 0xFF);
1317 // Labels refer to positions in the (to be) generated code.
1318 // There are bound, linked, and unused labels.
1320 // Bound labels refer to known positions in the already
1321 // generated code. pos() is the position the label refers to.
1323 // Linked labels refer to unknown positions in the code
1324 // to be generated; pos() is the position of the 32bit
1325 // Displacement of the last instruction using the label.
1328 void Assembler::print(Label* L) {
1329 if (L->is_unused()) {
1330 PrintF("unused label\n");
1331 } else if (L->is_bound()) {
1332 PrintF("bound label to %d\n", L->pos());
1333 } else if (L->is_linked()) {
1335 PrintF("unbound label");
1336 while (l.is_linked()) {
1337 Displacement disp = disp_at(&l);
1338 PrintF("@ %d ", l.pos());
1344 PrintF("label in inconsistent state (pos = %d)\n", L->pos_);
1349 void Assembler::bind_to(Label* L, int pos) {
1350 EnsureSpace ensure_space(this);
1351 DCHECK(0 <= pos && pos <= pc_offset()); // must have a valid binding position
1352 while (L->is_linked()) {
1353 Displacement disp = disp_at(L);
1354 int fixup_pos = L->pos();
1355 if (disp.type() == Displacement::CODE_RELATIVE) {
1356 // Relative to Code* heap object pointer.
1357 long_at_put(fixup_pos, pos + Code::kHeaderSize - kHeapObjectTag);
1359 if (disp.type() == Displacement::UNCONDITIONAL_JUMP) {
1360 DCHECK(byte_at(fixup_pos - 1) == 0xE9); // jmp expected
1362 // Relative address, relative to point after address.
1363 int imm32 = pos - (fixup_pos + sizeof(int32_t));
1364 long_at_put(fixup_pos, imm32);
1368 while (L->is_near_linked()) {
1369 int fixup_pos = L->near_link_pos();
1370 int offset_to_next =
1371 static_cast<int>(*reinterpret_cast<int8_t*>(addr_at(fixup_pos)));
1372 DCHECK(offset_to_next <= 0);
1373 // Relative address, relative to point after address.
1374 int disp = pos - fixup_pos - sizeof(int8_t);
1375 CHECK(0 <= disp && disp <= 127);
1376 set_byte_at(fixup_pos, disp);
1377 if (offset_to_next < 0) {
1378 L->link_to(fixup_pos + offset_to_next, Label::kNear);
1387 void Assembler::bind(Label* L) {
1388 EnsureSpace ensure_space(this);
1389 DCHECK(!L->is_bound()); // label can only be bound once
1390 bind_to(L, pc_offset());
1394 void Assembler::call(Label* L) {
1395 positions_recorder()->WriteRecordedPositions();
1396 EnsureSpace ensure_space(this);
1397 if (L->is_bound()) {
1398 const int long_size = 5;
1399 int offs = L->pos() - pc_offset();
1401 // 1110 1000 #32-bit disp.
1403 emit(offs - long_size);
1405 // 1110 1000 #32-bit disp.
1407 emit_disp(L, Displacement::OTHER);
1412 void Assembler::call(byte* entry, RelocInfo::Mode rmode) {
1413 positions_recorder()->WriteRecordedPositions();
1414 EnsureSpace ensure_space(this);
1415 DCHECK(!RelocInfo::IsCodeTarget(rmode));
1417 if (RelocInfo::IsRuntimeEntry(rmode)) {
1418 emit(reinterpret_cast<uint32_t>(entry), rmode);
1420 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1425 int Assembler::CallSize(const Operand& adr) {
1426 // Call size is 1 (opcode) + adr.len_ (operand).
1427 return 1 + adr.len_;
1431 void Assembler::call(const Operand& adr) {
1432 positions_recorder()->WriteRecordedPositions();
1433 EnsureSpace ensure_space(this);
1435 emit_operand(edx, adr);
1439 int Assembler::CallSize(Handle<Code> code, RelocInfo::Mode rmode) {
1440 return 1 /* EMIT */ + sizeof(uint32_t) /* emit */;
1444 void Assembler::call(Handle<Code> code,
1445 RelocInfo::Mode rmode,
1446 TypeFeedbackId ast_id) {
1447 positions_recorder()->WriteRecordedPositions();
1448 EnsureSpace ensure_space(this);
1449 DCHECK(RelocInfo::IsCodeTarget(rmode)
1450 || rmode == RelocInfo::CODE_AGE_SEQUENCE);
1452 emit(code, rmode, ast_id);
1456 void Assembler::jmp(Label* L, Label::Distance distance) {
1457 EnsureSpace ensure_space(this);
1458 if (L->is_bound()) {
1459 const int short_size = 2;
1460 const int long_size = 5;
1461 int offs = L->pos() - pc_offset();
1463 if (is_int8(offs - short_size)) {
1464 // 1110 1011 #8-bit disp.
1466 EMIT((offs - short_size) & 0xFF);
1468 // 1110 1001 #32-bit disp.
1470 emit(offs - long_size);
1472 } else if (distance == Label::kNear) {
1476 // 1110 1001 #32-bit disp.
1478 emit_disp(L, Displacement::UNCONDITIONAL_JUMP);
1483 void Assembler::jmp(byte* entry, RelocInfo::Mode rmode) {
1484 EnsureSpace ensure_space(this);
1485 DCHECK(!RelocInfo::IsCodeTarget(rmode));
1487 if (RelocInfo::IsRuntimeEntry(rmode)) {
1488 emit(reinterpret_cast<uint32_t>(entry), rmode);
1490 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1495 void Assembler::jmp(const Operand& adr) {
1496 EnsureSpace ensure_space(this);
1498 emit_operand(esp, adr);
1502 void Assembler::jmp(Handle<Code> code, RelocInfo::Mode rmode) {
1503 EnsureSpace ensure_space(this);
1504 DCHECK(RelocInfo::IsCodeTarget(rmode));
1510 void Assembler::j(Condition cc, Label* L, Label::Distance distance) {
1511 EnsureSpace ensure_space(this);
1512 DCHECK(0 <= cc && static_cast<int>(cc) < 16);
1513 if (L->is_bound()) {
1514 const int short_size = 2;
1515 const int long_size = 6;
1516 int offs = L->pos() - pc_offset();
1518 if (is_int8(offs - short_size)) {
1519 // 0111 tttn #8-bit disp
1521 EMIT((offs - short_size) & 0xFF);
1523 // 0000 1111 1000 tttn #32-bit disp
1526 emit(offs - long_size);
1528 } else if (distance == Label::kNear) {
1532 // 0000 1111 1000 tttn #32-bit disp
1533 // Note: could eliminate cond. jumps to this jump if condition
1534 // is the same however, seems to be rather unlikely case.
1537 emit_disp(L, Displacement::OTHER);
1542 void Assembler::j(Condition cc, byte* entry, RelocInfo::Mode rmode) {
1543 EnsureSpace ensure_space(this);
1544 DCHECK((0 <= cc) && (static_cast<int>(cc) < 16));
1545 // 0000 1111 1000 tttn #32-bit disp.
1548 if (RelocInfo::IsRuntimeEntry(rmode)) {
1549 emit(reinterpret_cast<uint32_t>(entry), rmode);
1551 emit(entry - (pc_ + sizeof(int32_t)), rmode);
1556 void Assembler::j(Condition cc, Handle<Code> code) {
1557 EnsureSpace ensure_space(this);
1558 // 0000 1111 1000 tttn #32-bit disp
1561 emit(code, RelocInfo::CODE_TARGET);
1565 // FPU instructions.
1567 void Assembler::fld(int i) {
1568 EnsureSpace ensure_space(this);
1569 emit_farith(0xD9, 0xC0, i);
1573 void Assembler::fstp(int i) {
1574 EnsureSpace ensure_space(this);
1575 emit_farith(0xDD, 0xD8, i);
1579 void Assembler::fld1() {
1580 EnsureSpace ensure_space(this);
1586 void Assembler::fldpi() {
1587 EnsureSpace ensure_space(this);
1593 void Assembler::fldz() {
1594 EnsureSpace ensure_space(this);
1600 void Assembler::fldln2() {
1601 EnsureSpace ensure_space(this);
1607 void Assembler::fld_s(const Operand& adr) {
1608 EnsureSpace ensure_space(this);
1610 emit_operand(eax, adr);
1614 void Assembler::fld_d(const Operand& adr) {
1615 EnsureSpace ensure_space(this);
1617 emit_operand(eax, adr);
1621 void Assembler::fstp_s(const Operand& adr) {
1622 EnsureSpace ensure_space(this);
1624 emit_operand(ebx, adr);
1628 void Assembler::fst_s(const Operand& adr) {
1629 EnsureSpace ensure_space(this);
1631 emit_operand(edx, adr);
1635 void Assembler::fstp_d(const Operand& adr) {
1636 EnsureSpace ensure_space(this);
1638 emit_operand(ebx, adr);
1642 void Assembler::fst_d(const Operand& adr) {
1643 EnsureSpace ensure_space(this);
1645 emit_operand(edx, adr);
1649 void Assembler::fild_s(const Operand& adr) {
1650 EnsureSpace ensure_space(this);
1652 emit_operand(eax, adr);
1656 void Assembler::fild_d(const Operand& adr) {
1657 EnsureSpace ensure_space(this);
1659 emit_operand(ebp, adr);
1663 void Assembler::fistp_s(const Operand& adr) {
1664 EnsureSpace ensure_space(this);
1666 emit_operand(ebx, adr);
1670 void Assembler::fisttp_s(const Operand& adr) {
1671 DCHECK(IsEnabled(SSE3));
1672 EnsureSpace ensure_space(this);
1674 emit_operand(ecx, adr);
1678 void Assembler::fisttp_d(const Operand& adr) {
1679 DCHECK(IsEnabled(SSE3));
1680 EnsureSpace ensure_space(this);
1682 emit_operand(ecx, adr);
1686 void Assembler::fist_s(const Operand& adr) {
1687 EnsureSpace ensure_space(this);
1689 emit_operand(edx, adr);
1693 void Assembler::fistp_d(const Operand& adr) {
1694 EnsureSpace ensure_space(this);
1696 emit_operand(edi, adr);
1700 void Assembler::fabs() {
1701 EnsureSpace ensure_space(this);
1707 void Assembler::fchs() {
1708 EnsureSpace ensure_space(this);
1714 void Assembler::fcos() {
1715 EnsureSpace ensure_space(this);
1721 void Assembler::fsin() {
1722 EnsureSpace ensure_space(this);
1728 void Assembler::fptan() {
1729 EnsureSpace ensure_space(this);
1735 void Assembler::fyl2x() {
1736 EnsureSpace ensure_space(this);
1742 void Assembler::f2xm1() {
1743 EnsureSpace ensure_space(this);
1749 void Assembler::fscale() {
1750 EnsureSpace ensure_space(this);
1756 void Assembler::fninit() {
1757 EnsureSpace ensure_space(this);
1763 void Assembler::fadd(int i) {
1764 EnsureSpace ensure_space(this);
1765 emit_farith(0xDC, 0xC0, i);
1769 void Assembler::fadd_i(int i) {
1770 EnsureSpace ensure_space(this);
1771 emit_farith(0xD8, 0xC0, i);
1775 void Assembler::fsub(int i) {
1776 EnsureSpace ensure_space(this);
1777 emit_farith(0xDC, 0xE8, i);
1781 void Assembler::fsub_i(int i) {
1782 EnsureSpace ensure_space(this);
1783 emit_farith(0xD8, 0xE0, i);
1787 void Assembler::fisub_s(const Operand& adr) {
1788 EnsureSpace ensure_space(this);
1790 emit_operand(esp, adr);
1794 void Assembler::fmul_i(int i) {
1795 EnsureSpace ensure_space(this);
1796 emit_farith(0xD8, 0xC8, i);
1800 void Assembler::fmul(int i) {
1801 EnsureSpace ensure_space(this);
1802 emit_farith(0xDC, 0xC8, i);
1806 void Assembler::fdiv(int i) {
1807 EnsureSpace ensure_space(this);
1808 emit_farith(0xDC, 0xF8, i);
1812 void Assembler::fdiv_i(int i) {
1813 EnsureSpace ensure_space(this);
1814 emit_farith(0xD8, 0xF0, i);
1818 void Assembler::faddp(int i) {
1819 EnsureSpace ensure_space(this);
1820 emit_farith(0xDE, 0xC0, i);
1824 void Assembler::fsubp(int i) {
1825 EnsureSpace ensure_space(this);
1826 emit_farith(0xDE, 0xE8, i);
1830 void Assembler::fsubrp(int i) {
1831 EnsureSpace ensure_space(this);
1832 emit_farith(0xDE, 0xE0, i);
1836 void Assembler::fmulp(int i) {
1837 EnsureSpace ensure_space(this);
1838 emit_farith(0xDE, 0xC8, i);
1842 void Assembler::fdivp(int i) {
1843 EnsureSpace ensure_space(this);
1844 emit_farith(0xDE, 0xF8, i);
1848 void Assembler::fprem() {
1849 EnsureSpace ensure_space(this);
1855 void Assembler::fprem1() {
1856 EnsureSpace ensure_space(this);
1862 void Assembler::fxch(int i) {
1863 EnsureSpace ensure_space(this);
1864 emit_farith(0xD9, 0xC8, i);
1868 void Assembler::fincstp() {
1869 EnsureSpace ensure_space(this);
1875 void Assembler::ffree(int i) {
1876 EnsureSpace ensure_space(this);
1877 emit_farith(0xDD, 0xC0, i);
1881 void Assembler::ftst() {
1882 EnsureSpace ensure_space(this);
1888 void Assembler::fucomp(int i) {
1889 EnsureSpace ensure_space(this);
1890 emit_farith(0xDD, 0xE8, i);
1894 void Assembler::fucompp() {
1895 EnsureSpace ensure_space(this);
1901 void Assembler::fucomi(int i) {
1902 EnsureSpace ensure_space(this);
1908 void Assembler::fucomip() {
1909 EnsureSpace ensure_space(this);
1915 void Assembler::fcompp() {
1916 EnsureSpace ensure_space(this);
1922 void Assembler::fnstsw_ax() {
1923 EnsureSpace ensure_space(this);
1929 void Assembler::fwait() {
1930 EnsureSpace ensure_space(this);
1935 void Assembler::frndint() {
1936 EnsureSpace ensure_space(this);
1942 void Assembler::fnclex() {
1943 EnsureSpace ensure_space(this);
1949 void Assembler::sahf() {
1950 EnsureSpace ensure_space(this);
1955 void Assembler::setcc(Condition cc, Register reg) {
1956 DCHECK(reg.is_byte_register());
1957 EnsureSpace ensure_space(this);
1960 EMIT(0xC0 | reg.code());
1964 void Assembler::cvttss2si(Register dst, const Operand& src) {
1965 EnsureSpace ensure_space(this);
1969 emit_operand(dst, src);
1973 void Assembler::cvttsd2si(Register dst, const Operand& src) {
1974 EnsureSpace ensure_space(this);
1978 emit_operand(dst, src);
1982 void Assembler::cvtsd2si(Register dst, XMMRegister src) {
1983 EnsureSpace ensure_space(this);
1987 emit_sse_operand(dst, src);
1991 void Assembler::cvtsi2sd(XMMRegister dst, const Operand& src) {
1992 EnsureSpace ensure_space(this);
1996 emit_sse_operand(dst, src);
2000 void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
2001 EnsureSpace ensure_space(this);
2005 emit_sse_operand(dst, src);
2009 void Assembler::cvtsd2ss(XMMRegister dst, const Operand& src) {
2010 EnsureSpace ensure_space(this);
2014 emit_sse_operand(dst, src);
2018 void Assembler::addsd(XMMRegister dst, const Operand& src) {
2019 EnsureSpace ensure_space(this);
2023 emit_sse_operand(dst, src);
2027 void Assembler::mulsd(XMMRegister dst, const Operand& src) {
2028 EnsureSpace ensure_space(this);
2032 emit_sse_operand(dst, src);
2036 void Assembler::subsd(XMMRegister dst, const Operand& src) {
2037 EnsureSpace ensure_space(this);
2041 emit_sse_operand(dst, src);
2045 void Assembler::divsd(XMMRegister dst, const Operand& src) {
2046 EnsureSpace ensure_space(this);
2050 emit_sse_operand(dst, src);
2054 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2055 EnsureSpace ensure_space(this);
2059 emit_sse_operand(dst, src);
2063 void Assembler::xorpd(XMMRegister dst, const Operand& src) {
2064 EnsureSpace ensure_space(this);
2068 emit_sse_operand(dst, src);
2072 void Assembler::andps(XMMRegister dst, const Operand& src) {
2073 EnsureSpace ensure_space(this);
2076 emit_sse_operand(dst, src);
2080 void Assembler::orps(XMMRegister dst, const Operand& src) {
2081 EnsureSpace ensure_space(this);
2084 emit_sse_operand(dst, src);
2088 void Assembler::xorps(XMMRegister dst, const Operand& src) {
2089 EnsureSpace ensure_space(this);
2092 emit_sse_operand(dst, src);
2096 void Assembler::addps(XMMRegister dst, const Operand& src) {
2097 EnsureSpace ensure_space(this);
2100 emit_sse_operand(dst, src);
2104 void Assembler::subps(XMMRegister dst, const Operand& src) {
2105 EnsureSpace ensure_space(this);
2108 emit_sse_operand(dst, src);
2112 void Assembler::mulps(XMMRegister dst, const Operand& src) {
2113 EnsureSpace ensure_space(this);
2116 emit_sse_operand(dst, src);
2120 void Assembler::divps(XMMRegister dst, const Operand& src) {
2121 EnsureSpace ensure_space(this);
2124 emit_sse_operand(dst, src);
2128 void Assembler::addpd(XMMRegister dst, const Operand& src) {
2129 EnsureSpace ensure_space(this);
2133 emit_sse_operand(dst, src);
2137 void Assembler::subpd(XMMRegister dst, const Operand& src) {
2138 EnsureSpace ensure_space(this);
2142 emit_sse_operand(dst, src);
2146 void Assembler::mulpd(XMMRegister dst, const Operand& src) {
2147 EnsureSpace ensure_space(this);
2151 emit_sse_operand(dst, src);
2155 void Assembler::divpd(XMMRegister dst, const Operand& src) {
2156 EnsureSpace ensure_space(this);
2160 emit_sse_operand(dst, src);
2164 void Assembler::sqrtsd(XMMRegister dst, const Operand& src) {
2165 EnsureSpace ensure_space(this);
2169 emit_sse_operand(dst, src);
2173 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
2174 EnsureSpace ensure_space(this);
2178 emit_sse_operand(dst, src);
2182 void Assembler::andpd(XMMRegister dst, const Operand& src) {
2183 EnsureSpace ensure_space(this);
2187 emit_sse_operand(dst, src);
2191 void Assembler::orpd(XMMRegister dst, XMMRegister src) {
2192 EnsureSpace ensure_space(this);
2196 emit_sse_operand(dst, src);
2200 void Assembler::ucomisd(XMMRegister dst, const Operand& src) {
2201 EnsureSpace ensure_space(this);
2205 emit_sse_operand(dst, src);
2209 void Assembler::roundsd(XMMRegister dst, XMMRegister src, RoundingMode mode) {
2210 DCHECK(IsEnabled(SSE4_1));
2211 EnsureSpace ensure_space(this);
2216 emit_sse_operand(dst, src);
2217 // Mask precision exeption.
2218 EMIT(static_cast<byte>(mode) | 0x8);
2222 void Assembler::movmskpd(Register dst, XMMRegister src) {
2223 EnsureSpace ensure_space(this);
2227 emit_sse_operand(dst, src);
2231 void Assembler::movmskps(Register dst, XMMRegister src) {
2232 EnsureSpace ensure_space(this);
2235 emit_sse_operand(dst, src);
2239 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
2240 EnsureSpace ensure_space(this);
2244 emit_sse_operand(dst, src);
2248 void Assembler::pcmpgtd(XMMRegister dst, XMMRegister src) {
2249 EnsureSpace ensure_space(this);
2253 emit_sse_operand(dst, src);
2257 void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) {
2258 EnsureSpace ensure_space(this);
2262 emit_sse_operand(dst, src);
2267 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2268 EnsureSpace ensure_space(this);
2271 emit_sse_operand(dst, src);
2275 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2276 EnsureSpace ensure_space(this);
2279 emit_sse_operand(dst, src);
2283 void Assembler::movhlps(XMMRegister dst, XMMRegister src) {
2284 EnsureSpace ensure_space(this);
2287 emit_sse_operand(dst, src);
2291 void Assembler::movups(XMMRegister dst, const Operand& src) {
2292 EnsureSpace ensure_space(this);
2295 emit_sse_operand(dst, src);
2299 void Assembler::movups(const Operand& dst, XMMRegister src) {
2300 EnsureSpace ensure_space(this);
2303 emit_sse_operand(src, dst);
2307 void Assembler::shufps(XMMRegister dst, XMMRegister src, byte imm8) {
2308 DCHECK(is_uint8(imm8));
2309 EnsureSpace ensure_space(this);
2312 emit_sse_operand(dst, src);
2317 void Assembler::shufpd(XMMRegister dst, XMMRegister src, byte imm8) {
2318 DCHECK(is_uint8(imm8));
2319 EnsureSpace ensure_space(this);
2323 emit_sse_operand(dst, src);
2328 void Assembler::movdqa(const Operand& dst, XMMRegister src) {
2329 EnsureSpace ensure_space(this);
2333 emit_sse_operand(src, dst);
2337 void Assembler::movdqa(XMMRegister dst, const Operand& src) {
2338 EnsureSpace ensure_space(this);
2342 emit_sse_operand(dst, src);
2346 void Assembler::movdqu(const Operand& dst, XMMRegister src ) {
2347 EnsureSpace ensure_space(this);
2351 emit_sse_operand(src, dst);
2355 void Assembler::movdqu(XMMRegister dst, const Operand& src) {
2356 EnsureSpace ensure_space(this);
2360 emit_sse_operand(dst, src);
2364 void Assembler::movntdqa(XMMRegister dst, const Operand& src) {
2365 DCHECK(IsEnabled(SSE4_1));
2366 EnsureSpace ensure_space(this);
2371 emit_sse_operand(dst, src);
2375 void Assembler::movntdq(const Operand& dst, XMMRegister src) {
2376 EnsureSpace ensure_space(this);
2380 emit_sse_operand(src, dst);
2384 void Assembler::prefetch(const Operand& src, int level) {
2385 DCHECK(is_uint2(level));
2386 EnsureSpace ensure_space(this);
2389 // Emit hint number in Reg position of RegR/M.
2390 XMMRegister code = XMMRegister::from_code(level);
2391 emit_sse_operand(code, src);
2395 void Assembler::movsd(const Operand& dst, XMMRegister src ) {
2396 EnsureSpace ensure_space(this);
2397 EMIT(0xF2); // double
2399 EMIT(0x11); // store
2400 emit_sse_operand(src, dst);
2404 void Assembler::movsd(XMMRegister dst, const Operand& src) {
2405 EnsureSpace ensure_space(this);
2406 EMIT(0xF2); // double
2409 emit_sse_operand(dst, src);
2413 void Assembler::movss(const Operand& dst, XMMRegister src ) {
2414 EnsureSpace ensure_space(this);
2415 EMIT(0xF3); // float
2417 EMIT(0x11); // store
2418 emit_sse_operand(src, dst);
2422 void Assembler::movss(XMMRegister dst, const Operand& src) {
2423 EnsureSpace ensure_space(this);
2424 EMIT(0xF3); // float
2427 emit_sse_operand(dst, src);
2431 void Assembler::movq(const Operand& dst, XMMRegister src ) {
2432 EnsureSpace ensure_space(this);
2435 EMIT(0xD6); // store
2436 emit_sse_operand(src, dst);
2440 void Assembler::movq(XMMRegister dst, const Operand& src) {
2441 EnsureSpace ensure_space(this);
2445 emit_sse_operand(dst, src);
2449 void Assembler::movd(XMMRegister dst, const Operand& src) {
2450 EnsureSpace ensure_space(this);
2454 emit_sse_operand(dst, src);
2458 void Assembler::movd(const Operand& dst, XMMRegister src) {
2459 EnsureSpace ensure_space(this);
2463 emit_sse_operand(src, dst);
2467 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
2468 DCHECK(IsEnabled(SSE4_1));
2469 DCHECK(is_uint8(imm8));
2470 EnsureSpace ensure_space(this);
2475 emit_sse_operand(src, dst);
2480 void Assembler::pand(XMMRegister dst, XMMRegister src) {
2481 EnsureSpace ensure_space(this);
2485 emit_sse_operand(dst, src);
2489 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
2490 EnsureSpace ensure_space(this);
2494 emit_sse_operand(dst, src);
2498 void Assembler::por(XMMRegister dst, XMMRegister src) {
2499 EnsureSpace ensure_space(this);
2503 emit_sse_operand(dst, src);
2507 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
2508 DCHECK(IsEnabled(SSE4_1));
2509 EnsureSpace ensure_space(this);
2514 emit_sse_operand(dst, src);
2518 void Assembler::pslld(XMMRegister reg, int8_t shift) {
2519 EnsureSpace ensure_space(this);
2523 emit_sse_operand(esi, reg); // esi == 6
2528 void Assembler::psrld(XMMRegister reg, int8_t shift) {
2529 EnsureSpace ensure_space(this);
2533 emit_sse_operand(edx, reg); // edx == 2
2538 void Assembler::psllq(XMMRegister reg, int8_t shift) {
2539 EnsureSpace ensure_space(this);
2543 emit_sse_operand(esi, reg); // esi == 6
2548 void Assembler::psllq(XMMRegister dst, XMMRegister src) {
2549 EnsureSpace ensure_space(this);
2553 emit_sse_operand(dst, src);
2557 void Assembler::pslld(XMMRegister dst, XMMRegister src) {
2558 EnsureSpace ensure_space(this);
2562 emit_sse_operand(dst, src);
2566 void Assembler::psrld(XMMRegister dst, XMMRegister src) {
2567 EnsureSpace ensure_space(this);
2571 emit_sse_operand(dst, src);
2575 void Assembler::psrad(XMMRegister reg, int8_t shift) {
2576 EnsureSpace ensure_space(this);
2580 emit_sse_operand(esp, reg); // esp == 4
2585 void Assembler::psrad(XMMRegister dst, XMMRegister src) {
2586 EnsureSpace ensure_space(this);
2590 emit_sse_operand(dst, src);
2594 void Assembler::psrlq(XMMRegister reg, int8_t shift) {
2595 EnsureSpace ensure_space(this);
2599 emit_sse_operand(edx, reg); // edx == 2
2604 void Assembler::psrlq(XMMRegister dst, XMMRegister src) {
2605 EnsureSpace ensure_space(this);
2609 emit_sse_operand(dst, src);
2613 void Assembler::psrldq(XMMRegister dst, int8_t shift) {
2614 EnsureSpace ensure_space(this);
2618 emit_sse_operand(ebx, dst); // ebx == 3
2623 void Assembler::pshufd(XMMRegister dst, XMMRegister src, uint8_t shuffle) {
2624 EnsureSpace ensure_space(this);
2628 emit_sse_operand(dst, src);
2633 void Assembler::pextrd(const Operand& dst, XMMRegister src, int8_t offset) {
2634 DCHECK(IsEnabled(SSE4_1));
2635 EnsureSpace ensure_space(this);
2640 emit_sse_operand(src, dst);
2645 void Assembler::pinsrd(XMMRegister dst, const Operand& src, int8_t offset) {
2646 DCHECK(IsEnabled(SSE4_1));
2647 EnsureSpace ensure_space(this);
2652 emit_sse_operand(dst, src);
2657 void Assembler::minps(XMMRegister dst, const Operand& src) {
2658 EnsureSpace ensure_space(this);
2661 emit_sse_operand(dst, src);
2665 void Assembler::maxps(XMMRegister dst, const Operand& src) {
2666 EnsureSpace ensure_space(this);
2669 emit_sse_operand(dst, src);
2673 void Assembler::minpd(XMMRegister dst, const Operand& src) {
2674 EnsureSpace ensure_space(this);
2678 emit_sse_operand(dst, src);
2682 void Assembler::maxpd(XMMRegister dst, const Operand& src) {
2683 EnsureSpace ensure_space(this);
2687 emit_sse_operand(dst, src);
2691 void Assembler::rcpps(XMMRegister dst, const Operand& src) {
2692 EnsureSpace ensure_space(this);
2695 emit_sse_operand(dst, src);
2699 void Assembler::rsqrtps(XMMRegister dst, const Operand& src) {
2700 EnsureSpace ensure_space(this);
2703 emit_sse_operand(dst, src);
2707 void Assembler::sqrtps(XMMRegister dst, const Operand& src) {
2708 EnsureSpace ensure_space(this);
2711 emit_sse_operand(dst, src);
2715 void Assembler::sqrtpd(XMMRegister dst, const Operand& src) {
2716 EnsureSpace ensure_space(this);
2720 emit_sse_operand(dst, src);
2724 void Assembler::cvtdq2ps(XMMRegister dst, const Operand& src) {
2725 EnsureSpace ensure_space(this);
2728 emit_sse_operand(dst, src);
2732 void Assembler::paddd(XMMRegister dst, const Operand& src) {
2733 EnsureSpace ensure_space(this);
2737 emit_sse_operand(dst, src);
2741 void Assembler::psubd(XMMRegister dst, const Operand& src) {
2742 EnsureSpace ensure_space(this);
2746 emit_sse_operand(dst, src);
2750 void Assembler::pmulld(XMMRegister dst, const Operand& src) {
2751 DCHECK(IsEnabled(SSE4_1));
2752 EnsureSpace ensure_space(this);
2757 emit_sse_operand(dst, src);
2761 void Assembler::pmuludq(XMMRegister dst, const Operand& src) {
2762 EnsureSpace ensure_space(this);
2766 emit_sse_operand(dst, src);
2770 void Assembler::punpackldq(XMMRegister dst, const Operand& src) {
2771 EnsureSpace ensure_space(this);
2775 emit_sse_operand(dst, src);
2779 void Assembler::cvtps2dq(XMMRegister dst, const Operand& src) {
2780 EnsureSpace ensure_space(this);
2784 emit_sse_operand(dst, src);
2788 void Assembler::cmpps(XMMRegister dst, XMMRegister src, int8_t cmp) {
2789 EnsureSpace ensure_space(this);
2792 emit_sse_operand(dst, src);
2797 void Assembler::cmpeqps(XMMRegister dst, XMMRegister src) {
2798 cmpps(dst, src, 0x0);
2802 void Assembler::cmpltps(XMMRegister dst, XMMRegister src) {
2803 cmpps(dst, src, 0x1);
2807 void Assembler::cmpleps(XMMRegister dst, XMMRegister src) {
2808 cmpps(dst, src, 0x2);
2812 void Assembler::cmpneqps(XMMRegister dst, XMMRegister src) {
2813 cmpps(dst, src, 0x4);
2817 void Assembler::cmpnltps(XMMRegister dst, XMMRegister src) {
2818 cmpps(dst, src, 0x5);
2822 void Assembler::cmpnleps(XMMRegister dst, XMMRegister src) {
2823 cmpps(dst, src, 0x6);
2827 void Assembler::insertps(XMMRegister dst, XMMRegister src, byte imm8) {
2828 DCHECK(CpuFeatures::IsSupported(SSE4_1));
2829 DCHECK(is_uint8(imm8));
2830 EnsureSpace ensure_space(this);
2835 emit_sse_operand(dst, src);
2840 void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) {
2841 Register ireg = { reg.code() };
2842 emit_operand(ireg, adr);
2846 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
2847 EMIT(0xC0 | dst.code() << 3 | src.code());
2851 void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
2852 EMIT(0xC0 | dst.code() << 3 | src.code());
2856 void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
2857 EMIT(0xC0 | (dst.code() << 3) | src.code());
2861 void Assembler::RecordJSReturn() {
2862 positions_recorder()->WriteRecordedPositions();
2863 EnsureSpace ensure_space(this);
2864 RecordRelocInfo(RelocInfo::JS_RETURN);
2868 void Assembler::RecordDebugBreakSlot() {
2869 positions_recorder()->WriteRecordedPositions();
2870 EnsureSpace ensure_space(this);
2871 RecordRelocInfo(RelocInfo::DEBUG_BREAK_SLOT);
2875 void Assembler::RecordComment(const char* msg, bool force) {
2876 if (FLAG_code_comments || force) {
2877 EnsureSpace ensure_space(this);
2878 RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg));
2883 void Assembler::GrowBuffer() {
2884 DCHECK(buffer_overflow());
2885 if (!own_buffer_) FATAL("external code buffer is too small");
2887 // Compute new buffer size.
2888 CodeDesc desc; // the new buffer
2889 desc.buffer_size = 2 * buffer_size_;
2891 // Some internal data structures overflow for very large buffers,
2892 // they must ensure that kMaximalBufferSize is not too large.
2893 if ((desc.buffer_size > kMaximalBufferSize) ||
2894 (desc.buffer_size > isolate()->heap()->MaxOldGenerationSize())) {
2895 V8::FatalProcessOutOfMemory("Assembler::GrowBuffer");
2898 // Set up new buffer.
2899 desc.buffer = NewArray<byte>(desc.buffer_size);
2900 desc.instr_size = pc_offset();
2901 desc.reloc_size = (buffer_ + buffer_size_) - (reloc_info_writer.pos());
2903 // Clear the buffer in debug mode. Use 'int3' instructions to make
2904 // sure to get into problems if we ever run uninitialized code.
2906 memset(desc.buffer, 0xCC, desc.buffer_size);
2910 int pc_delta = desc.buffer - buffer_;
2911 int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_);
2912 MemMove(desc.buffer, buffer_, desc.instr_size);
2913 MemMove(rc_delta + reloc_info_writer.pos(), reloc_info_writer.pos(),
2917 DeleteArray(buffer_);
2918 buffer_ = desc.buffer;
2919 buffer_size_ = desc.buffer_size;
2921 reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
2922 reloc_info_writer.last_pc() + pc_delta);
2924 // Relocate runtime entries.
2925 for (RelocIterator it(desc); !it.done(); it.next()) {
2926 RelocInfo::Mode rmode = it.rinfo()->rmode();
2927 if (rmode == RelocInfo::INTERNAL_REFERENCE) {
2928 int32_t* p = reinterpret_cast<int32_t*>(it.rinfo()->pc());
2929 if (*p != 0) { // 0 means uninitialized.
2935 DCHECK(!buffer_overflow());
2939 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
2940 DCHECK(is_uint8(op1) && is_uint8(op2)); // wrong opcode
2941 DCHECK(is_uint8(imm8));
2942 DCHECK((op1 & 0x01) == 0); // should be 8bit operation
2944 EMIT(op2 | dst.code());
2949 void Assembler::emit_arith(int sel, Operand dst, const Immediate& x) {
2950 DCHECK((0 <= sel) && (sel <= 7));
2951 Register ireg = { sel };
2953 EMIT(0x83); // using a sign-extended 8-bit immediate.
2954 emit_operand(ireg, dst);
2956 } else if (dst.is_reg(eax)) {
2957 EMIT((sel << 3) | 0x05); // short form if the destination is eax.
2960 EMIT(0x81); // using a literal 32-bit immediate.
2961 emit_operand(ireg, dst);
2967 void Assembler::emit_operand(Register reg, const Operand& adr) {
2968 const unsigned length = adr.len_;
2971 // Emit updated ModRM byte containing the given register.
2972 pc_[0] = (adr.buf_[0] & ~0x38) | (reg.code() << 3);
2974 // Emit the rest of the encoded operand.
2975 for (unsigned i = 1; i < length; i++) pc_[i] = adr.buf_[i];
2978 // Emit relocation information if necessary.
2979 if (length >= sizeof(int32_t) && !RelocInfo::IsNone(adr.rmode_)) {
2980 pc_ -= sizeof(int32_t); // pc_ must be *at* disp32
2981 RecordRelocInfo(adr.rmode_);
2982 pc_ += sizeof(int32_t);
2987 void Assembler::emit_farith(int b1, int b2, int i) {
2988 DCHECK(is_uint8(b1) && is_uint8(b2)); // wrong opcode
2989 DCHECK(0 <= i && i < 8); // illegal stack offset
2995 void Assembler::db(uint8_t data) {
2996 EnsureSpace ensure_space(this);
3001 void Assembler::dd(uint32_t data) {
3002 EnsureSpace ensure_space(this);
3007 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
3008 DCHECK(!RelocInfo::IsNone(rmode));
3009 // Don't record external references unless the heap will be serialized.
3010 if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
3011 !serializer_enabled() && !emit_debug_code()) {
3014 RelocInfo rinfo(pc_, rmode, data, NULL);
3015 reloc_info_writer.Write(&rinfo);
3019 Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) {
3020 // No out-of-line constant pool support.
3021 DCHECK(!FLAG_enable_ool_constant_pool);
3022 return isolate->factory()->empty_constant_pool_array();
3026 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) {
3027 // No out-of-line constant pool support.
3028 DCHECK(!FLAG_enable_ool_constant_pool);
3033 #ifdef GENERATED_CODE_COVERAGE
3034 static FILE* coverage_log = NULL;
3037 static void InitCoverageLog() {
3038 char* file_name = getenv("V8_GENERATED_CODE_COVERAGE_LOG");
3039 if (file_name != NULL) {
3040 coverage_log = fopen(file_name, "aw+");
3045 void LogGeneratedCodeCoverage(const char* file_line) {
3046 const char* return_address = (&file_line)[-1];
3047 char* push_insn = const_cast<char*>(return_address - 12);
3048 push_insn[0] = 0xeb; // Relative branch insn.
3049 push_insn[1] = 13; // Skip over coverage insns.
3050 if (coverage_log != NULL) {
3051 fprintf(coverage_log, "%s\n", file_line);
3052 fflush(coverage_log);
3058 } } // namespace v8::internal
3060 #endif // V8_TARGET_ARCH_IA32